[deliverable/linux.git] / arch / sh / boards / mach-migor / setup.c

/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/i2c.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <media/ov772x.h>
#include <media/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/sh_keysc.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 32, /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 79,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->IO_ADDR_W);
}

static int migor_nand_flash_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_cfg = {
			.name = "LB070WV1",
			.xres = 800,
			.yres = 480,
			.left_margin = 64,
			.right_margin = 16,
			.hsync_len = 120,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = 0,
		},
		.lcd_size_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#endif
#ifdef CONFIG_SH_MIGOR_QVGA
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_cfg = {
			.name = "PH240320T",
			.xres = 320,
			.yres = 240,
			.left_margin = 0,
			.right_margin = 16,
			.hsync_len = 8,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = FB_SYNC_HOR_HIGH_ACT,
		},
		.lcd_size_cfg = { /* 2.4 inch */
			.width = 49,
			.height = 37,
		},
		.board_cfg = {
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe941fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
};

static struct clk *camera_clk;
static DEFINE_MUTEX(camera_lock);

static void camera_power_on(int is_tw)
{
	mutex_lock(&camera_lock);

	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	 * around signal quality issues on Panel Board V2.1.
	 */
	camera_clk = clk_get(NULL, "video_clk");
	clk_set_rate(camera_clk, 10000000);
	clk_enable(camera_clk);	/* start VIO_CKO */

	/* use VIO_RST to take camera out of reset */
	mdelay(10);
	if (is_tw) {
		gpio_set_value(GPIO_PTT2, 0);
		gpio_set_value(GPIO_PTT0, 0);
	} else {
		gpio_set_value(GPIO_PTT0, 1);
	}
	gpio_set_value(GPIO_PTT3, 0);
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 1);
	mdelay(10); /* wait to let chip come out of reset */
}

static void camera_power_off(void)
{
	clk_disable(camera_clk); /* stop VIO_CKO */
	clk_put(camera_clk);

	gpio_set_value(GPIO_PTT3, 0);
	mutex_unlock(&camera_lock);
}

static int ov7725_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(0);
	else
		camera_power_off();

	return 0;
}

static int tw9910_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(1);
	else
		camera_power_off();

	return 0;
}

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &sh_mobile_ceu_info,
	},
};

static struct ov772x_camera_info ov7725_info = {
	.buswidth  = SOCAM_DATAWIDTH_8,
	.link = {
		.power  = ov7725_power,
	},
};

static struct tw9910_video_info tw9910_info = {
	.buswidth = SOCAM_DATAWIDTH_8,
	.mpout    = TW9910_MPO_FIELD,
	.link = {
		.power  = tw9910_power,
	}
};

struct spi_gpio_platform_data sdcard_cn9_platform_data = {
	.sck = GPIO_PTD0,
	.mosi = GPIO_PTD1,
	.miso = GPIO_PTD2,
	.num_chipselect = 1,
};

static struct platform_device sdcard_cn9_device = {
	.name		= "spi_gpio",
	.dev	= {
		.platform_data	= &sdcard_cn9_platform_data,
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_ceu_device,
	&migor_nor_flash_device,
	&migor_nand_flash_device,
	&sdcard_cn9_device,
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = 38, /* IRQ6 */
	},
	{
		I2C_BOARD_INFO("ov772x", 0x21),
		.platform_data = &ov7725_info.link,
	},
	{
		I2C_BOARD_INFO("tw9910", 0x45),
		.platform_data = &tw9910_info.link,
	},
};

static struct spi_board_info migor_spi_devices[] = {
	{
		.modalias = "mmc_spi",
		.max_speed_hz = 5000000,
		.chip_select = 0,
		.controller_data = (void *) GPIO_PTD5,
	},
};

static int __init migor_devices_setup(void)
{

#ifdef CONFIG_PM
	/* Let D11 LED show STATUS0 */
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* Lit D12 LED show PDSTATUS */
	gpio_request(GPIO_FN_PDSTATUS, NULL);
#else
	/* Lit D11 LED */
	gpio_request(GPIO_PTJ7, NULL);
	gpio_direction_output(GPIO_PTJ7, 1);
	gpio_export(GPIO_PTJ7, 0);

	/* Lit D12 LED */
	gpio_request(GPIO_PTJ5, NULL);
	gpio_direction_output(GPIO_PTJ5, 1);
	gpio_export(GPIO_PTJ5, 0);
#endif

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	ctrl_outl(0x00003400, BSC_CS4BCR);
	ctrl_outl(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	gpio_direction_output(GPIO_PTT3, 0);
	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	gpio_direction_output(GPIO_PTT2, 1);
	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	gpio_direction_output(GPIO_PTT0, 0);
#else
	gpio_direction_output(GPIO_PTT0, 1);
#endif
	ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	spi_register_board_info(migor_spi_devices,
				ARRAY_SIZE(migor_spi_devices));

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);

/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=0: Test Mode Disabled
	 */
	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_migor __initmv = {
	.mv_name		= "Migo-R",
	.mv_mode_pins		= migor_mode_pins,
};
Commit	Line	Data
70f784ec MD	1	/*
	2	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
92cfeb61	13	#include <linux/input.h>
b8808786	14	#include <linux/mtd/physmap.h>
3c803a9a	15	#include <linux/mtd/nand.h>
0c6111ec	16	#include <linux/i2c.h>
8a3ee0fc	17	#include <linux/smc91x.h>
1765534c MD	18	#include <linux/delay.h>
1765534c MD	19	#include <linux/clk.h>
91b6f3c5	20	#include <linux/gpio.h>
70e5c4f0 MD	21	#include <linux/spi/spi.h>
	22	#include <linux/spi/spi_gpio.h>
	23	#include <video/sh_mobile_lcdc.h>
1765534c	24	#include <media/sh_mobile_ceu.h>
ff04ea40	25	#include <media/ov772x.h>
deae7b86	26	#include <media/tw9910.h>
6c7d826c	27	#include <asm/clock.h>
70f784ec MD	28	#include <asm/machvec.h>
70f784ec MD	29	#include <asm/io.h>
92cfeb61	30	#include <asm/sh_keysc.h>
7639a454	31	#include <mach/migor.h>
f7275650	32	#include <cpu/sh7722.h>
70f784ec MD	33
	34	/* Address IRQ Size Bus Description
	35	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	36	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	37	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	38	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	39	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	40	*/
	41
8a3ee0fc	42	static struct smc91x_platdata smc91x_info = {
a30c89ad	43	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	44	};
8a3ee0fc MD	45
70f784ec MD	46	static struct resource smc91x_eth_resources[] = {
70f784ec MD	47	[0] = {
b026a23c MD	48	.name = "SMC91C111" ,
	49	.start = 0x10000300,
	50	.end = 0x1000030f,
70f784ec MD	51	.flags = IORESOURCE_MEM,
	52	},
	53	[1] = {
	54	.start = 32, /* IRQ0 */
d280eadc	55	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	56	},
	57	};
	58
	59	static struct platform_device smc91x_eth_device = {
	60	.name = "smc91x",
	61	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	62	.resource = smc91x_eth_resources,
8a3ee0fc MD	63	.dev = {
	64	.platform_data = &smc91x_info,
	65	},
70f784ec MD	66	};
70f784ec MD	67
92cfeb61 MD	68	static struct sh_keysc_info sh_keysc_info = {
	69	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	70	.scan_timing = 3,
	71	.delay = 5,
	72	.keycodes = {
	73	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	74	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	75	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	76	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	77	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	78	},
	79	};
	80
	81	static struct resource sh_keysc_resources[] = {
	82	[0] = {
	83	.start = 0x044b0000,
	84	.end = 0x044b000f,
	85	.flags = IORESOURCE_MEM,
	86	},
	87	[1] = {
	88	.start = 79,
	89	.flags = IORESOURCE_IRQ,
	90	},
	91	};
	92
	93	static struct platform_device sh_keysc_device = {
	94	.name = "sh_keysc",
090d951b	95	.id = 0, /* "keysc0" clock */
92cfeb61 MD	96	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	97	.resource = sh_keysc_resources,
	98	.dev = {
	99	.platform_data = &sh_keysc_info,
	100	},
	101	};
	102
b8808786 MD	103	static struct mtd_partition migor_nor_flash_partitions[] =
	104	{
	105	{
	106	.name = "uboot",
	107	.offset = 0,
	108	.size = (1 * 1024 * 1024),
	109	.mask_flags = MTD_WRITEABLE, /* Read-only */
	110	},
	111	{
	112	.name = "rootfs",
	113	.offset = MTDPART_OFS_APPEND,
	114	.size = (15 * 1024 * 1024),
	115	},
	116	{
	117	.name = "other",
	118	.offset = MTDPART_OFS_APPEND,
	119	.size = MTDPART_SIZ_FULL,
	120	},
	121	};
	122
	123	static struct physmap_flash_data migor_nor_flash_data = {
	124	.width = 2,
	125	.parts = migor_nor_flash_partitions,
	126	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	127	};
	128
	129	static struct resource migor_nor_flash_resources[] = {
	130	[0] = {
	131	.name = "NOR Flash",
	132	.start = 0x00000000,
	133	.end = 0x03ffffff,
	134	.flags = IORESOURCE_MEM,
	135	}
	136	};
	137
	138	static struct platform_device migor_nor_flash_device = {
	139	.name = "physmap-flash",
	140	.resource = migor_nor_flash_resources,
	141	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	142	.dev = {
	143	.platform_data = &migor_nor_flash_data,
	144	},
	145	};
	146
3c803a9a MD	147	static struct mtd_partition migor_nand_flash_partitions[] = {
	148	{
	149	.name = "nanddata1",
	150	.offset = 0x0,
	151	.size = 512 * 1024 * 1024,
	152	},
	153	{
	154	.name = "nanddata2",
	155	.offset = MTDPART_OFS_APPEND,
	156	.size = 512 * 1024 * 1024,
	157	},
	158	};
	159
	160	static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
	161	unsigned int ctrl)
	162	{
	163	struct nand_chip *chip = mtd->priv;
	164
	165	if (cmd == NAND_CMD_NONE)
	166	return;
	167
	168	if (ctrl & NAND_CLE)
	169	writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	170	else if (ctrl & NAND_ALE)
	171	writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	172	else
	173	writeb(cmd, chip->IO_ADDR_W);
	174	}
	175
	176	static int migor_nand_flash_ready(struct mtd_info *mtd)
	177	{
91b6f3c5	178	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	179	}
	180
	181	struct platform_nand_data migor_nand_flash_data = {
	182	.chip = {
	183	.nr_chips = 1,
	184	.partitions = migor_nand_flash_partitions,
	185	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	186	.chip_delay = 20,
	187	.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	188	},
	189	.ctrl = {
	190	.dev_ready = migor_nand_flash_ready,
	191	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	192	},
	193	};
	194
	195	static struct resource migor_nand_flash_resources[] = {
	196	[0] = {
	197	.name = "NAND Flash",
	198	.start = 0x18000000,
	199	.end = 0x18ffffff,
	200	.flags = IORESOURCE_MEM,
	201	},
	202	};
	203
	204	static struct platform_device migor_nand_flash_device = {
	205	.name = "gen_nand",
	206	.resource = migor_nand_flash_resources,
	207	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	208	.dev = {
	209	.platform_data = &migor_nand_flash_data,
	210	}
	211	};
	212
8b1285f1 MD	213	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
	214	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	215	.clock_source = LCDC_CLK_BUS,
	216	.ch[0] = {
	217	.chan = LCDC_CHAN_MAINLCD,
	218	.bpp = 16,
	219	.interface_type = RGB16,
	220	.clock_divider = 2,
	221	.lcd_cfg = {
	222	.name = "LB070WV1",
	223	.xres = 800,
	224	.yres = 480,
	225	.left_margin = 64,
	226	.right_margin = 16,
	227	.hsync_len = 120,
	228	.upper_margin = 1,
	229	.lower_margin = 17,
	230	.vsync_len = 2,
	231	.sync = 0,
	232	},
ce9c008c MD	233	.lcd_size_cfg = { /* 7.0 inch */
	234	.width = 152,
	235	.height = 91,
	236	},
8b1285f1 MD	237	}
	238	#endif
	239	#ifdef CONFIG_SH_MIGOR_QVGA
	240	.clock_source = LCDC_CLK_PERIPHERAL,
	241	.ch[0] = {
	242	.chan = LCDC_CHAN_MAINLCD,
	243	.bpp = 16,
	244	.interface_type = SYS16A,
	245	.clock_divider = 10,
	246	.lcd_cfg = {
	247	.name = "PH240320T",
	248	.xres = 320,
	249	.yres = 240,
	250	.left_margin = 0,
	251	.right_margin = 16,
	252	.hsync_len = 8,
	253	.upper_margin = 1,
	254	.lower_margin = 17,
	255	.vsync_len = 2,
	256	.sync = FB_SYNC_HOR_HIGH_ACT,
	257	},
ce9c008c MD	258	.lcd_size_cfg = { /* 2.4 inch */
	259	.width = 49,
	260	.height = 37,
	261	},
8b1285f1 MD	262	.board_cfg = {
	263	.setup_sys = migor_lcd_qvga_setup,
	264	},
	265	.sys_bus_cfg = {
	266	.ldmt2r = 0x06000a09,
	267	.ldmt3r = 0x180e3418,
b5868e8c MD	268	/* set 1s delay to encourage fsync() */
b5868e8c MD	269	.deferred_io_msec = 1000,
8b1285f1 MD	270	},
	271	}
	272	#endif
	273	};
	274
	275	static struct resource migor_lcdc_resources[] = {
	276	[0] = {
	277	.name = "LCDC",
	278	.start = 0xfe940000, /* P4-only space */
	279	.end = 0xfe941fff,
	280	.flags = IORESOURCE_MEM,
	281	},
07905554 MD	282	[1] = {
	283	.start = 28,
	284	.flags = IORESOURCE_IRQ,
	285	},
8b1285f1 MD	286	};
	287
	288	static struct platform_device migor_lcdc_device = {
	289	.name = "sh_mobile_lcdc_fb",
	290	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	291	.resource = migor_lcdc_resources,
	292	.dev = {
	293	.platform_data = &sh_mobile_lcdc_info,
	294	},
	295	};
	296
1765534c	297	static struct clk *camera_clk;
deae7b86	298	static DEFINE_MUTEX(camera_lock);
1765534c	299
deae7b86	300	static void camera_power_on(int is_tw)
1765534c	301	{
deae7b86 KM	302	mutex_lock(&camera_lock);
deae7b86 KM	303
22ee3ba6 MD	304	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	305	* around signal quality issues on Panel Board V2.1.
	306	*/
1765534c	307	camera_clk = clk_get(NULL, "video_clk");
22ee3ba6	308	clk_set_rate(camera_clk, 10000000);
1765534c MD	309	clk_enable(camera_clk); /* start VIO_CKO */
1765534c MD	310
91b6f3c5	311	/* use VIO_RST to take camera out of reset */
1765534c	312	mdelay(10);
deae7b86 KM	313	if (is_tw) {
	314	gpio_set_value(GPIO_PTT2, 0);
	315	gpio_set_value(GPIO_PTT0, 0);
	316	} else {
	317	gpio_set_value(GPIO_PTT0, 1);
	318	}
91b6f3c5	319	gpio_set_value(GPIO_PTT3, 0);
1765534c	320	mdelay(10);
91b6f3c5	321	gpio_set_value(GPIO_PTT3, 1);
4545bfa0	322	mdelay(10); /* wait to let chip come out of reset */
1765534c MD	323	}
	324
	325	static void camera_power_off(void)
	326	{
	327	clk_disable(camera_clk); /* stop VIO_CKO */
	328	clk_put(camera_clk);
	329
91b6f3c5	330	gpio_set_value(GPIO_PTT3, 0);
deae7b86	331	mutex_unlock(&camera_lock);
1765534c MD	332	}
1765534c MD	333
ff04ea40 KM	334	static int ov7725_power(struct device *dev, int mode)
	335	{
	336	if (mode)
deae7b86 KM	337	camera_power_on(0);
	338	else
	339	camera_power_off();
	340
	341	return 0;
	342	}
	343
	344	static int tw9910_power(struct device *dev, int mode)
	345	{
	346	if (mode)
	347	camera_power_on(1);
ff04ea40 KM	348	else
	349	camera_power_off();
	350
	351	return 0;
	352	}
	353
1765534c	354	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
64935056	355	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
1765534c MD	356	};
	357
	358	static struct resource migor_ceu_resources[] = {
	359	[0] = {
	360	.name = "CEU",
	361	.start = 0xfe910000,
	362	.end = 0xfe91009f,
	363	.flags = IORESOURCE_MEM,
	364	},
	365	[1] = {
	366	.start = 52,
	367	.flags = IORESOURCE_IRQ,
	368	},
	369	[2] = {
	370	/* place holder for contiguous memory */
	371	},
	372	};
	373
	374	static struct platform_device migor_ceu_device = {
	375	.name = "sh_mobile_ceu",
a42b6dd6	376	.id = 0, /* "ceu0" clock */
1765534c MD	377	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	378	.resource = migor_ceu_resources,
	379	.dev = {
	380	.platform_data = &sh_mobile_ceu_info,
	381	},
	382	};
	383
ff04ea40 KM	384	static struct ov772x_camera_info ov7725_info = {
	385	.buswidth = SOCAM_DATAWIDTH_8,
	386	.link = {
	387	.power = ov7725_power,
	388	},
	389	};
	390
deae7b86 KM	391	static struct tw9910_video_info tw9910_info = {
	392	.buswidth = SOCAM_DATAWIDTH_8,
	393	.mpout = TW9910_MPO_FIELD,
	394	.link = {
	395	.power = tw9910_power,
	396	}
	397	};
	398
70e5c4f0 MD	399	struct spi_gpio_platform_data sdcard_cn9_platform_data = {
	400	.sck = GPIO_PTD0,
	401	.mosi = GPIO_PTD1,
	402	.miso = GPIO_PTD2,
	403	.num_chipselect = 1,
	404	};
	405
	406	static struct platform_device sdcard_cn9_device = {
	407	.name = "spi_gpio",
	408	.dev = {
	409	.platform_data = &sdcard_cn9_platform_data,
	410	},
	411	};
	412
70f784ec MD	413	static struct platform_device *migor_devices[] __initdata = {
70f784ec MD	414	&smc91x_eth_device,
92cfeb61	415	&sh_keysc_device,
8b1285f1	416	&migor_lcdc_device,
1765534c	417	&migor_ceu_device,
b8808786	418	&migor_nor_flash_device,
3c803a9a	419	&migor_nand_flash_device,
70e5c4f0	420	&sdcard_cn9_device,
70f784ec MD	421	};
70f784ec MD	422
1765534c	423	static struct i2c_board_info migor_i2c_devices[] = {
57795867	424	{
3760f736	425	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	426	},
67908abf MD	427	{
	428	I2C_BOARD_INFO("migor_ts", 0x51),
	429	.irq = 38, /* IRQ6 */
	430	},
ff04ea40 KM	431	{
ff04ea40 KM	432	I2C_BOARD_INFO("ov772x", 0x21),
0a861e9e	433	.platform_data = &ov7725_info.link,
ff04ea40	434	},
deae7b86 KM	435	{
deae7b86 KM	436	I2C_BOARD_INFO("tw9910", 0x45),
0a861e9e	437	.platform_data = &tw9910_info.link,
deae7b86	438	},
0c6111ec MD	439	};
0c6111ec MD	440
70e5c4f0 MD	441	static struct spi_board_info migor_spi_devices[] = {
	442	{
	443	.modalias = "mmc_spi",
	444	.max_speed_hz = 5000000,
	445	.chip_select = 0,
	446	.controller_data = (void *) GPIO_PTD5,
	447	},
	448	};
	449
70f784ec MD	450	static int __init migor_devices_setup(void)
70f784ec MD	451	{
50840714 MD	452
	453	#ifdef CONFIG_PM
	454	/* Let D11 LED show STATUS0 */
	455	gpio_request(GPIO_FN_STATUS0, NULL);
	456
	457	/* Lit D12 LED show PDSTATUS */
	458	gpio_request(GPIO_FN_PDSTATUS, NULL);
	459	#else
91b6f3c5 MD	460	/* Lit D11 LED */
	461	gpio_request(GPIO_PTJ7, NULL);
	462	gpio_direction_output(GPIO_PTJ7, 1);
	463	gpio_export(GPIO_PTJ7, 0);
	464
	465	/* Lit D12 LED */
	466	gpio_request(GPIO_PTJ5, NULL);
	467	gpio_direction_output(GPIO_PTJ5, 1);
	468	gpio_export(GPIO_PTJ5, 0);
50840714	469	#endif
91b6f3c5	470
a30c89ad	471	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	472	gpio_request(GPIO_FN_IRQ0, NULL);
a30c89ad MD	473	ctrl_outl(0x00003400, BSC_CS4BCR);
a30c89ad MD	474	ctrl_outl(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	475
91b6f3c5 MD	476	/* KEYSC */
91b6f3c5 MD	477	gpio_request(GPIO_FN_KEYOUT0, NULL);
	478	gpio_request(GPIO_FN_KEYOUT1, NULL);
	479	gpio_request(GPIO_FN_KEYOUT2, NULL);
	480	gpio_request(GPIO_FN_KEYOUT3, NULL);
	481	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	482	gpio_request(GPIO_FN_KEYIN1, NULL);
	483	gpio_request(GPIO_FN_KEYIN2, NULL);
	484	gpio_request(GPIO_FN_KEYIN3, NULL);
	485	gpio_request(GPIO_FN_KEYIN4, NULL);
	486	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	487
	488	/* NAND Flash */
	489	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	490	ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
	491	gpio_request(GPIO_PTA1, NULL);
	492	gpio_direction_input(GPIO_PTA1);
	493
	494	/* Touch Panel */
	495	gpio_request(GPIO_FN_IRQ6, NULL);
	496
	497	/* LCD Panel */
91b6f3c5 MD	498	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	499	gpio_request(GPIO_FN_LCDD17, NULL);
	500	gpio_request(GPIO_FN_LCDD16, NULL);
	501	gpio_request(GPIO_FN_LCDD15, NULL);
	502	gpio_request(GPIO_FN_LCDD14, NULL);
	503	gpio_request(GPIO_FN_LCDD13, NULL);
	504	gpio_request(GPIO_FN_LCDD12, NULL);
	505	gpio_request(GPIO_FN_LCDD11, NULL);
	506	gpio_request(GPIO_FN_LCDD10, NULL);
	507	gpio_request(GPIO_FN_LCDD8, NULL);
	508	gpio_request(GPIO_FN_LCDD7, NULL);
	509	gpio_request(GPIO_FN_LCDD6, NULL);
	510	gpio_request(GPIO_FN_LCDD5, NULL);
	511	gpio_request(GPIO_FN_LCDD4, NULL);
	512	gpio_request(GPIO_FN_LCDD3, NULL);
	513	gpio_request(GPIO_FN_LCDD2, NULL);
	514	gpio_request(GPIO_FN_LCDD1, NULL);
	515	gpio_request(GPIO_FN_LCDRS, NULL);
	516	gpio_request(GPIO_FN_LCDCS, NULL);
	517	gpio_request(GPIO_FN_LCDRD, NULL);
	518	gpio_request(GPIO_FN_LCDWR, NULL);
	519	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	520	gpio_direction_output(GPIO_PTH2, 1);
	521	#endif
	522	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	523	gpio_request(GPIO_FN_LCDD15, NULL);
	524	gpio_request(GPIO_FN_LCDD14, NULL);
	525	gpio_request(GPIO_FN_LCDD13, NULL);
	526	gpio_request(GPIO_FN_LCDD12, NULL);
	527	gpio_request(GPIO_FN_LCDD11, NULL);
	528	gpio_request(GPIO_FN_LCDD10, NULL);
	529	gpio_request(GPIO_FN_LCDD9, NULL);
	530	gpio_request(GPIO_FN_LCDD8, NULL);
	531	gpio_request(GPIO_FN_LCDD7, NULL);
	532	gpio_request(GPIO_FN_LCDD6, NULL);
	533	gpio_request(GPIO_FN_LCDD5, NULL);
	534	gpio_request(GPIO_FN_LCDD4, NULL);
	535	gpio_request(GPIO_FN_LCDD3, NULL);
	536	gpio_request(GPIO_FN_LCDD2, NULL);
	537	gpio_request(GPIO_FN_LCDD1, NULL);
	538	gpio_request(GPIO_FN_LCDD0, NULL);
	539	gpio_request(GPIO_FN_LCDLCLK, NULL);
	540	gpio_request(GPIO_FN_LCDDCK, NULL);
	541	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	542	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	543	gpio_request(GPIO_FN_LCDVSYN, NULL);
	544	gpio_request(GPIO_FN_LCDHSYN, NULL);
	545	gpio_request(GPIO_FN_LCDDISP, NULL);
	546	gpio_request(GPIO_FN_LCDDON, NULL);
	547	#endif
	548
	549	/* CEU */
91b6f3c5 MD	550	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	551	gpio_request(GPIO_FN_VIO_VD2, NULL);
	552	gpio_request(GPIO_FN_VIO_HD2, NULL);
	553	gpio_request(GPIO_FN_VIO_FLD, NULL);
	554	gpio_request(GPIO_FN_VIO_CKO, NULL);
	555	gpio_request(GPIO_FN_VIO_D15, NULL);
	556	gpio_request(GPIO_FN_VIO_D14, NULL);
	557	gpio_request(GPIO_FN_VIO_D13, NULL);
	558	gpio_request(GPIO_FN_VIO_D12, NULL);
	559	gpio_request(GPIO_FN_VIO_D11, NULL);
	560	gpio_request(GPIO_FN_VIO_D10, NULL);
	561	gpio_request(GPIO_FN_VIO_D9, NULL);
	562	gpio_request(GPIO_FN_VIO_D8, NULL);
	563
	564	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	565	gpio_direction_output(GPIO_PTT3, 0);
	566	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	567	gpio_direction_output(GPIO_PTT2, 1);
	568	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
	569	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	570	gpio_direction_output(GPIO_PTT0, 0);
	571	#else
	572	gpio_direction_output(GPIO_PTT0, 1);
	573	#endif
	574	ctrl_outw(ctrl_inw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c MD	575
1765534c MD	576	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c	577
0c6111ec MD	578	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	579	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	580
70e5c4f0 MD	581	spi_register_board_info(migor_spi_devices,
	582	ARRAY_SIZE(migor_spi_devices));
	583
70f784ec MD	584	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
	585	}
	586	__initcall(migor_devices_setup);
0ec80fdd MD	587
	588	/* Return the board specific boot mode pin configuration */
	589	static int migor_mode_pins(void)
	590	{
	591	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	592	* MD3=0: 16-bit Area0 Bus Width
	593	* MD5=1: Little Endian
	594	* TSTMD=1, MD8=0: Test Mode Disabled
	595	*/
	596	return MODE_PIN0 \| MODE_PIN1 \| MODE_PIN5;
	597	}
	598
	599	/*
	600	* The Machine Vector
	601	*/
	602	static struct sh_machine_vector mv_migor __initmv = {
	603	.mv_name = "Migo-R",
	604	.mv_mode_pins = migor_mode_pins,
	605	};