[deliverable/linux.git] / arch / sh / boards / mach-migor / setup.c

/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/i2c.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <media/soc_camera_platform.h>
#include <media/sh_mobile_ceu.h>
#include <video/sh_mobile_lcdc.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/sh_keysc.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 32, /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 79,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->IO_ADDR_W);
}

static int migor_nand_flash_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_cfg = {
			.name = "LB070WV1",
			.xres = 800,
			.yres = 480,
			.left_margin = 64,
			.right_margin = 16,
			.hsync_len = 120,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = 0,
		},
		.lcd_size_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#endif
#ifdef CONFIG_SH_MIGOR_QVGA
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_cfg = {
			.name = "PH240320T",
			.xres = 320,
			.yres = 240,
			.left_margin = 0,
			.right_margin = 16,
			.hsync_len = 8,
			.upper_margin = 1,
			.lower_margin = 17,
			.vsync_len = 2,
			.sync = FB_SYNC_HOR_HIGH_ACT,
		},
		.lcd_size_cfg = { /* 2.4 inch */
			.width = 49,
			.height = 37,
		},
		.board_cfg = {
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe941fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
};

static struct clk *camera_clk;

static void camera_power_on(void)
{
	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	 * around signal quality issues on Panel Board V2.1.
	 */
	camera_clk = clk_get(NULL, "video_clk");
	clk_set_rate(camera_clk, 10000000);
	clk_enable(camera_clk);	/* start VIO_CKO */

	/* use VIO_RST to take camera out of reset */
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 0);
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 1);
	mdelay(10); /* wait to let chip come out of reset */
}

static void camera_power_off(void)
{
	clk_disable(camera_clk); /* stop VIO_CKO */
	clk_put(camera_clk);

	gpio_set_value(GPIO_PTT3, 0);
}

static void camera_power(int mode)
{
	if (mode)
		camera_power_on();
	else
		camera_power_off();
}

#ifdef CONFIG_I2C
static unsigned char camera_ov772x_magic[] =
{
	0x09, 0x01, 0x0c, 0x20, 0x0d, 0x41, 0x0e, 0x01,
	0x12, 0x00, 0x13, 0x8F, 0x14, 0x4A, 0x15, 0x00,
	0x16, 0x00, 0x17, 0x23, 0x18, 0xa0, 0x19, 0x07,
	0x1a, 0xf0, 0x1b, 0x40, 0x1f, 0x00, 0x20, 0x10,
	0x22, 0xff, 0x23, 0x01, 0x28, 0x00, 0x29, 0xa0,
	0x2a, 0x00, 0x2b, 0x00, 0x2c, 0xf0, 0x2d, 0x00,
	0x2e, 0x00, 0x30, 0x80, 0x31, 0x60, 0x32, 0x00,
	0x33, 0x00, 0x34, 0x00, 0x3d, 0x80, 0x3e, 0xe2,
	0x3f, 0x1f, 0x42, 0x80, 0x43, 0x80, 0x44, 0x80,
	0x45, 0x80, 0x46, 0x00, 0x47, 0x00, 0x48, 0x00,
	0x49, 0x50, 0x4a, 0x30, 0x4b, 0x50, 0x4c, 0x50,
	0x4d, 0x00, 0x4e, 0xef, 0x4f, 0x10, 0x50, 0x60,
	0x51, 0x00, 0x52, 0x00, 0x53, 0x24, 0x54, 0x7a,
	0x55, 0xfc, 0x62, 0xff, 0x63, 0xf0, 0x64, 0x1f,
	0x65, 0x00, 0x66, 0x10, 0x67, 0x00, 0x68, 0x00,
	0x69, 0x5c, 0x6a, 0x11, 0x6b, 0xa2, 0x6c, 0x01,
	0x6d, 0x50, 0x6e, 0x80, 0x6f, 0x80, 0x70, 0x0f,
	0x71, 0x00, 0x72, 0x00, 0x73, 0x0f, 0x74, 0x0f,
	0x75, 0xff, 0x78, 0x10, 0x79, 0x70, 0x7a, 0x70,
	0x7b, 0xf0, 0x7c, 0xf0, 0x7d, 0xf0, 0x7e, 0x0e,
	0x7f, 0x1a, 0x80, 0x31, 0x81, 0x5a, 0x82, 0x69,
	0x83, 0x75, 0x84, 0x7e, 0x85, 0x88, 0x86, 0x8f,
	0x87, 0x96, 0x88, 0xa3, 0x89, 0xaf, 0x8a, 0xc4,
	0x8b, 0xd7, 0x8c, 0xe8, 0x8d, 0x20, 0x8e, 0x00,
	0x8f, 0x00, 0x90, 0x08, 0x91, 0x10, 0x92, 0x1f,
	0x93, 0x01, 0x94, 0x2c, 0x95, 0x24, 0x96, 0x08,
	0x97, 0x14, 0x98, 0x24, 0x99, 0x38, 0x9a, 0x9e,
	0x9b, 0x00, 0x9c, 0x40, 0x9e, 0x11, 0x9f, 0x02,
	0xa0, 0x00, 0xa1, 0x40, 0xa2, 0x40, 0xa3, 0x06,
	0xa4, 0x00, 0xa6, 0x00, 0xa7, 0x40, 0xa8, 0x40,
	0xa9, 0x80, 0xaa, 0x80, 0xab, 0x06, 0xac, 0xff,
	0x12, 0x06, 0x64, 0x3f, 0x12, 0x46, 0x17, 0x3f,
	0x18, 0x50, 0x19, 0x03, 0x1a, 0x78, 0x29, 0x50,
	0x2c, 0x78,
};

static int ov772x_set_capture(struct soc_camera_platform_info *info,
			      int enable)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	int ret = 0;
	int i;

	if (!enable)
		return 0; /* camera_power_off() is enough */

	for (i = 0; i < ARRAY_SIZE(camera_ov772x_magic); i += 2) {
		u_int8_t buf[8];

		msg.addr = 0x21;
		msg.buf = buf;
		msg.len = 2;
		msg.flags = 0;

		buf[0] = camera_ov772x_magic[i];
		buf[1] = camera_ov772x_magic[i + 1];

		ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	}

	return ret;
}

static struct soc_camera_platform_info ov772x_info = {
	.iface = 0,
	.format_name = "RGB565",
	.format_depth = 16,
	.format = {
		.pixelformat = V4L2_PIX_FMT_RGB565,
		.colorspace = V4L2_COLORSPACE_SRGB,
		.width = 320,
		.height = 240,
	},
	.bus_param =  SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
	SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
	.power = camera_power,
	.set_capture = ov772x_set_capture,
};

static struct platform_device migor_camera_device = {
	.name		= "soc_camera_platform",
	.dev	= {
		.platform_data	= &ov772x_info,
	},
};
#endif /* CONFIG_I2C */

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SOCAM_MASTER | SOCAM_DATAWIDTH_8 | SOCAM_PCLK_SAMPLE_RISING \
	| SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH,
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &sh_mobile_ceu_info,
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_ceu_device,
#ifdef CONFIG_I2C
	&migor_camera_device,
#endif
	&migor_nor_flash_device,
	&migor_nand_flash_device,
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = 38, /* IRQ6 */
	},
};

static int __init migor_devices_setup(void)
{
	/* Lit D11 LED */
	gpio_request(GPIO_PTJ7, NULL);
	gpio_direction_output(GPIO_PTJ7, 1);
	gpio_export(GPIO_PTJ7, 0);

	/* Lit D12 LED */
	gpio_request(GPIO_PTJ5, NULL);
	gpio_direction_output(GPIO_PTJ5, 1);
	gpio_export(GPIO_PTJ5, 0);

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	ctrl_outl(0x00003400, BSC_CS4BCR);
	ctrl_outl(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	gpio_direction_output(GPIO_PTT3, 0);
	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	gpio_direction_output(GPIO_PTT2, 1);
	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	gpio_direction_output(GPIO_PTT0, 0);
#else
	gpio_direction_output(GPIO_PTT0, 1);
#endif
	ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);
Commit	Line	Data
70f784ec MD	1	/*
	2	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
92cfeb61	13	#include <linux/input.h>
b8808786	14	#include <linux/mtd/physmap.h>
3c803a9a	15	#include <linux/mtd/nand.h>
0c6111ec	16	#include <linux/i2c.h>
8a3ee0fc	17	#include <linux/smc91x.h>
1765534c MD	18	#include <linux/delay.h>
1765534c MD	19	#include <linux/clk.h>
91b6f3c5	20	#include <linux/gpio.h>
1765534c MD	21	#include <media/soc_camera_platform.h>
1765534c MD	22	#include <media/sh_mobile_ceu.h>
225c9a8d	23	#include <video/sh_mobile_lcdc.h>
6c7d826c	24	#include <asm/clock.h>
70f784ec MD	25	#include <asm/machvec.h>
70f784ec MD	26	#include <asm/io.h>
92cfeb61	27	#include <asm/sh_keysc.h>
7639a454	28	#include <mach/migor.h>
f7275650	29	#include <cpu/sh7722.h>
70f784ec MD	30
	31	/* Address IRQ Size Bus Description
	32	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	33	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	34	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	35	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	36	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	37	*/
	38
8a3ee0fc	39	static struct smc91x_platdata smc91x_info = {
a30c89ad	40	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	41	};
8a3ee0fc MD	42
70f784ec MD	43	static struct resource smc91x_eth_resources[] = {
70f784ec MD	44	[0] = {
b026a23c MD	45	.name = "SMC91C111" ,
	46	.start = 0x10000300,
	47	.end = 0x1000030f,
70f784ec MD	48	.flags = IORESOURCE_MEM,
	49	},
	50	[1] = {
	51	.start = 32, /* IRQ0 */
d280eadc	52	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	53	},
	54	};
	55
	56	static struct platform_device smc91x_eth_device = {
	57	.name = "smc91x",
	58	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	59	.resource = smc91x_eth_resources,
8a3ee0fc MD	60	.dev = {
	61	.platform_data = &smc91x_info,
	62	},
70f784ec MD	63	};
70f784ec MD	64
92cfeb61 MD	65	static struct sh_keysc_info sh_keysc_info = {
	66	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	67	.scan_timing = 3,
	68	.delay = 5,
	69	.keycodes = {
	70	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	71	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	72	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	73	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	74	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	75	},
	76	};
	77
	78	static struct resource sh_keysc_resources[] = {
	79	[0] = {
	80	.start = 0x044b0000,
	81	.end = 0x044b000f,
	82	.flags = IORESOURCE_MEM,
	83	},
	84	[1] = {
	85	.start = 79,
	86	.flags = IORESOURCE_IRQ,
	87	},
	88	};
	89
	90	static struct platform_device sh_keysc_device = {
	91	.name = "sh_keysc",
090d951b	92	.id = 0, /* "keysc0" clock */
92cfeb61 MD	93	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	94	.resource = sh_keysc_resources,
	95	.dev = {
	96	.platform_data = &sh_keysc_info,
	97	},
	98	};
	99
b8808786 MD	100	static struct mtd_partition migor_nor_flash_partitions[] =
	101	{
	102	{
	103	.name = "uboot",
	104	.offset = 0,
	105	.size = (1 * 1024 * 1024),
	106	.mask_flags = MTD_WRITEABLE, /* Read-only */
	107	},
	108	{
	109	.name = "rootfs",
	110	.offset = MTDPART_OFS_APPEND,
	111	.size = (15 * 1024 * 1024),
	112	},
	113	{
	114	.name = "other",
	115	.offset = MTDPART_OFS_APPEND,
	116	.size = MTDPART_SIZ_FULL,
	117	},
	118	};
	119
	120	static struct physmap_flash_data migor_nor_flash_data = {
	121	.width = 2,
	122	.parts = migor_nor_flash_partitions,
	123	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	124	};
	125
	126	static struct resource migor_nor_flash_resources[] = {
	127	[0] = {
	128	.name = "NOR Flash",
	129	.start = 0x00000000,
	130	.end = 0x03ffffff,
	131	.flags = IORESOURCE_MEM,
	132	}
	133	};
	134
	135	static struct platform_device migor_nor_flash_device = {
	136	.name = "physmap-flash",
	137	.resource = migor_nor_flash_resources,
	138	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	139	.dev = {
	140	.platform_data = &migor_nor_flash_data,
	141	},
	142	};
	143
3c803a9a MD	144	static struct mtd_partition migor_nand_flash_partitions[] = {
	145	{
	146	.name = "nanddata1",
	147	.offset = 0x0,
	148	.size = 512 * 1024 * 1024,
	149	},
	150	{
	151	.name = "nanddata2",
	152	.offset = MTDPART_OFS_APPEND,
	153	.size = 512 * 1024 * 1024,
	154	},
	155	};
	156
	157	static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
	158	unsigned int ctrl)
	159	{
	160	struct nand_chip *chip = mtd->priv;
	161
	162	if (cmd == NAND_CMD_NONE)
	163	return;
	164
	165	if (ctrl & NAND_CLE)
	166	writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	167	else if (ctrl & NAND_ALE)
	168	writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	169	else
	170	writeb(cmd, chip->IO_ADDR_W);
	171	}
	172
	173	static int migor_nand_flash_ready(struct mtd_info *mtd)
	174	{
91b6f3c5	175	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	176	}
	177
	178	struct platform_nand_data migor_nand_flash_data = {
	179	.chip = {
	180	.nr_chips = 1,
	181	.partitions = migor_nand_flash_partitions,
	182	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	183	.chip_delay = 20,
	184	.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	185	},
	186	.ctrl = {
	187	.dev_ready = migor_nand_flash_ready,
	188	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	189	},
	190	};
	191
	192	static struct resource migor_nand_flash_resources[] = {
	193	[0] = {
	194	.name = "NAND Flash",
	195	.start = 0x18000000,
	196	.end = 0x18ffffff,
	197	.flags = IORESOURCE_MEM,
	198	},
	199	};
	200
	201	static struct platform_device migor_nand_flash_device = {
	202	.name = "gen_nand",
	203	.resource = migor_nand_flash_resources,
	204	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	205	.dev = {
	206	.platform_data = &migor_nand_flash_data,
	207	}
	208	};
	209
8b1285f1 MD	210	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
	211	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	212	.clock_source = LCDC_CLK_BUS,
	213	.ch[0] = {
	214	.chan = LCDC_CHAN_MAINLCD,
	215	.bpp = 16,
	216	.interface_type = RGB16,
	217	.clock_divider = 2,
	218	.lcd_cfg = {
	219	.name = "LB070WV1",
	220	.xres = 800,
	221	.yres = 480,
	222	.left_margin = 64,
	223	.right_margin = 16,
	224	.hsync_len = 120,
	225	.upper_margin = 1,
	226	.lower_margin = 17,
	227	.vsync_len = 2,
	228	.sync = 0,
	229	},
ce9c008c MD	230	.lcd_size_cfg = { /* 7.0 inch */
	231	.width = 152,
	232	.height = 91,
	233	},
8b1285f1 MD	234	}
	235	#endif
	236	#ifdef CONFIG_SH_MIGOR_QVGA
	237	.clock_source = LCDC_CLK_PERIPHERAL,
	238	.ch[0] = {
	239	.chan = LCDC_CHAN_MAINLCD,
	240	.bpp = 16,
	241	.interface_type = SYS16A,
	242	.clock_divider = 10,
	243	.lcd_cfg = {
	244	.name = "PH240320T",
	245	.xres = 320,
	246	.yres = 240,
	247	.left_margin = 0,
	248	.right_margin = 16,
	249	.hsync_len = 8,
	250	.upper_margin = 1,
	251	.lower_margin = 17,
	252	.vsync_len = 2,
	253	.sync = FB_SYNC_HOR_HIGH_ACT,
	254	},
ce9c008c MD	255	.lcd_size_cfg = { /* 2.4 inch */
	256	.width = 49,
	257	.height = 37,
	258	},
8b1285f1 MD	259	.board_cfg = {
	260	.setup_sys = migor_lcd_qvga_setup,
	261	},
	262	.sys_bus_cfg = {
	263	.ldmt2r = 0x06000a09,
	264	.ldmt3r = 0x180e3418,
b5868e8c MD	265	/* set 1s delay to encourage fsync() */
b5868e8c MD	266	.deferred_io_msec = 1000,
8b1285f1 MD	267	},
	268	}
	269	#endif
	270	};
	271
	272	static struct resource migor_lcdc_resources[] = {
	273	[0] = {
	274	.name = "LCDC",
	275	.start = 0xfe940000, /* P4-only space */
	276	.end = 0xfe941fff,
	277	.flags = IORESOURCE_MEM,
	278	},
07905554 MD	279	[1] = {
	280	.start = 28,
	281	.flags = IORESOURCE_IRQ,
	282	},
8b1285f1 MD	283	};
	284
	285	static struct platform_device migor_lcdc_device = {
	286	.name = "sh_mobile_lcdc_fb",
	287	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	288	.resource = migor_lcdc_resources,
	289	.dev = {
	290	.platform_data = &sh_mobile_lcdc_info,
	291	},
	292	};
	293
1765534c MD	294	static struct clk *camera_clk;
	295
	296	static void camera_power_on(void)
	297	{
22ee3ba6 MD	298	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	299	* around signal quality issues on Panel Board V2.1.
	300	*/
1765534c	301	camera_clk = clk_get(NULL, "video_clk");
22ee3ba6	302	clk_set_rate(camera_clk, 10000000);
1765534c MD	303	clk_enable(camera_clk); /* start VIO_CKO */
1765534c MD	304
91b6f3c5	305	/* use VIO_RST to take camera out of reset */
1765534c	306	mdelay(10);
91b6f3c5	307	gpio_set_value(GPIO_PTT3, 0);
1765534c	308	mdelay(10);
91b6f3c5	309	gpio_set_value(GPIO_PTT3, 1);
4545bfa0	310	mdelay(10); /* wait to let chip come out of reset */
1765534c MD	311	}
	312
	313	static void camera_power_off(void)
	314	{
	315	clk_disable(camera_clk); /* stop VIO_CKO */
	316	clk_put(camera_clk);
	317
91b6f3c5	318	gpio_set_value(GPIO_PTT3, 0);
1765534c MD	319	}
1765534c MD	320
58419abd GL	321	static void camera_power(int mode)
	322	{
	323	if (mode)
	324	camera_power_on();
	325	else
	326	camera_power_off();
	327	}
	328
e565b518	329	#ifdef CONFIG_I2C
1765534c MD	330	static unsigned char camera_ov772x_magic[] =
1765534c MD	331	{
3b495513	332	0x09, 0x01, 0x0c, 0x20, 0x0d, 0x41, 0x0e, 0x01,
1765534c MD	333	0x12, 0x00, 0x13, 0x8F, 0x14, 0x4A, 0x15, 0x00,
	334	0x16, 0x00, 0x17, 0x23, 0x18, 0xa0, 0x19, 0x07,
	335	0x1a, 0xf0, 0x1b, 0x40, 0x1f, 0x00, 0x20, 0x10,
	336	0x22, 0xff, 0x23, 0x01, 0x28, 0x00, 0x29, 0xa0,
	337	0x2a, 0x00, 0x2b, 0x00, 0x2c, 0xf0, 0x2d, 0x00,
	338	0x2e, 0x00, 0x30, 0x80, 0x31, 0x60, 0x32, 0x00,
	339	0x33, 0x00, 0x34, 0x00, 0x3d, 0x80, 0x3e, 0xe2,
	340	0x3f, 0x1f, 0x42, 0x80, 0x43, 0x80, 0x44, 0x80,
	341	0x45, 0x80, 0x46, 0x00, 0x47, 0x00, 0x48, 0x00,
	342	0x49, 0x50, 0x4a, 0x30, 0x4b, 0x50, 0x4c, 0x50,
	343	0x4d, 0x00, 0x4e, 0xef, 0x4f, 0x10, 0x50, 0x60,
	344	0x51, 0x00, 0x52, 0x00, 0x53, 0x24, 0x54, 0x7a,
	345	0x55, 0xfc, 0x62, 0xff, 0x63, 0xf0, 0x64, 0x1f,
	346	0x65, 0x00, 0x66, 0x10, 0x67, 0x00, 0x68, 0x00,
	347	0x69, 0x5c, 0x6a, 0x11, 0x6b, 0xa2, 0x6c, 0x01,
	348	0x6d, 0x50, 0x6e, 0x80, 0x6f, 0x80, 0x70, 0x0f,
	349	0x71, 0x00, 0x72, 0x00, 0x73, 0x0f, 0x74, 0x0f,
	350	0x75, 0xff, 0x78, 0x10, 0x79, 0x70, 0x7a, 0x70,
	351	0x7b, 0xf0, 0x7c, 0xf0, 0x7d, 0xf0, 0x7e, 0x0e,
	352	0x7f, 0x1a, 0x80, 0x31, 0x81, 0x5a, 0x82, 0x69,
	353	0x83, 0x75, 0x84, 0x7e, 0x85, 0x88, 0x86, 0x8f,
	354	0x87, 0x96, 0x88, 0xa3, 0x89, 0xaf, 0x8a, 0xc4,
	355	0x8b, 0xd7, 0x8c, 0xe8, 0x8d, 0x20, 0x8e, 0x00,
	356	0x8f, 0x00, 0x90, 0x08, 0x91, 0x10, 0x92, 0x1f,
	357	0x93, 0x01, 0x94, 0x2c, 0x95, 0x24, 0x96, 0x08,
	358	0x97, 0x14, 0x98, 0x24, 0x99, 0x38, 0x9a, 0x9e,
	359	0x9b, 0x00, 0x9c, 0x40, 0x9e, 0x11, 0x9f, 0x02,
	360	0xa0, 0x00, 0xa1, 0x40, 0xa2, 0x40, 0xa3, 0x06,
	361	0xa4, 0x00, 0xa6, 0x00, 0xa7, 0x40, 0xa8, 0x40,
	362	0xa9, 0x80, 0xaa, 0x80, 0xab, 0x06, 0xac, 0xff,
	363	0x12, 0x06, 0x64, 0x3f, 0x12, 0x46, 0x17, 0x3f,
	364	0x18, 0x50, 0x19, 0x03, 0x1a, 0x78, 0x29, 0x50,
	365	0x2c, 0x78,
	366	};
	367
	368	static int ov772x_set_capture(struct soc_camera_platform_info *info,
	369	int enable)
	370	{
	371	struct i2c_adapter *a = i2c_get_adapter(0);
	372	struct i2c_msg msg;
	373	int ret = 0;
	374	int i;
	375
	376	if (!enable)
	377	return 0; /* camera_power_off() is enough */
	378
	379	for (i = 0; i < ARRAY_SIZE(camera_ov772x_magic); i += 2) {
	380	u_int8_t buf[8];
	381
	382	msg.addr = 0x21;
	383	msg.buf = buf;
	384	msg.len = 2;
	385	msg.flags = 0;
	386
	387	buf[0] = camera_ov772x_magic[i];
	388	buf[1] = camera_ov772x_magic[i + 1];
	389
	390	ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	391	}
	392
	393	return ret;
	394	}
	395
	396	static struct soc_camera_platform_info ov772x_info = {
397	.iface = 0,
398	.format_name = "RGB565",
399	.format_depth = 16,
400	.format = {
401	.pixelformat = V4L2_PIX_FMT_RGB565,
402	.colorspace = V4L2_COLORSPACE_SRGB,
403	.width = 320,
404	.height = 240,
405	},
406	.bus_param = SOCAM_PCLK_SAMPLE_RISING \| SOCAM_HSYNC_ACTIVE_HIGH \|
407	SOCAM_VSYNC_ACTIVE_HIGH \| SOCAM_MASTER \| SOCAM_DATAWIDTH_8,
58419abd	408	.power = camera_power,
1765534c MD	409	.set_capture = ov772x_set_capture,
	410	};
	411
	412	static struct platform_device migor_camera_device = {
	413	.name = "soc_camera_platform",
	414	.dev = {
	415	.platform_data = &ov772x_info,
	416	},
	417	};
e565b518	418	#endif /* CONFIG_I2C */
1765534c MD	419
	420	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	421	.flags = SOCAM_MASTER \| SOCAM_DATAWIDTH_8 \| SOCAM_PCLK_SAMPLE_RISING \
	422	\| SOCAM_HSYNC_ACTIVE_HIGH \| SOCAM_VSYNC_ACTIVE_HIGH,
1765534c MD	423	};
	424
	425	static struct resource migor_ceu_resources[] = {
	426	[0] = {
	427	.name = "CEU",
	428	.start = 0xfe910000,
	429	.end = 0xfe91009f,
	430	.flags = IORESOURCE_MEM,
	431	},
	432	[1] = {
	433	.start = 52,
	434	.flags = IORESOURCE_IRQ,
	435	},
	436	[2] = {
	437	/* place holder for contiguous memory */
	438	},
	439	};
	440
	441	static struct platform_device migor_ceu_device = {
	442	.name = "sh_mobile_ceu",
a42b6dd6	443	.id = 0, /* "ceu0" clock */
1765534c MD	444	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	445	.resource = migor_ceu_resources,
	446	.dev = {
	447	.platform_data = &sh_mobile_ceu_info,
	448	},
	449	};
	450
70f784ec MD	451	static struct platform_device *migor_devices[] __initdata = {
70f784ec MD	452	&smc91x_eth_device,
92cfeb61	453	&sh_keysc_device,
8b1285f1	454	&migor_lcdc_device,
1765534c	455	&migor_ceu_device,
e565b518	456	#ifdef CONFIG_I2C
1765534c	457	&migor_camera_device,
e565b518	458	#endif
b8808786	459	&migor_nor_flash_device,
3c803a9a	460	&migor_nand_flash_device,
70f784ec MD	461	};
70f784ec MD	462
1765534c	463	static struct i2c_board_info migor_i2c_devices[] = {
57795867	464	{
3760f736	465	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	466	},
67908abf MD	467	{
	468	I2C_BOARD_INFO("migor_ts", 0x51),
	469	.irq = 38, /* IRQ6 */
	470	},
0c6111ec MD	471	};
0c6111ec MD	472
70f784ec MD	473	static int __init migor_devices_setup(void)
70f784ec MD	474	{
91b6f3c5 MD	475	/* Lit D11 LED */
	476	gpio_request(GPIO_PTJ7, NULL);
	477	gpio_direction_output(GPIO_PTJ7, 1);
	478	gpio_export(GPIO_PTJ7, 0);
	479
	480	/* Lit D12 LED */
	481	gpio_request(GPIO_PTJ5, NULL);
	482	gpio_direction_output(GPIO_PTJ5, 1);
	483	gpio_export(GPIO_PTJ5, 0);
	484
a30c89ad	485	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	486	gpio_request(GPIO_FN_IRQ0, NULL);
a30c89ad MD	487	ctrl_outl(0x00003400, BSC_CS4BCR);
a30c89ad MD	488	ctrl_outl(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	489
91b6f3c5 MD	490	/* KEYSC */
91b6f3c5 MD	491	gpio_request(GPIO_FN_KEYOUT0, NULL);
	492	gpio_request(GPIO_FN_KEYOUT1, NULL);
	493	gpio_request(GPIO_FN_KEYOUT2, NULL);
	494	gpio_request(GPIO_FN_KEYOUT3, NULL);
	495	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	496	gpio_request(GPIO_FN_KEYIN1, NULL);
	497	gpio_request(GPIO_FN_KEYIN2, NULL);
	498	gpio_request(GPIO_FN_KEYIN3, NULL);
	499	gpio_request(GPIO_FN_KEYIN4, NULL);
	500	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	501
	502	/* NAND Flash */
	503	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	504	ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
	505	gpio_request(GPIO_PTA1, NULL);
	506	gpio_direction_input(GPIO_PTA1);
	507
	508	/* Touch Panel */
	509	gpio_request(GPIO_FN_IRQ6, NULL);
	510
	511	/* LCD Panel */
91b6f3c5 MD	512	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	513	gpio_request(GPIO_FN_LCDD17, NULL);
	514	gpio_request(GPIO_FN_LCDD16, NULL);
	515	gpio_request(GPIO_FN_LCDD15, NULL);
	516	gpio_request(GPIO_FN_LCDD14, NULL);
	517	gpio_request(GPIO_FN_LCDD13, NULL);
	518	gpio_request(GPIO_FN_LCDD12, NULL);
	519	gpio_request(GPIO_FN_LCDD11, NULL);
	520	gpio_request(GPIO_FN_LCDD10, NULL);
	521	gpio_request(GPIO_FN_LCDD8, NULL);
	522	gpio_request(GPIO_FN_LCDD7, NULL);
	523	gpio_request(GPIO_FN_LCDD6, NULL);
	524	gpio_request(GPIO_FN_LCDD5, NULL);
	525	gpio_request(GPIO_FN_LCDD4, NULL);
	526	gpio_request(GPIO_FN_LCDD3, NULL);
	527	gpio_request(GPIO_FN_LCDD2, NULL);
	528	gpio_request(GPIO_FN_LCDD1, NULL);
	529	gpio_request(GPIO_FN_LCDRS, NULL);
	530	gpio_request(GPIO_FN_LCDCS, NULL);
	531	gpio_request(GPIO_FN_LCDRD, NULL);
	532	gpio_request(GPIO_FN_LCDWR, NULL);
	533	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	534	gpio_direction_output(GPIO_PTH2, 1);
	535	#endif
	536	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	537	gpio_request(GPIO_FN_LCDD15, NULL);
	538	gpio_request(GPIO_FN_LCDD14, NULL);
	539	gpio_request(GPIO_FN_LCDD13, NULL);
	540	gpio_request(GPIO_FN_LCDD12, NULL);
	541	gpio_request(GPIO_FN_LCDD11, NULL);
	542	gpio_request(GPIO_FN_LCDD10, NULL);
	543	gpio_request(GPIO_FN_LCDD9, NULL);
	544	gpio_request(GPIO_FN_LCDD8, NULL);
	545	gpio_request(GPIO_FN_LCDD7, NULL);
	546	gpio_request(GPIO_FN_LCDD6, NULL);
	547	gpio_request(GPIO_FN_LCDD5, NULL);
	548	gpio_request(GPIO_FN_LCDD4, NULL);
	549	gpio_request(GPIO_FN_LCDD3, NULL);
	550	gpio_request(GPIO_FN_LCDD2, NULL);
	551	gpio_request(GPIO_FN_LCDD1, NULL);
	552	gpio_request(GPIO_FN_LCDD0, NULL);
	553	gpio_request(GPIO_FN_LCDLCLK, NULL);
	554	gpio_request(GPIO_FN_LCDDCK, NULL);
	555	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	556	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	557	gpio_request(GPIO_FN_LCDVSYN, NULL);
	558	gpio_request(GPIO_FN_LCDHSYN, NULL);
	559	gpio_request(GPIO_FN_LCDDISP, NULL);
	560	gpio_request(GPIO_FN_LCDDON, NULL);
	561	#endif
	562
	563	/* CEU */
91b6f3c5 MD	564	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	565	gpio_request(GPIO_FN_VIO_VD2, NULL);
	566	gpio_request(GPIO_FN_VIO_HD2, NULL);
	567	gpio_request(GPIO_FN_VIO_FLD, NULL);
	568	gpio_request(GPIO_FN_VIO_CKO, NULL);
	569	gpio_request(GPIO_FN_VIO_D15, NULL);
	570	gpio_request(GPIO_FN_VIO_D14, NULL);
	571	gpio_request(GPIO_FN_VIO_D13, NULL);
	572	gpio_request(GPIO_FN_VIO_D12, NULL);
	573	gpio_request(GPIO_FN_VIO_D11, NULL);
	574	gpio_request(GPIO_FN_VIO_D10, NULL);
	575	gpio_request(GPIO_FN_VIO_D9, NULL);
	576	gpio_request(GPIO_FN_VIO_D8, NULL);
	577
	578	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	579	gpio_direction_output(GPIO_PTT3, 0);
	580	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	581	gpio_direction_output(GPIO_PTT2, 1);
	582	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
	583	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	584	gpio_direction_output(GPIO_PTT0, 0);
	585	#else
	586	gpio_direction_output(GPIO_PTT0, 1);
	587	#endif
	588	ctrl_outw(ctrl_inw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c MD	589
1765534c MD	590	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c	591
0c6111ec MD	592	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	593	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	594
70f784ec MD	595	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
	596	}
	597	__initcall(migor_devices_setup);