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sh_eth: get SH7724 support out of #ifdef
[deliverable/linux.git] / arch / sh / boards / mach-se / 7724 / setup.c
CommitLineData
287c1297
KM		 1/*
2 * linux/arch/sh/boards/se/7724/setup.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
a68a0784 17#include <linux/mmc/host.h>
960b9e7e 18#include <linux/mmc/sh_mobile_sdhi.h>
287c1297
KM		 19#include <linux/mtd/physmap.h>
20#include <linux/delay.h>
67ef5786
GL		 21#include <linux/regulator/fixed.h>
22#include <linux/regulator/machine.h>
287c1297
KM		 23#include <linux/smc91x.h>
24#include <linux/gpio.h>
25#include <linux/input.h>
fc1d003d 26#include <linux/input/sh_keysc.h>
9731f4a2 27#include <linux/usb/r8a66597.h>
cf8e56bf 28#include <linux/sh_eth.h>
b894701e 29#include <linux/sh_intc.h>
a1ad8033 30#include <linux/videodev2.h>
287c1297
KM		 31#include <video/sh_mobile_lcdc.h>
32#include <media/sh_mobile_ceu.h>
3e9ad52b 33#include <sound/sh_fsi.h>
af8a2fe1 34#include <sound/simple_card.h>
287c1297
KM		 35#include <asm/io.h>
36#include <asm/heartbeat.h>
a80cad95 37#include <asm/clock.h>
3b9f2952 38#include <asm/suspend.h>
287c1297
KM		 39#include <cpu/sh7724.h>
40#include <mach-se/mach/se7724.h>
41
42/*
43 * SWx 1234 5678
44 * ------------------------------------
45 * SW31 : 1001 1100 : default
46 * SW32 : 0111 1111 : use on board flash
47 *
48 * SW41 : abxx xxxx -> a = 0 : Analog monitor
49 * 1 : Digital monitor
50 * b = 0 : VGA
4f324311
KM		 51 * 1 : 720p
52 */
53
54/*
55 * about 720p
56 *
57 * When you use 1280 x 720 lcdc output,
58 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
59 * and change SW41 to use 720p
287c1297
KM		 60 */
61
bec9fb07
KM		 62/*
63 * about sound
64 *
65 * This setup.c supports FSI slave mode.
66 * Please change J20, J21, J22 pin to 1-2 connection.
67 */
68
287c1297 69/* Heartbeat */
a09d2831
PM		 70static struct resource heartbeat_resource = {
71 .start = PA_LED,
72 .end = PA_LED,
73 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
287c1297
KM		 74};
75
76static struct platform_device heartbeat_device = {
77 .name = "heartbeat",
78 .id = -1,
a09d2831
PM		 79 .num_resources = 1,
80 .resource = &heartbeat_resource,
287c1297
KM		 81};
82
83/* LAN91C111 */
84static struct smc91x_platdata smc91x_info = {
85 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
86};
87
88static struct resource smc91x_eth_resources[] = {
89 [0] = {
90 .name = "SMC91C111" ,
91 .start = 0x1a300300,
92 .end = 0x1a30030f,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = IRQ0_SMC,
97 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
98 },
99};
100
101static struct platform_device smc91x_eth_device = {
102 .name = "smc91x",
103 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
104 .resource = smc91x_eth_resources,
105 .dev = {
106 .platform_data = &smc91x_info,
107 },
108};
109
110/* MTD */
111static struct mtd_partition nor_flash_partitions[] = {
112 {
113 .name = "uboot",
114 .offset = 0,
115 .size = (1 * 1024 * 1024),
116 .mask_flags = MTD_WRITEABLE, /* Read-only */
117 }, {
118 .name = "kernel",
119 .offset = MTDPART_OFS_APPEND,
120 .size = (2 * 1024 * 1024),
121 }, {
122 .name = "free-area",
123 .offset = MTDPART_OFS_APPEND,
124 .size = MTDPART_SIZ_FULL,
125 },
126};
127
128static struct physmap_flash_data nor_flash_data = {
129 .width = 2,
130 .parts = nor_flash_partitions,
131 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
132};
133
134static struct resource nor_flash_resources[] = {
135 [0] = {
136 .name = "NOR Flash",
137 .start = 0x00000000,
138 .end = 0x01ffffff,
139 .flags = IORESOURCE_MEM,
140 }
141};
142
143static struct platform_device nor_flash_device = {
144 .name = "physmap-flash",
145 .resource = nor_flash_resources,
146 .num_resources = ARRAY_SIZE(nor_flash_resources),
147 .dev = {
148 .platform_data = &nor_flash_data,
149 },
150};
151
152/* LCDC */
e04008eb 153static const struct fb_videomode lcdc_720p_modes[] = {
44432407
GL		 154 {
155 .name = "LB070WV1",
156 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 157 .xres = 1280,
158 .yres = 720,
159 .left_margin = 220,
160 .right_margin = 110,
161 .hsync_len = 40,
162 .upper_margin = 20,
163 .lower_margin = 5,
164 .vsync_len = 5,
44432407
GL		 165 },
166};
167
e04008eb 168static const struct fb_videomode lcdc_vga_modes[] = {
44432407
GL		 169 {
170 .name = "LB070WV1",
171 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 172 .xres = 640,
173 .yres = 480,
174 .left_margin = 105,
175 .right_margin = 50,
176 .hsync_len = 96,
177 .upper_margin = 33,
178 .lower_margin = 10,
179 .vsync_len = 2,
44432407
GL		 180 },
181};
182
287c1297
KM		 183static struct sh_mobile_lcdc_info lcdc_info = {
184 .clock_source = LCDC_CLK_EXTERNAL,
185 .ch[0] = {
186 .chan = LCDC_CHAN_MAINLCD,
edd153a3 187 .fourcc = V4L2_PIX_FMT_RGB565,
287c1297 188 .clock_divider = 1,
afaad83b 189 .panel_cfg = { /* 7.0 inch */
287c1297
KM		 190 .width = 152,
191 .height = 91,
192 },
287c1297
KM		 193 }
194};
195
196static struct resource lcdc_resources[] = {
197 [0] = {
198 .name = "LCDC",
199 .start = 0xfe940000,
a6f15ade 200 .end = 0xfe942fff,
287c1297
KM		 201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
b894701e 204 .start = evt2irq(0xf40),
287c1297
KM		 205 .flags = IORESOURCE_IRQ,
206 },
207};
208
209static struct platform_device lcdc_device = {
210 .name = "sh_mobile_lcdc_fb",
211 .num_resources = ARRAY_SIZE(lcdc_resources),
212 .resource = lcdc_resources,
213 .dev = {
214 .platform_data = &lcdc_info,
215 },
216};
217
218/* CEU0 */
219static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
220 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
221};
222
223static struct resource ceu0_resources[] = {
224 [0] = {
225 .name = "CEU0",
226 .start = 0xfe910000,
227 .end = 0xfe91009f,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
b894701e 231 .start = evt2irq(0x880),
287c1297
KM		 232 .flags = IORESOURCE_IRQ,
233 },
234 [2] = {
235 /* place holder for contiguous memory */
236 },
237};
238
239static struct platform_device ceu0_device = {
240 .name = "sh_mobile_ceu",
241 .id = 0, /* "ceu0" clock */
242 .num_resources = ARRAY_SIZE(ceu0_resources),
243 .resource = ceu0_resources,
244 .dev = {
245 .platform_data = &sh_mobile_ceu0_info,
246 },
247};
248
249/* CEU1 */
250static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
251 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
252};
253
254static struct resource ceu1_resources[] = {
255 [0] = {
256 .name = "CEU1",
257 .start = 0xfe914000,
258 .end = 0xfe91409f,
259 .flags = IORESOURCE_MEM,
260 },
261 [1] = {
b894701e 262 .start = evt2irq(0x9e0),
287c1297
KM		 263 .flags = IORESOURCE_IRQ,
264 },
265 [2] = {
266 /* place holder for contiguous memory */
267 },
268};
269
270static struct platform_device ceu1_device = {
271 .name = "sh_mobile_ceu",
272 .id = 1, /* "ceu1" clock */
273 .num_resources = ARRAY_SIZE(ceu1_resources),
274 .resource = ceu1_resources,
275 .dev = {
276 .platform_data = &sh_mobile_ceu1_info,
277 },
278};
279
3e9ad52b 280/* FSI */
bec9fb07 281/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
3e9ad52b
KM		 282static struct resource fsi_resources[] = {
283 [0] = {
284 .name = "FSI",
285 .start = 0xFE3C0000,
286 .end = 0xFE3C021d,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
b894701e 290 .start = evt2irq(0xf80),
3e9ad52b
KM		 291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device fsi_device = {
296 .name = "sh_fsi",
297 .id = 0,
298 .num_resources = ARRAY_SIZE(fsi_resources),
299 .resource = fsi_resources,
3e9ad52b
KM		 300};
301
af8a2fe1 302static struct asoc_simple_card_info fsi_ak4642_info = {
45f31216
KM		 303 .name = "AK4642",
304 .card = "FSIA-AK4642",
45f31216
KM		 305 .codec = "ak4642-codec.0-0012",
306 .platform = "sh_fsi.0",
a4a2992c
KM		 307 .daifmt = SND_SOC_DAIFMT_LEFT_J,
308 .cpu_dai = {
309 .name = "fsia-dai",
310 .fmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
311 },
312 .codec_dai = {
313 .name = "ak4642-hifi",
314 .fmt = SND_SOC_DAIFMT_CBM_CFM,
315 .sysclk = 11289600,
316 },
45f31216
KM		 317};
318
c8d6bf9a 319static struct platform_device fsi_ak4642_device = {
af8a2fe1 320 .name = "asoc-simple-card",
45f31216
KM		 321 .dev = {
322 .platform_data = &fsi_ak4642_info,
323 },
c8d6bf9a
KM		 324};
325
9747e78b 326/* KEYSC in SoC (Needs SW33-2 set to ON) */
287c1297
KM		 327static struct sh_keysc_info keysc_info = {
328 .mode = SH_KEYSC_MODE_1,
29463c28 329 .scan_timing = 3,
287c1297
KM		 330 .delay = 50,
331 .keycodes = {
332 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
333 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
334 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
335 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
336 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
337 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
338 },
339};
340
341static struct resource keysc_resources[] = {
342 [0] = {
9747e78b
MD		 343 .name = "KEYSC",
344 .start = 0x044b0000,
345 .end = 0x044b000f,
287c1297
KM		 346 .flags = IORESOURCE_MEM,
347 },
348 [1] = {
b894701e 349 .start = evt2irq(0xbe0),
287c1297
KM		 350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354static struct platform_device keysc_device = {
355 .name = "sh_keysc",
356 .id = 0, /* "keysc0" clock */
357 .num_resources = ARRAY_SIZE(keysc_resources),
358 .resource = keysc_resources,
359 .dev = {
360 .platform_data = &keysc_info,
361 },
362};
363
a80cad95
KM		 364/* SH Eth */
365static struct resource sh_eth_resources[] = {
366 [0] = {
367 .start = SH_ETH_ADDR,
368 .end = SH_ETH_ADDR + 0x1FC,
369 .flags = IORESOURCE_MEM,
370 },
371 [1] = {
b894701e 372 .start = evt2irq(0xd60),
a80cad95
KM		 373 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
374 },
375};
376
560526f1 377static struct sh_eth_plat_data sh_eth_plat = {
a80cad95
KM		 378 .phy = 0x1f, /* SMSC LAN8187 */
379 .edmac_endian = EDMAC_LITTLE_ENDIAN,
380};
381
382static struct platform_device sh_eth_device = {
9c3beaab
SS		 383 .name = "sh7724-ether",
384 .id = 0,
a80cad95
KM		 385 .dev = {
386 .platform_data = &sh_eth_plat,
387 },
388 .num_resources = ARRAY_SIZE(sh_eth_resources),
389 .resource = sh_eth_resources,
390};
391
9731f4a2 392static struct r8a66597_platdata sh7724_usb0_host_data = {
719a72b7 393 .on_chip = 1,
9731f4a2
MD		 394};
395
396static struct resource sh7724_usb0_host_resources[] = {
397 [0] = {
398 .start = 0xa4d80000,
1bc265d0 399 .end = 0xa4d80124 - 1,
9731f4a2
MD		 400 .flags = IORESOURCE_MEM,
401 },
402 [1] = {
b894701e
PM		 403 .start = evt2irq(0xa20),
404 .end = evt2irq(0xa20),
9731f4a2
MD		 405 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
406 },
407};
408
409static struct platform_device sh7724_usb0_host_device = {
410 .name = "r8a66597_hcd",
411 .id = 0,
412 .dev = {
413 .dma_mask = NULL, /* not use dma */
414 .coherent_dma_mask = 0xffffffff,
415 .platform_data = &sh7724_usb0_host_data,
416 },
417 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
418 .resource = sh7724_usb0_host_resources,
419};
420
f8f8c079
MD		 421static struct r8a66597_platdata sh7724_usb1_gadget_data = {
422 .on_chip = 1,
423};
424
425static struct resource sh7724_usb1_gadget_resources[] = {
426 [0] = {
427 .start = 0xa4d90000,
428 .end = 0xa4d90123,
429 .flags = IORESOURCE_MEM,
430 },
431 [1] = {
b894701e
PM		 432 .start = evt2irq(0xa40),
433 .end = evt2irq(0xa40),
f8f8c079
MD		 434 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
435 },
436};
437
438static struct platform_device sh7724_usb1_gadget_device = {
439 .name = "r8a66597_udc",
440 .id = 1, /* USB1 */
441 .dev = {
442 .dma_mask = NULL, /* not use dma */
443 .coherent_dma_mask = 0xffffffff,
444 .platform_data = &sh7724_usb1_gadget_data,
445 },
446 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
447 .resource = sh7724_usb1_gadget_resources,
448};
449
67ef5786
GL		 450/* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
451static struct regulator_consumer_supply fixed3v3_power_consumers[] =
452{
453 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
454 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
455 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
456 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
457};
458
0f79af60
MD		 459static struct resource sdhi0_cn7_resources[] = {
460 [0] = {
461 .name = "SDHI0",
462 .start = 0x04ce0000,
d80e9221 463 .end = 0x04ce00ff,
0f79af60
MD		 464 .flags = IORESOURCE_MEM,
465 },
466 [1] = {
b894701e 467 .start = evt2irq(0xe80),
0f79af60
MD		 468 .flags = IORESOURCE_IRQ,
469 },
470};
471
470ef1a7
GL		 472static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
473 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
474 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
a68a0784 475 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 476};
477
0f79af60
MD		 478static struct platform_device sdhi0_cn7_device = {
479 .name = "sh_mobile_sdhi",
5b380ec1 480 .id = 0,
0f79af60
MD		 481 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
482 .resource = sdhi0_cn7_resources,
470ef1a7
GL		 483 .dev = {
484 .platform_data = &sh7724_sdhi0_data,
485 },
0f79af60
MD		 486};
487
5b380ec1
MD		 488static struct resource sdhi1_cn8_resources[] = {
489 [0] = {
490 .name = "SDHI1",
491 .start = 0x04cf0000,
d80e9221 492 .end = 0x04cf00ff,
5b380ec1
MD		 493 .flags = IORESOURCE_MEM,
494 },
495 [1] = {
b894701e 496 .start = evt2irq(0x4e0),
5b380ec1
MD		 497 .flags = IORESOURCE_IRQ,
498 },
499};
500
470ef1a7
GL		 501static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
502 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
503 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
a68a0784 504 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 505};
506
5b380ec1
MD		 507static struct platform_device sdhi1_cn8_device = {
508 .name = "sh_mobile_sdhi",
509 .id = 1,
510 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
511 .resource = sdhi1_cn8_resources,
470ef1a7
GL		 512 .dev = {
513 .platform_data = &sh7724_sdhi1_data,
514 },
5b380ec1
MD		 515};
516
bbb892aa
KM		 517/* IrDA */
518static struct resource irda_resources[] = {
519 [0] = {
520 .name = "IrDA",
521 .start = 0xA45D0000,
522 .end = 0xA45D0049,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
b894701e 526 .start = evt2irq(0x480),
bbb892aa
KM		 527 .flags = IORESOURCE_IRQ,
528 },
529};
530
531static struct platform_device irda_device = {
532 .name = "sh_sir",
533 .num_resources = ARRAY_SIZE(irda_resources),
534 .resource = irda_resources,
535};
536
2d151248
GL		 537#include <media/ak881x.h>
538#include <media/sh_vou.h>
539
560526f1 540static struct ak881x_pdata ak881x_pdata = {
2d151248
GL		 541 .flags = AK881X_IF_MODE_SLAVE,
542};
543
544static struct i2c_board_info ak8813 = {
545 /* With open J18 jumper address is 0x21 */
546 I2C_BOARD_INFO("ak8813", 0x20),
547 .platform_data = &ak881x_pdata,
548};
549
560526f1 550static struct sh_vou_pdata sh_vou_pdata = {
2d151248
GL		 551 .bus_fmt = SH_VOU_BUS_8BIT,
552 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
553 .board_info = &ak8813,
554 .i2c_adap = 0,
2d151248
GL		 555};
556
557static struct resource sh_vou_resources[] = {
558 [0] = {
559 .start = 0xfe960000,
560 .end = 0xfe962043,
561 .flags = IORESOURCE_MEM,
562 },
563 [1] = {
b894701e 564 .start = evt2irq(0x8e0),
2d151248
GL		 565 .flags = IORESOURCE_IRQ,
566 },
567};
568
569static struct platform_device vou_device = {
570 .name = "sh-vou",
571 .id = -1,
572 .num_resources = ARRAY_SIZE(sh_vou_resources),
573 .resource = sh_vou_resources,
574 .dev = {
575 .platform_data = &sh_vou_pdata,
576 },
2d151248
GL		 577};
578
287c1297
KM		 579static struct platform_device *ms7724se_devices[] __initdata = {
580 &heartbeat_device,
581 &smc91x_eth_device,
582 &lcdc_device,
583 &nor_flash_device,
584 &ceu0_device,
585 &ceu1_device,
586 &keysc_device,
a80cad95 587 &sh_eth_device,
9731f4a2 588 &sh7724_usb0_host_device,
f8f8c079 589 &sh7724_usb1_gadget_device,
3e9ad52b 590 &fsi_device,
c8d6bf9a 591 &fsi_ak4642_device,
0f79af60 592 &sdhi0_cn7_device,
5b380ec1 593 &sdhi1_cn8_device,
bbb892aa 594 &irda_device,
2d151248 595 &vou_device,
287c1297
KM		 596};
597
9f815a17
KM		 598/* I2C device */
599static struct i2c_board_info i2c0_devices[] = {
600 {
601 I2C_BOARD_INFO("ak4642", 0x12),
602 },
603};
604
a80cad95
KM		 605#define EEPROM_OP 0xBA206000
606#define EEPROM_ADR 0xBA206004
607#define EEPROM_DATA 0xBA20600C
608#define EEPROM_STAT 0xBA206010
609#define EEPROM_STRT 0xBA206014
b894701e 610
a80cad95
KM		 611static int __init sh_eth_is_eeprom_ready(void)
612{
613 int t = 10000;
614
615 while (t--) {
9d56dd3b 616 if (!__raw_readw(EEPROM_STAT))
a80cad95 617 return 1;
c718aff2 618 udelay(1);
a80cad95
KM		 619 }
620
621 printk(KERN_ERR "ms7724se can not access to eeprom\n");
622 return 0;
623}
624
625static void __init sh_eth_init(void)
626{
627 int i;
8013cc9a 628 u16 mac;
a80cad95
KM		 629
630 /* check EEPROM status */
631 if (!sh_eth_is_eeprom_ready())
632 return;
633
634 /* read MAC addr from EEPROM */
635 for (i = 0 ; i < 3 ; i++) {
9d56dd3b
PM		 636 __raw_writew(0x0, EEPROM_OP); /* read */
637 __raw_writew(i*2, EEPROM_ADR);
638 __raw_writew(0x1, EEPROM_STRT);
a80cad95
KM		 639 if (!sh_eth_is_eeprom_ready())
640 return;
641
9d56dd3b 642 mac = __raw_readw(EEPROM_DATA);
8013cc9a
MD		 643 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
644 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
a80cad95 645 }
a80cad95
KM		 646}
647
287c1297
KM		 648#define SW4140 0xBA201000
649#define FPGA_OUT 0xBA200400
650#define PORT_HIZA 0xA4050158
9731f4a2 651#define PORT_MSELCRB 0xA4050182
287c1297
KM		 652
653#define SW41_A 0x0100
654#define SW41_B 0x0200
655#define SW41_C 0x0400
656#define SW41_D 0x0800
657#define SW41_E 0x1000
658#define SW41_F 0x2000
659#define SW41_G 0x4000
660#define SW41_H 0x8000
9731f4a2 661
3b9f2952
MD		 662extern char ms7724se_sdram_enter_start;
663extern char ms7724se_sdram_enter_end;
664extern char ms7724se_sdram_leave_start;
665extern char ms7724se_sdram_leave_end;
666
9f815a17
KM		 667static int __init arch_setup(void)
668{
669 /* enable I2C device */
670 i2c_register_board_info(0, i2c0_devices,
671 ARRAY_SIZE(i2c0_devices));
672 return 0;
673}
674arch_initcall(arch_setup);
675
287c1297
KM		 676static int __init devices_setup(void)
677{
9d56dd3b 678 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
16afc9fb 679 struct clk *clk;
2d151248 680 u16 fpga_out;
287c1297 681
3b9f2952 682 /* register board specific self-refresh code */
b67cf284
MD		 683 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
684 SUSP_SH_RSTANDBY,
3b9f2952
MD		 685 &ms7724se_sdram_enter_start,
686 &ms7724se_sdram_enter_end,
687 &ms7724se_sdram_leave_start,
688 &ms7724se_sdram_leave_end);
67ef5786
GL		 689
690 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
691 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
692
287c1297 693 /* Reset Release */
2d151248
GL		 694 fpga_out = __raw_readw(FPGA_OUT);
695 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
696 fpga_out &= ~((1 << 1) | /* LAN */
697 (1 << 4) | /* AK8813 PDN */
698 (1 << 5) | /* AK8813 RESET */
699 (1 << 6) | /* VIDEO DAC */
700 (1 << 7) | /* AK4643 */
701 (1 << 8) | /* IrDA */
702 (1 << 12) | /* USB0 */
703 (1 << 14)); /* RMII */
704 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
705
706 udelay(10);
707
708 /* AK8813 RESET */
709 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
710
711 udelay(10);
712
713 __raw_writew(fpga_out, FPGA_OUT);
287c1297 714
9731f4a2 715 /* turn on USB clocks, use external clock */
9d56dd3b 716 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
9731f4a2 717
7766e16b
MD		 718 /* Let LED9 show STATUS2 */
719 gpio_request(GPIO_FN_STATUS2, NULL);
720
721 /* Lit LED10 show STATUS0 */
722 gpio_request(GPIO_FN_STATUS0, NULL);
723
724 /* Lit LED11 show PDSTATUS */
725 gpio_request(GPIO_FN_PDSTATUS, NULL);
7766e16b 726
9731f4a2 727 /* enable USB0 port */
9d56dd3b 728 __raw_writew(0x0600, 0xa40501d4);
9731f4a2 729
f8f8c079 730 /* enable USB1 port */
9d56dd3b 731 __raw_writew(0x0600, 0xa4050192);
f8f8c079 732
287c1297
KM		 733 /* enable IRQ 0,1,2 */
734 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
735 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
736 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
737
738 /* enable SCIFA3 */
739 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
740 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
741 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
742 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
743 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
744
745 /* enable LCDC */
746 gpio_request(GPIO_FN_LCDD23, NULL);
747 gpio_request(GPIO_FN_LCDD22, NULL);
748 gpio_request(GPIO_FN_LCDD21, NULL);
749 gpio_request(GPIO_FN_LCDD20, NULL);
750 gpio_request(GPIO_FN_LCDD19, NULL);
751 gpio_request(GPIO_FN_LCDD18, NULL);
752 gpio_request(GPIO_FN_LCDD17, NULL);
753 gpio_request(GPIO_FN_LCDD16, NULL);
754 gpio_request(GPIO_FN_LCDD15, NULL);
755 gpio_request(GPIO_FN_LCDD14, NULL);
756 gpio_request(GPIO_FN_LCDD13, NULL);
757 gpio_request(GPIO_FN_LCDD12, NULL);
758 gpio_request(GPIO_FN_LCDD11, NULL);
759 gpio_request(GPIO_FN_LCDD10, NULL);
760 gpio_request(GPIO_FN_LCDD9, NULL);
761 gpio_request(GPIO_FN_LCDD8, NULL);
762 gpio_request(GPIO_FN_LCDD7, NULL);
763 gpio_request(GPIO_FN_LCDD6, NULL);
764 gpio_request(GPIO_FN_LCDD5, NULL);
765 gpio_request(GPIO_FN_LCDD4, NULL);
766 gpio_request(GPIO_FN_LCDD3, NULL);
767 gpio_request(GPIO_FN_LCDD2, NULL);
768 gpio_request(GPIO_FN_LCDD1, NULL);
769 gpio_request(GPIO_FN_LCDD0, NULL);
770 gpio_request(GPIO_FN_LCDDISP, NULL);
771 gpio_request(GPIO_FN_LCDHSYN, NULL);
772 gpio_request(GPIO_FN_LCDDCK, NULL);
773 gpio_request(GPIO_FN_LCDVSYN, NULL);
774 gpio_request(GPIO_FN_LCDDON, NULL);
775 gpio_request(GPIO_FN_LCDVEPWC, NULL);
776 gpio_request(GPIO_FN_LCDVCPWC, NULL);
777 gpio_request(GPIO_FN_LCDRD, NULL);
778 gpio_request(GPIO_FN_LCDLCLK, NULL);
9d56dd3b 779 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
287c1297
KM		 780
781 /* enable CEU0 */
782 gpio_request(GPIO_FN_VIO0_D15, NULL);
783 gpio_request(GPIO_FN_VIO0_D14, NULL);
784 gpio_request(GPIO_FN_VIO0_D13, NULL);
785 gpio_request(GPIO_FN_VIO0_D12, NULL);
786 gpio_request(GPIO_FN_VIO0_D11, NULL);
787 gpio_request(GPIO_FN_VIO0_D10, NULL);
788 gpio_request(GPIO_FN_VIO0_D9, NULL);
789 gpio_request(GPIO_FN_VIO0_D8, NULL);
790 gpio_request(GPIO_FN_VIO0_D7, NULL);
791 gpio_request(GPIO_FN_VIO0_D6, NULL);
792 gpio_request(GPIO_FN_VIO0_D5, NULL);
793 gpio_request(GPIO_FN_VIO0_D4, NULL);
794 gpio_request(GPIO_FN_VIO0_D3, NULL);
795 gpio_request(GPIO_FN_VIO0_D2, NULL);
796 gpio_request(GPIO_FN_VIO0_D1, NULL);
797 gpio_request(GPIO_FN_VIO0_D0, NULL);
798 gpio_request(GPIO_FN_VIO0_VD, NULL);
799 gpio_request(GPIO_FN_VIO0_CLK, NULL);
800 gpio_request(GPIO_FN_VIO0_FLD, NULL);
801 gpio_request(GPIO_FN_VIO0_HD, NULL);
84f7597c 802 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
287c1297
KM		 803
804 /* enable CEU1 */
805 gpio_request(GPIO_FN_VIO1_D7, NULL);
806 gpio_request(GPIO_FN_VIO1_D6, NULL);
807 gpio_request(GPIO_FN_VIO1_D5, NULL);
808 gpio_request(GPIO_FN_VIO1_D4, NULL);
809 gpio_request(GPIO_FN_VIO1_D3, NULL);
810 gpio_request(GPIO_FN_VIO1_D2, NULL);
811 gpio_request(GPIO_FN_VIO1_D1, NULL);
812 gpio_request(GPIO_FN_VIO1_D0, NULL);
813 gpio_request(GPIO_FN_VIO1_FLD, NULL);
814 gpio_request(GPIO_FN_VIO1_HD, NULL);
815 gpio_request(GPIO_FN_VIO1_VD, NULL);
816 gpio_request(GPIO_FN_VIO1_CLK, NULL);
84f7597c 817 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
287c1297
KM		 818
819 /* KEYSC */
820 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
821 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
822 gpio_request(GPIO_FN_KEYIN4, NULL);
823 gpio_request(GPIO_FN_KEYIN3, NULL);
824 gpio_request(GPIO_FN_KEYIN2, NULL);
825 gpio_request(GPIO_FN_KEYIN1, NULL);
826 gpio_request(GPIO_FN_KEYIN0, NULL);
827 gpio_request(GPIO_FN_KEYOUT3, NULL);
828 gpio_request(GPIO_FN_KEYOUT2, NULL);
829 gpio_request(GPIO_FN_KEYOUT1, NULL);
830 gpio_request(GPIO_FN_KEYOUT0, NULL);
831
3e9ad52b 832 /* enable FSI */
3e9ad52b 833 gpio_request(GPIO_FN_FSIMCKA, NULL);
c44352c5 834 gpio_request(GPIO_FN_FSIIASD, NULL);
3e9ad52b
KM		 835 gpio_request(GPIO_FN_FSIOASD, NULL);
836 gpio_request(GPIO_FN_FSIIABCK, NULL);
837 gpio_request(GPIO_FN_FSIIALRCK, NULL);
838 gpio_request(GPIO_FN_FSIOABCK, NULL);
839 gpio_request(GPIO_FN_FSIOALRCK, NULL);
840 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
3e9ad52b 841
16afc9fb
KM		 842 /* set SPU2 clock to 83.4 MHz */
843 clk = clk_get(NULL, "spu_clk");
193006f7 844 if (!IS_ERR(clk)) {
03c5ecd1
KM		 845 clk_set_rate(clk, clk_round_rate(clk, 83333333));
846 clk_put(clk);
847 }
16afc9fb 848
3e9ad52b 849 /* change parent of FSI A */
16afc9fb 850 clk = clk_get(NULL, "fsia_clk");
193006f7 851 if (!IS_ERR(clk)) {
e17ca5cf
NI		 852 /* 48kHz dummy clock was used to make sure 1/1 divide */
853 clk_set_rate(&sh7724_fsimcka_clk, 48000);
854 clk_set_parent(clk, &sh7724_fsimcka_clk);
855 clk_set_rate(clk, 48000);
03c5ecd1
KM		 856 clk_put(clk);
857 }
3e9ad52b 858
0f79af60
MD		 859 /* SDHI0 connected to cn7 */
860 gpio_request(GPIO_FN_SDHI0CD, NULL);
861 gpio_request(GPIO_FN_SDHI0WP, NULL);
862 gpio_request(GPIO_FN_SDHI0D3, NULL);
863 gpio_request(GPIO_FN_SDHI0D2, NULL);
864 gpio_request(GPIO_FN_SDHI0D1, NULL);
865 gpio_request(GPIO_FN_SDHI0D0, NULL);
866 gpio_request(GPIO_FN_SDHI0CMD, NULL);
867 gpio_request(GPIO_FN_SDHI0CLK, NULL);
868
5b380ec1
MD		 869 /* SDHI1 connected to cn8 */
870 gpio_request(GPIO_FN_SDHI1CD, NULL);
871 gpio_request(GPIO_FN_SDHI1WP, NULL);
872 gpio_request(GPIO_FN_SDHI1D3, NULL);
873 gpio_request(GPIO_FN_SDHI1D2, NULL);
874 gpio_request(GPIO_FN_SDHI1D1, NULL);
875 gpio_request(GPIO_FN_SDHI1D0, NULL);
876 gpio_request(GPIO_FN_SDHI1CMD, NULL);
877 gpio_request(GPIO_FN_SDHI1CLK, NULL);
878
bbb892aa
KM		 879 /* enable IrDA */
880 gpio_request(GPIO_FN_IRDA_OUT, NULL);
881 gpio_request(GPIO_FN_IRDA_IN, NULL);
882
a80cad95
KM		 883 /*
884 * enable SH-Eth
885 *
886 * please remove J33 pin from your board !!
887 *
888 * ms7724 board should not use GPIO_FN_LNKSTA pin
889 * So, This time PTX5 is set to input pin
890 */
891 gpio_request(GPIO_FN_RMII_RXD0, NULL);
892 gpio_request(GPIO_FN_RMII_RXD1, NULL);
893 gpio_request(GPIO_FN_RMII_TXD0, NULL);
894 gpio_request(GPIO_FN_RMII_TXD1, NULL);
895 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
896 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
897 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
898 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
899 gpio_request(GPIO_FN_MDIO, NULL);
900 gpio_request(GPIO_FN_MDC, NULL);
901 gpio_request(GPIO_PTX5, NULL);
902 gpio_direction_input(GPIO_PTX5);
903 sh_eth_init();
904
287c1297 905 if (sw & SW41_B) {
4f324311 906 /* 720p */
93ff2598
LP		 907 lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
908 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
287c1297
KM		 909 } else {
910 /* VGA */
93ff2598
LP		 911 lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
912 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
287c1297
KM		 913 }
914
915 if (sw & SW41_A) {
916 /* Digital monitor */
917 lcdc_info.ch[0].interface_type = RGB18;
918 lcdc_info.ch[0].flags = 0;
919 } else {
920 /* Analog monitor */
921 lcdc_info.ch[0].interface_type = RGB24;
922 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
923 }
924
2d151248
GL		 925 /* VOU */
926 gpio_request(GPIO_FN_DV_D15, NULL);
927 gpio_request(GPIO_FN_DV_D14, NULL);
928 gpio_request(GPIO_FN_DV_D13, NULL);
929 gpio_request(GPIO_FN_DV_D12, NULL);
930 gpio_request(GPIO_FN_DV_D11, NULL);
931 gpio_request(GPIO_FN_DV_D10, NULL);
932 gpio_request(GPIO_FN_DV_D9, NULL);
933 gpio_request(GPIO_FN_DV_D8, NULL);
934 gpio_request(GPIO_FN_DV_CLKI, NULL);
935 gpio_request(GPIO_FN_DV_CLK, NULL);
936 gpio_request(GPIO_FN_DV_VSYNC, NULL);
937 gpio_request(GPIO_FN_DV_HSYNC, NULL);
938
287c1297 939 return platform_add_devices(ms7724se_devices,
a80cad95 940 ARRAY_SIZE(ms7724se_devices));
287c1297
KM		 941}
942device_initcall(devices_setup);
943
944static struct sh_machine_vector mv_ms7724se __initmv = {
945 .mv_name = "ms7724se",
946 .mv_init_irq = init_se7724_IRQ,
287c1297 947};
Linux kernel - Deliverables
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