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ASoC: sh: fsi: modify selection method of I2S/PCM/SPDIF format
[deliverable/linux.git] / arch / sh / boards / mach-se / 7724 / setup.c
CommitLineData
287c1297
KM		 1/*
2 * linux/arch/sh/boards/se/7724/setup.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
470ef1a7 17#include <linux/mfd/sh_mobile_sdhi.h>
a68a0784 18#include <linux/mmc/host.h>
287c1297
KM		 19#include <linux/mtd/physmap.h>
20#include <linux/delay.h>
21#include <linux/smc91x.h>
22#include <linux/gpio.h>
23#include <linux/input.h>
fc1d003d 24#include <linux/input/sh_keysc.h>
9731f4a2 25#include <linux/usb/r8a66597.h>
287c1297
KM		 26#include <video/sh_mobile_lcdc.h>
27#include <media/sh_mobile_ceu.h>
3e9ad52b 28#include <sound/sh_fsi.h>
287c1297
KM		 29#include <asm/io.h>
30#include <asm/heartbeat.h>
a80cad95
KM		 31#include <asm/sh_eth.h>
32#include <asm/clock.h>
3b9f2952 33#include <asm/suspend.h>
287c1297
KM		 34#include <cpu/sh7724.h>
35#include <mach-se/mach/se7724.h>
36
37/*
38 * SWx 1234 5678
39 * ------------------------------------
40 * SW31 : 1001 1100 : default
41 * SW32 : 0111 1111 : use on board flash
42 *
43 * SW41 : abxx xxxx -> a = 0 : Analog monitor
44 * 1 : Digital monitor
45 * b = 0 : VGA
4f324311
KM		 46 * 1 : 720p
47 */
48
49/*
50 * about 720p
51 *
52 * When you use 1280 x 720 lcdc output,
53 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
54 * and change SW41 to use 720p
287c1297
KM		 55 */
56
bec9fb07
KM		 57/*
58 * about sound
59 *
60 * This setup.c supports FSI slave mode.
61 * Please change J20, J21, J22 pin to 1-2 connection.
62 */
63
287c1297 64/* Heartbeat */
a09d2831
PM		 65static struct resource heartbeat_resource = {
66 .start = PA_LED,
67 .end = PA_LED,
68 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
287c1297
KM		 69};
70
71static struct platform_device heartbeat_device = {
72 .name = "heartbeat",
73 .id = -1,
a09d2831
PM		 74 .num_resources = 1,
75 .resource = &heartbeat_resource,
287c1297
KM		 76};
77
78/* LAN91C111 */
79static struct smc91x_platdata smc91x_info = {
80 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
81};
82
83static struct resource smc91x_eth_resources[] = {
84 [0] = {
85 .name = "SMC91C111" ,
86 .start = 0x1a300300,
87 .end = 0x1a30030f,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = IRQ0_SMC,
92 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
93 },
94};
95
96static struct platform_device smc91x_eth_device = {
97 .name = "smc91x",
98 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
99 .resource = smc91x_eth_resources,
100 .dev = {
101 .platform_data = &smc91x_info,
102 },
103};
104
105/* MTD */
106static struct mtd_partition nor_flash_partitions[] = {
107 {
108 .name = "uboot",
109 .offset = 0,
110 .size = (1 * 1024 * 1024),
111 .mask_flags = MTD_WRITEABLE, /* Read-only */
112 }, {
113 .name = "kernel",
114 .offset = MTDPART_OFS_APPEND,
115 .size = (2 * 1024 * 1024),
116 }, {
117 .name = "free-area",
118 .offset = MTDPART_OFS_APPEND,
119 .size = MTDPART_SIZ_FULL,
120 },
121};
122
123static struct physmap_flash_data nor_flash_data = {
124 .width = 2,
125 .parts = nor_flash_partitions,
126 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
127};
128
129static struct resource nor_flash_resources[] = {
130 [0] = {
131 .name = "NOR Flash",
132 .start = 0x00000000,
133 .end = 0x01ffffff,
134 .flags = IORESOURCE_MEM,
135 }
136};
137
138static struct platform_device nor_flash_device = {
139 .name = "physmap-flash",
140 .resource = nor_flash_resources,
141 .num_resources = ARRAY_SIZE(nor_flash_resources),
142 .dev = {
143 .platform_data = &nor_flash_data,
144 },
145};
146
147/* LCDC */
44432407
GL		 148const static struct fb_videomode lcdc_720p_modes[] = {
149 {
150 .name = "LB070WV1",
151 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 152 .xres = 1280,
153 .yres = 720,
154 .left_margin = 220,
155 .right_margin = 110,
156 .hsync_len = 40,
157 .upper_margin = 20,
158 .lower_margin = 5,
159 .vsync_len = 5,
44432407
GL		 160 },
161};
162
163const static struct fb_videomode lcdc_vga_modes[] = {
164 {
165 .name = "LB070WV1",
166 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 167 .xres = 640,
168 .yres = 480,
169 .left_margin = 105,
170 .right_margin = 50,
171 .hsync_len = 96,
172 .upper_margin = 33,
173 .lower_margin = 10,
174 .vsync_len = 2,
44432407
GL		 175 },
176};
177
287c1297
KM		 178static struct sh_mobile_lcdc_info lcdc_info = {
179 .clock_source = LCDC_CLK_EXTERNAL,
180 .ch[0] = {
181 .chan = LCDC_CHAN_MAINLCD,
182 .bpp = 16,
183 .clock_divider = 1,
287c1297
KM		 184 .lcd_size_cfg = { /* 7.0 inch */
185 .width = 152,
186 .height = 91,
187 },
188 .board_cfg = {
189 },
190 }
191};
192
193static struct resource lcdc_resources[] = {
194 [0] = {
195 .name = "LCDC",
196 .start = 0xfe940000,
a6f15ade 197 .end = 0xfe942fff,
287c1297
KM		 198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = 106,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device lcdc_device = {
207 .name = "sh_mobile_lcdc_fb",
208 .num_resources = ARRAY_SIZE(lcdc_resources),
209 .resource = lcdc_resources,
210 .dev = {
211 .platform_data = &lcdc_info,
212 },
df47cd09
MD		 213 .archdata = {
214 .hwblk_id = HWBLK_LCDC,
215 },
287c1297
KM		 216};
217
218/* CEU0 */
219static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
220 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
221};
222
223static struct resource ceu0_resources[] = {
224 [0] = {
225 .name = "CEU0",
226 .start = 0xfe910000,
227 .end = 0xfe91009f,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = 52,
232 .flags = IORESOURCE_IRQ,
233 },
234 [2] = {
235 /* place holder for contiguous memory */
236 },
237};
238
239static struct platform_device ceu0_device = {
240 .name = "sh_mobile_ceu",
241 .id = 0, /* "ceu0" clock */
242 .num_resources = ARRAY_SIZE(ceu0_resources),
243 .resource = ceu0_resources,
244 .dev = {
245 .platform_data = &sh_mobile_ceu0_info,
246 },
df47cd09
MD		 247 .archdata = {
248 .hwblk_id = HWBLK_CEU0,
249 },
287c1297
KM		 250};
251
252/* CEU1 */
253static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
254 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
255};
256
257static struct resource ceu1_resources[] = {
258 [0] = {
259 .name = "CEU1",
260 .start = 0xfe914000,
261 .end = 0xfe91409f,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = 63,
266 .flags = IORESOURCE_IRQ,
267 },
268 [2] = {
269 /* place holder for contiguous memory */
270 },
271};
272
273static struct platform_device ceu1_device = {
274 .name = "sh_mobile_ceu",
275 .id = 1, /* "ceu1" clock */
276 .num_resources = ARRAY_SIZE(ceu1_resources),
277 .resource = ceu1_resources,
278 .dev = {
279 .platform_data = &sh_mobile_ceu1_info,
280 },
df47cd09
MD		 281 .archdata = {
282 .hwblk_id = HWBLK_CEU1,
283 },
287c1297
KM		 284};
285
3e9ad52b 286/* FSI */
bec9fb07 287/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
560526f1 288static struct sh_fsi_platform_info fsi_info = {
f17c13ca 289 .porta_flags = SH_FSI_BRS_INV,
3e9ad52b
KM		 290};
291
292static struct resource fsi_resources[] = {
293 [0] = {
294 .name = "FSI",
295 .start = 0xFE3C0000,
296 .end = 0xFE3C021d,
297 .flags = IORESOURCE_MEM,
298 },
299 [1] = {
300 .start = 108,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct platform_device fsi_device = {
306 .name = "sh_fsi",
307 .id = 0,
308 .num_resources = ARRAY_SIZE(fsi_resources),
309 .resource = fsi_resources,
310 .dev = {
311 .platform_data = &fsi_info,
312 },
d53bd80c
KM		 313 .archdata = {
314 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
315 },
3e9ad52b
KM		 316};
317
c8d6bf9a
KM		 318static struct platform_device fsi_ak4642_device = {
319 .name = "sh_fsi_a_ak4642",
320};
321
9747e78b 322/* KEYSC in SoC (Needs SW33-2 set to ON) */
287c1297
KM		 323static struct sh_keysc_info keysc_info = {
324 .mode = SH_KEYSC_MODE_1,
29463c28 325 .scan_timing = 3,
287c1297
KM		 326 .delay = 50,
327 .keycodes = {
328 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
329 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
330 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
331 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
332 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
333 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
334 },
335};
336
337static struct resource keysc_resources[] = {
338 [0] = {
9747e78b
MD		 339 .name = "KEYSC",
340 .start = 0x044b0000,
341 .end = 0x044b000f,
287c1297
KM		 342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
9747e78b 345 .start = 79,
287c1297
KM		 346 .flags = IORESOURCE_IRQ,
347 },
348};
349
350static struct platform_device keysc_device = {
351 .name = "sh_keysc",
352 .id = 0, /* "keysc0" clock */
353 .num_resources = ARRAY_SIZE(keysc_resources),
354 .resource = keysc_resources,
355 .dev = {
356 .platform_data = &keysc_info,
357 },
df47cd09
MD		 358 .archdata = {
359 .hwblk_id = HWBLK_KEYSC,
360 },
287c1297
KM		 361};
362
a80cad95
KM		 363/* SH Eth */
364static struct resource sh_eth_resources[] = {
365 [0] = {
366 .start = SH_ETH_ADDR,
367 .end = SH_ETH_ADDR + 0x1FC,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = 91,
372 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
373 },
374};
375
560526f1 376static struct sh_eth_plat_data sh_eth_plat = {
a80cad95
KM		 377 .phy = 0x1f, /* SMSC LAN8187 */
378 .edmac_endian = EDMAC_LITTLE_ENDIAN,
379};
380
381static struct platform_device sh_eth_device = {
382 .name = "sh-eth",
383 .id = 0,
384 .dev = {
385 .platform_data = &sh_eth_plat,
386 },
387 .num_resources = ARRAY_SIZE(sh_eth_resources),
388 .resource = sh_eth_resources,
df47cd09
MD		 389 .archdata = {
390 .hwblk_id = HWBLK_ETHER,
391 },
a80cad95
KM		 392};
393
9731f4a2 394static struct r8a66597_platdata sh7724_usb0_host_data = {
719a72b7 395 .on_chip = 1,
9731f4a2
MD		 396};
397
398static struct resource sh7724_usb0_host_resources[] = {
399 [0] = {
400 .start = 0xa4d80000,
1bc265d0 401 .end = 0xa4d80124 - 1,
9731f4a2
MD		 402 .flags = IORESOURCE_MEM,
403 },
404 [1] = {
405 .start = 65,
406 .end = 65,
407 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
408 },
409};
410
411static struct platform_device sh7724_usb0_host_device = {
412 .name = "r8a66597_hcd",
413 .id = 0,
414 .dev = {
415 .dma_mask = NULL, /* not use dma */
416 .coherent_dma_mask = 0xffffffff,
417 .platform_data = &sh7724_usb0_host_data,
418 },
419 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
420 .resource = sh7724_usb0_host_resources,
df47cd09
MD		 421 .archdata = {
422 .hwblk_id = HWBLK_USB0,
423 },
9731f4a2
MD		 424};
425
f8f8c079
MD		 426static struct r8a66597_platdata sh7724_usb1_gadget_data = {
427 .on_chip = 1,
428};
429
430static struct resource sh7724_usb1_gadget_resources[] = {
431 [0] = {
432 .start = 0xa4d90000,
433 .end = 0xa4d90123,
434 .flags = IORESOURCE_MEM,
435 },
436 [1] = {
437 .start = 66,
438 .end = 66,
439 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
440 },
441};
442
443static struct platform_device sh7724_usb1_gadget_device = {
444 .name = "r8a66597_udc",
445 .id = 1, /* USB1 */
446 .dev = {
447 .dma_mask = NULL, /* not use dma */
448 .coherent_dma_mask = 0xffffffff,
449 .platform_data = &sh7724_usb1_gadget_data,
450 },
451 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
452 .resource = sh7724_usb1_gadget_resources,
453};
454
0f79af60
MD		 455static struct resource sdhi0_cn7_resources[] = {
456 [0] = {
457 .name = "SDHI0",
458 .start = 0x04ce0000,
459 .end = 0x04ce01ff,
460 .flags = IORESOURCE_MEM,
461 },
462 [1] = {
3844eadc 463 .start = 100,
0f79af60
MD		 464 .flags = IORESOURCE_IRQ,
465 },
466};
467
470ef1a7
GL		 468static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
469 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
470 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
a68a0784 471 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 472};
473
0f79af60
MD		 474static struct platform_device sdhi0_cn7_device = {
475 .name = "sh_mobile_sdhi",
5b380ec1 476 .id = 0,
0f79af60
MD		 477 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
478 .resource = sdhi0_cn7_resources,
470ef1a7
GL		 479 .dev = {
480 .platform_data = &sh7724_sdhi0_data,
481 },
0f79af60
MD		 482 .archdata = {
483 .hwblk_id = HWBLK_SDHI0,
484 },
485};
486
5b380ec1
MD		 487static struct resource sdhi1_cn8_resources[] = {
488 [0] = {
489 .name = "SDHI1",
490 .start = 0x04cf0000,
491 .end = 0x04cf01ff,
492 .flags = IORESOURCE_MEM,
493 },
494 [1] = {
3844eadc 495 .start = 23,
5b380ec1
MD		 496 .flags = IORESOURCE_IRQ,
497 },
498};
499
470ef1a7
GL		 500static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
501 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
502 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
a68a0784 503 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 504};
505
5b380ec1
MD		 506static struct platform_device sdhi1_cn8_device = {
507 .name = "sh_mobile_sdhi",
508 .id = 1,
509 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
510 .resource = sdhi1_cn8_resources,
470ef1a7
GL		 511 .dev = {
512 .platform_data = &sh7724_sdhi1_data,
513 },
5b380ec1
MD		 514 .archdata = {
515 .hwblk_id = HWBLK_SDHI1,
516 },
517};
518
bbb892aa
KM		 519/* IrDA */
520static struct resource irda_resources[] = {
521 [0] = {
522 .name = "IrDA",
523 .start = 0xA45D0000,
524 .end = 0xA45D0049,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = 20,
529 .flags = IORESOURCE_IRQ,
530 },
531};
532
533static struct platform_device irda_device = {
534 .name = "sh_sir",
535 .num_resources = ARRAY_SIZE(irda_resources),
536 .resource = irda_resources,
537};
538
2d151248
GL		 539#include <media/ak881x.h>
540#include <media/sh_vou.h>
541
560526f1 542static struct ak881x_pdata ak881x_pdata = {
2d151248
GL		 543 .flags = AK881X_IF_MODE_SLAVE,
544};
545
546static struct i2c_board_info ak8813 = {
547 /* With open J18 jumper address is 0x21 */
548 I2C_BOARD_INFO("ak8813", 0x20),
549 .platform_data = &ak881x_pdata,
550};
551
560526f1 552static struct sh_vou_pdata sh_vou_pdata = {
2d151248
GL		 553 .bus_fmt = SH_VOU_BUS_8BIT,
554 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
555 .board_info = &ak8813,
556 .i2c_adap = 0,
2d151248
GL		 557};
558
559static struct resource sh_vou_resources[] = {
560 [0] = {
561 .start = 0xfe960000,
562 .end = 0xfe962043,
563 .flags = IORESOURCE_MEM,
564 },
565 [1] = {
566 .start = 55,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
571static struct platform_device vou_device = {
572 .name = "sh-vou",
573 .id = -1,
574 .num_resources = ARRAY_SIZE(sh_vou_resources),
575 .resource = sh_vou_resources,
576 .dev = {
577 .platform_data = &sh_vou_pdata,
578 },
579 .archdata = {
580 .hwblk_id = HWBLK_VOU,
581 },
582};
583
287c1297
KM		 584static struct platform_device *ms7724se_devices[] __initdata = {
585 &heartbeat_device,
586 &smc91x_eth_device,
587 &lcdc_device,
588 &nor_flash_device,
589 &ceu0_device,
590 &ceu1_device,
591 &keysc_device,
a80cad95 592 &sh_eth_device,
9731f4a2 593 &sh7724_usb0_host_device,
f8f8c079 594 &sh7724_usb1_gadget_device,
3e9ad52b 595 &fsi_device,
c8d6bf9a 596 &fsi_ak4642_device,
0f79af60 597 &sdhi0_cn7_device,
5b380ec1 598 &sdhi1_cn8_device,
bbb892aa 599 &irda_device,
2d151248 600 &vou_device,
287c1297
KM		 601};
602
9f815a17
KM		 603/* I2C device */
604static struct i2c_board_info i2c0_devices[] = {
605 {
606 I2C_BOARD_INFO("ak4642", 0x12),
607 },
608};
609
a80cad95
KM		 610#define EEPROM_OP 0xBA206000
611#define EEPROM_ADR 0xBA206004
612#define EEPROM_DATA 0xBA20600C
613#define EEPROM_STAT 0xBA206010
614#define EEPROM_STRT 0xBA206014
615static int __init sh_eth_is_eeprom_ready(void)
616{
617 int t = 10000;
618
619 while (t--) {
9d56dd3b 620 if (!__raw_readw(EEPROM_STAT))
a80cad95 621 return 1;
c718aff2 622 udelay(1);
a80cad95
KM		 623 }
624
625 printk(KERN_ERR "ms7724se can not access to eeprom\n");
626 return 0;
627}
628
629static void __init sh_eth_init(void)
630{
631 int i;
8013cc9a 632 u16 mac;
a80cad95
KM		 633
634 /* check EEPROM status */
635 if (!sh_eth_is_eeprom_ready())
636 return;
637
638 /* read MAC addr from EEPROM */
639 for (i = 0 ; i < 3 ; i++) {
9d56dd3b
PM		 640 __raw_writew(0x0, EEPROM_OP); /* read */
641 __raw_writew(i*2, EEPROM_ADR);
642 __raw_writew(0x1, EEPROM_STRT);
a80cad95
KM		 643 if (!sh_eth_is_eeprom_ready())
644 return;
645
9d56dd3b 646 mac = __raw_readw(EEPROM_DATA);
8013cc9a
MD		 647 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
648 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
a80cad95 649 }
a80cad95
KM		 650}
651
287c1297
KM		 652#define SW4140 0xBA201000
653#define FPGA_OUT 0xBA200400
654#define PORT_HIZA 0xA4050158
9731f4a2 655#define PORT_MSELCRB 0xA4050182
287c1297
KM		 656
657#define SW41_A 0x0100
658#define SW41_B 0x0200
659#define SW41_C 0x0400
660#define SW41_D 0x0800
661#define SW41_E 0x1000
662#define SW41_F 0x2000
663#define SW41_G 0x4000
664#define SW41_H 0x8000
9731f4a2 665
3b9f2952
MD		 666extern char ms7724se_sdram_enter_start;
667extern char ms7724se_sdram_enter_end;
668extern char ms7724se_sdram_leave_start;
669extern char ms7724se_sdram_leave_end;
670
9f815a17
KM		 671
672static int __init arch_setup(void)
673{
674 /* enable I2C device */
675 i2c_register_board_info(0, i2c0_devices,
676 ARRAY_SIZE(i2c0_devices));
677 return 0;
678}
679arch_initcall(arch_setup);
680
287c1297
KM		 681static int __init devices_setup(void)
682{
9d56dd3b 683 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
16afc9fb 684 struct clk *clk;
2d151248 685 u16 fpga_out;
287c1297 686
3b9f2952 687 /* register board specific self-refresh code */
b67cf284
MD		 688 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
689 SUSP_SH_RSTANDBY,
3b9f2952
MD		 690 &ms7724se_sdram_enter_start,
691 &ms7724se_sdram_enter_end,
692 &ms7724se_sdram_leave_start,
693 &ms7724se_sdram_leave_end);
287c1297 694 /* Reset Release */
2d151248
GL		 695 fpga_out = __raw_readw(FPGA_OUT);
696 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
697 fpga_out &= ~((1 << 1) | /* LAN */
698 (1 << 4) | /* AK8813 PDN */
699 (1 << 5) | /* AK8813 RESET */
700 (1 << 6) | /* VIDEO DAC */
701 (1 << 7) | /* AK4643 */
702 (1 << 8) | /* IrDA */
703 (1 << 12) | /* USB0 */
704 (1 << 14)); /* RMII */
705 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
706
707 udelay(10);
708
709 /* AK8813 RESET */
710 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
711
712 udelay(10);
713
714 __raw_writew(fpga_out, FPGA_OUT);
287c1297 715
9731f4a2 716 /* turn on USB clocks, use external clock */
9d56dd3b 717 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
9731f4a2 718
7766e16b
MD		 719 /* Let LED9 show STATUS2 */
720 gpio_request(GPIO_FN_STATUS2, NULL);
721
722 /* Lit LED10 show STATUS0 */
723 gpio_request(GPIO_FN_STATUS0, NULL);
724
725 /* Lit LED11 show PDSTATUS */
726 gpio_request(GPIO_FN_PDSTATUS, NULL);
7766e16b 727
9731f4a2 728 /* enable USB0 port */
9d56dd3b 729 __raw_writew(0x0600, 0xa40501d4);
9731f4a2 730
f8f8c079 731 /* enable USB1 port */
9d56dd3b 732 __raw_writew(0x0600, 0xa4050192);
f8f8c079 733
287c1297
KM		 734 /* enable IRQ 0,1,2 */
735 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
736 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
737 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
738
739 /* enable SCIFA3 */
740 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
741 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
742 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
743 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
744 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
745
746 /* enable LCDC */
747 gpio_request(GPIO_FN_LCDD23, NULL);
748 gpio_request(GPIO_FN_LCDD22, NULL);
749 gpio_request(GPIO_FN_LCDD21, NULL);
750 gpio_request(GPIO_FN_LCDD20, NULL);
751 gpio_request(GPIO_FN_LCDD19, NULL);
752 gpio_request(GPIO_FN_LCDD18, NULL);
753 gpio_request(GPIO_FN_LCDD17, NULL);
754 gpio_request(GPIO_FN_LCDD16, NULL);
755 gpio_request(GPIO_FN_LCDD15, NULL);
756 gpio_request(GPIO_FN_LCDD14, NULL);
757 gpio_request(GPIO_FN_LCDD13, NULL);
758 gpio_request(GPIO_FN_LCDD12, NULL);
759 gpio_request(GPIO_FN_LCDD11, NULL);
760 gpio_request(GPIO_FN_LCDD10, NULL);
761 gpio_request(GPIO_FN_LCDD9, NULL);
762 gpio_request(GPIO_FN_LCDD8, NULL);
763 gpio_request(GPIO_FN_LCDD7, NULL);
764 gpio_request(GPIO_FN_LCDD6, NULL);
765 gpio_request(GPIO_FN_LCDD5, NULL);
766 gpio_request(GPIO_FN_LCDD4, NULL);
767 gpio_request(GPIO_FN_LCDD3, NULL);
768 gpio_request(GPIO_FN_LCDD2, NULL);
769 gpio_request(GPIO_FN_LCDD1, NULL);
770 gpio_request(GPIO_FN_LCDD0, NULL);
771 gpio_request(GPIO_FN_LCDDISP, NULL);
772 gpio_request(GPIO_FN_LCDHSYN, NULL);
773 gpio_request(GPIO_FN_LCDDCK, NULL);
774 gpio_request(GPIO_FN_LCDVSYN, NULL);
775 gpio_request(GPIO_FN_LCDDON, NULL);
776 gpio_request(GPIO_FN_LCDVEPWC, NULL);
777 gpio_request(GPIO_FN_LCDVCPWC, NULL);
778 gpio_request(GPIO_FN_LCDRD, NULL);
779 gpio_request(GPIO_FN_LCDLCLK, NULL);
9d56dd3b 780 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
287c1297
KM		 781
782 /* enable CEU0 */
783 gpio_request(GPIO_FN_VIO0_D15, NULL);
784 gpio_request(GPIO_FN_VIO0_D14, NULL);
785 gpio_request(GPIO_FN_VIO0_D13, NULL);
786 gpio_request(GPIO_FN_VIO0_D12, NULL);
787 gpio_request(GPIO_FN_VIO0_D11, NULL);
788 gpio_request(GPIO_FN_VIO0_D10, NULL);
789 gpio_request(GPIO_FN_VIO0_D9, NULL);
790 gpio_request(GPIO_FN_VIO0_D8, NULL);
791 gpio_request(GPIO_FN_VIO0_D7, NULL);
792 gpio_request(GPIO_FN_VIO0_D6, NULL);
793 gpio_request(GPIO_FN_VIO0_D5, NULL);
794 gpio_request(GPIO_FN_VIO0_D4, NULL);
795 gpio_request(GPIO_FN_VIO0_D3, NULL);
796 gpio_request(GPIO_FN_VIO0_D2, NULL);
797 gpio_request(GPIO_FN_VIO0_D1, NULL);
798 gpio_request(GPIO_FN_VIO0_D0, NULL);
799 gpio_request(GPIO_FN_VIO0_VD, NULL);
800 gpio_request(GPIO_FN_VIO0_CLK, NULL);
801 gpio_request(GPIO_FN_VIO0_FLD, NULL);
802 gpio_request(GPIO_FN_VIO0_HD, NULL);
84f7597c 803 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
287c1297
KM		 804
805 /* enable CEU1 */
806 gpio_request(GPIO_FN_VIO1_D7, NULL);
807 gpio_request(GPIO_FN_VIO1_D6, NULL);
808 gpio_request(GPIO_FN_VIO1_D5, NULL);
809 gpio_request(GPIO_FN_VIO1_D4, NULL);
810 gpio_request(GPIO_FN_VIO1_D3, NULL);
811 gpio_request(GPIO_FN_VIO1_D2, NULL);
812 gpio_request(GPIO_FN_VIO1_D1, NULL);
813 gpio_request(GPIO_FN_VIO1_D0, NULL);
814 gpio_request(GPIO_FN_VIO1_FLD, NULL);
815 gpio_request(GPIO_FN_VIO1_HD, NULL);
816 gpio_request(GPIO_FN_VIO1_VD, NULL);
817 gpio_request(GPIO_FN_VIO1_CLK, NULL);
84f7597c 818 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
287c1297
KM		 819
820 /* KEYSC */
821 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
822 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
823 gpio_request(GPIO_FN_KEYIN4, NULL);
824 gpio_request(GPIO_FN_KEYIN3, NULL);
825 gpio_request(GPIO_FN_KEYIN2, NULL);
826 gpio_request(GPIO_FN_KEYIN1, NULL);
827 gpio_request(GPIO_FN_KEYIN0, NULL);
828 gpio_request(GPIO_FN_KEYOUT3, NULL);
829 gpio_request(GPIO_FN_KEYOUT2, NULL);
830 gpio_request(GPIO_FN_KEYOUT1, NULL);
831 gpio_request(GPIO_FN_KEYOUT0, NULL);
832
3e9ad52b 833 /* enable FSI */
3e9ad52b 834 gpio_request(GPIO_FN_FSIMCKA, NULL);
c44352c5 835 gpio_request(GPIO_FN_FSIIASD, NULL);
3e9ad52b
KM		 836 gpio_request(GPIO_FN_FSIOASD, NULL);
837 gpio_request(GPIO_FN_FSIIABCK, NULL);
838 gpio_request(GPIO_FN_FSIIALRCK, NULL);
839 gpio_request(GPIO_FN_FSIOABCK, NULL);
840 gpio_request(GPIO_FN_FSIOALRCK, NULL);
841 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
3e9ad52b 842
16afc9fb
KM		 843 /* set SPU2 clock to 83.4 MHz */
844 clk = clk_get(NULL, "spu_clk");
193006f7 845 if (!IS_ERR(clk)) {
03c5ecd1
KM		 846 clk_set_rate(clk, clk_round_rate(clk, 83333333));
847 clk_put(clk);
848 }
16afc9fb 849
3e9ad52b 850 /* change parent of FSI A */
16afc9fb 851 clk = clk_get(NULL, "fsia_clk");
193006f7 852 if (!IS_ERR(clk)) {
e17ca5cf
NI		 853 /* 48kHz dummy clock was used to make sure 1/1 divide */
854 clk_set_rate(&sh7724_fsimcka_clk, 48000);
855 clk_set_parent(clk, &sh7724_fsimcka_clk);
856 clk_set_rate(clk, 48000);
03c5ecd1
KM		 857 clk_put(clk);
858 }
3e9ad52b 859
0f79af60
MD		 860 /* SDHI0 connected to cn7 */
861 gpio_request(GPIO_FN_SDHI0CD, NULL);
862 gpio_request(GPIO_FN_SDHI0WP, NULL);
863 gpio_request(GPIO_FN_SDHI0D3, NULL);
864 gpio_request(GPIO_FN_SDHI0D2, NULL);
865 gpio_request(GPIO_FN_SDHI0D1, NULL);
866 gpio_request(GPIO_FN_SDHI0D0, NULL);
867 gpio_request(GPIO_FN_SDHI0CMD, NULL);
868 gpio_request(GPIO_FN_SDHI0CLK, NULL);
869
5b380ec1
MD		 870 /* SDHI1 connected to cn8 */
871 gpio_request(GPIO_FN_SDHI1CD, NULL);
872 gpio_request(GPIO_FN_SDHI1WP, NULL);
873 gpio_request(GPIO_FN_SDHI1D3, NULL);
874 gpio_request(GPIO_FN_SDHI1D2, NULL);
875 gpio_request(GPIO_FN_SDHI1D1, NULL);
876 gpio_request(GPIO_FN_SDHI1D0, NULL);
877 gpio_request(GPIO_FN_SDHI1CMD, NULL);
878 gpio_request(GPIO_FN_SDHI1CLK, NULL);
879
bbb892aa
KM		 880 /* enable IrDA */
881 gpio_request(GPIO_FN_IRDA_OUT, NULL);
882 gpio_request(GPIO_FN_IRDA_IN, NULL);
883
a80cad95
KM		 884 /*
885 * enable SH-Eth
886 *
887 * please remove J33 pin from your board !!
888 *
889 * ms7724 board should not use GPIO_FN_LNKSTA pin
890 * So, This time PTX5 is set to input pin
891 */
892 gpio_request(GPIO_FN_RMII_RXD0, NULL);
893 gpio_request(GPIO_FN_RMII_RXD1, NULL);
894 gpio_request(GPIO_FN_RMII_TXD0, NULL);
895 gpio_request(GPIO_FN_RMII_TXD1, NULL);
896 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
897 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
898 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
899 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
900 gpio_request(GPIO_FN_MDIO, NULL);
901 gpio_request(GPIO_FN_MDC, NULL);
902 gpio_request(GPIO_PTX5, NULL);
903 gpio_direction_input(GPIO_PTX5);
904 sh_eth_init();
905
287c1297 906 if (sw & SW41_B) {
4f324311 907 /* 720p */
44432407
GL		 908 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
909 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
287c1297
KM		 910 } else {
911 /* VGA */
44432407
GL		 912 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
913 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
287c1297
KM		 914 }
915
916 if (sw & SW41_A) {
917 /* Digital monitor */
918 lcdc_info.ch[0].interface_type = RGB18;
919 lcdc_info.ch[0].flags = 0;
920 } else {
921 /* Analog monitor */
922 lcdc_info.ch[0].interface_type = RGB24;
923 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
924 }
925
2d151248
GL		 926 /* VOU */
927 gpio_request(GPIO_FN_DV_D15, NULL);
928 gpio_request(GPIO_FN_DV_D14, NULL);
929 gpio_request(GPIO_FN_DV_D13, NULL);
930 gpio_request(GPIO_FN_DV_D12, NULL);
931 gpio_request(GPIO_FN_DV_D11, NULL);
932 gpio_request(GPIO_FN_DV_D10, NULL);
933 gpio_request(GPIO_FN_DV_D9, NULL);
934 gpio_request(GPIO_FN_DV_D8, NULL);
935 gpio_request(GPIO_FN_DV_CLKI, NULL);
936 gpio_request(GPIO_FN_DV_CLK, NULL);
937 gpio_request(GPIO_FN_DV_VSYNC, NULL);
938 gpio_request(GPIO_FN_DV_HSYNC, NULL);
939
287c1297 940 return platform_add_devices(ms7724se_devices,
a80cad95 941 ARRAY_SIZE(ms7724se_devices));
287c1297
KM		 942}
943device_initcall(devices_setup);
944
945static struct sh_machine_vector mv_ms7724se __initmv = {
946 .mv_name = "ms7724se",
947 .mv_init_irq = init_se7724_IRQ,
948 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
949};
Linux kernel - Deliverables
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