[deliverable/linux.git] / arch / sh / boards / se / 770x / setup.c

/*
 * linux/arch/sh/boards/se/770x/setup.c
 *
 * Copyright (C) 2000  Kazumoto Kojima
 *
 * Hitachi SolutionEngine Support.
 *
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <asm/se.h>
#include <asm/io.h>
#include <asm/smc37c93x.h>
#include <asm/heartbeat.h>

void init_se_IRQ(void);

/*
 * Configure the Super I/O chip
 */
static void __init smsc_config(int index, int data)
{
	outb_p(index, INDEX_PORT);
	outb_p(data, DATA_PORT);
}

/* XXX: Another candidate for a more generic cchip machine vector */
static void __init smsc_setup(char **cmdline_p)
{
	outb_p(CONFIG_ENTER, CONFIG_PORT);
	outb_p(CONFIG_ENTER, CONFIG_PORT);

	/* FDC */
	smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
	smsc_config(ACTIVATE_INDEX, 0x01);
	smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */

	/* AUXIO (GPIO): to use IDE1 */
	smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
	smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
	smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */

	/* COM1 */
	smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
	smsc_config(ACTIVATE_INDEX, 0x01);
	smsc_config(IO_BASE_HI_INDEX, 0x03);
	smsc_config(IO_BASE_LO_INDEX, 0xf8);
	smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */

	/* COM2 */
	smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
	smsc_config(ACTIVATE_INDEX, 0x01);
	smsc_config(IO_BASE_HI_INDEX, 0x02);
	smsc_config(IO_BASE_LO_INDEX, 0xf8);
	smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */

	/* RTC */
	smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
	smsc_config(ACTIVATE_INDEX, 0x01);
	smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */

	/* XXX: PARPORT, KBD, and MOUSE will come here... */
	outb_p(CONFIG_EXIT, CONFIG_PORT);
}


static struct resource cf_ide_resources[] = {
	[0] = {
		.start  = PA_MRSHPC_IO + 0x1f0,
		.end    = PA_MRSHPC_IO + 0x1f0 + 8,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = PA_MRSHPC_IO + 0x1f0 + 0x206,
		.end    = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
		.flags  = IORESOURCE_MEM,
	},
	[2] = {
		.start  = IRQ_CFCARD,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device cf_ide_device  = {
	.name           = "pata_platform",
	.id             = -1,
	.num_resources  = ARRAY_SIZE(cf_ide_resources),
	.resource       = cf_ide_resources,
};

static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };

static struct heartbeat_data heartbeat_data = {
	.bit_pos	= heartbeat_bit_pos,
	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
};

static struct resource heartbeat_resources[] = {
	[0] = {
		.start	= PA_LED,
		.end	= PA_LED,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device heartbeat_device = {
	.name		= "heartbeat",
	.id		= -1,
	.dev	= {
		.platform_data	= &heartbeat_data,
	},
	.num_resources	= ARRAY_SIZE(heartbeat_resources),
	.resource	= heartbeat_resources,
};

static struct platform_device *se_devices[] __initdata = {
	&heartbeat_device,
	&cf_ide_device,
};

static int __init se_devices_setup(void)
{
	return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
}
device_initcall(se_devices_setup);

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_se __initmv = {
	.mv_name		= "SolutionEngine",
	.mv_setup		= smsc_setup,
#if defined(CONFIG_CPU_SH4)
	.mv_nr_irqs		= 48,
#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
	.mv_nr_irqs		= 32,
#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
	.mv_nr_irqs		= 61,
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
	.mv_nr_irqs		= 86,
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
	.mv_nr_irqs             = 104,
#endif

	.mv_inb			= se_inb,
	.mv_inw			= se_inw,
	.mv_inl			= se_inl,
	.mv_outb		= se_outb,
	.mv_outw		= se_outw,
	.mv_outl		= se_outl,

	.mv_inb_p		= se_inb_p,
	.mv_inw_p		= se_inw,
	.mv_inl_p		= se_inl,
	.mv_outb_p		= se_outb_p,
	.mv_outw_p		= se_outw,
	.mv_outl_p		= se_outl,

	.mv_insb		= se_insb,
	.mv_insw		= se_insw,
	.mv_insl		= se_insl,
	.mv_outsb		= se_outsb,
	.mv_outsw		= se_outsw,
	.mv_outsl		= se_outsl,

	.mv_init_irq		= init_se_IRQ,
};
Commit	Line	Data
aa4a5db5	1	/*
1da177e4 LT	2	* linux/arch/sh/boards/se/770x/setup.c
	3	*
	4	* Copyright (C) 2000 Kazumoto Kojima
	5	*
	6	* Hitachi SolutionEngine Support.
	7	*
	8	*/
1da177e4	9	#include <linux/init.h>
3b4d9539	10	#include <linux/platform_device.h>
711fa809	11	#include <asm/machvec.h>
373e68b5	12	#include <asm/se.h>
711fa809	13	#include <asm/io.h>
0c91c1a7	14	#include <asm/smc37c93x.h>
8786c952	15	#include <asm/heartbeat.h>
2c7834a6	16
2c7834a6	17	void init_se_IRQ(void);
1da177e4 LT	18
	19	/*
	20	* Configure the Super I/O chip
	21	*/
	22	static void __init smsc_config(int index, int data)
	23	{
	24	outb_p(index, INDEX_PORT);
	25	outb_p(data, DATA_PORT);
	26	}
	27
2c7834a6 PM	28	/* XXX: Another candidate for a more generic cchip machine vector */
2c7834a6 PM	29	static void __init smsc_setup(char **cmdline_p)
1da177e4 LT	30	{
	31	outb_p(CONFIG_ENTER, CONFIG_PORT);
	32	outb_p(CONFIG_ENTER, CONFIG_PORT);
	33
	34	/* FDC */
	35	smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
	36	smsc_config(ACTIVATE_INDEX, 0x01);
	37	smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
	38
1da177e4 LT	39	/* AUXIO (GPIO): to use IDE1 */
	40	smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
	41	smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
	42	smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
	43
	44	/* COM1 */
	45	smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
	46	smsc_config(ACTIVATE_INDEX, 0x01);
	47	smsc_config(IO_BASE_HI_INDEX, 0x03);
	48	smsc_config(IO_BASE_LO_INDEX, 0xf8);
	49	smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
	50
	51	/* COM2 */
	52	smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
	53	smsc_config(ACTIVATE_INDEX, 0x01);
	54	smsc_config(IO_BASE_HI_INDEX, 0x02);
	55	smsc_config(IO_BASE_LO_INDEX, 0xf8);
	56	smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
	57
	58	/* RTC */
	59	smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
	60	smsc_config(ACTIVATE_INDEX, 0x01);
	61	smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
	62
	63	/* XXX: PARPORT, KBD, and MOUSE will come here... */
	64	outb_p(CONFIG_EXIT, CONFIG_PORT);
	65	}
	66
f987fc88 NI	67
	68	static struct resource cf_ide_resources[] = {
	69	[0] = {
	70	.start = PA_MRSHPC_IO + 0x1f0,
	71	.end = PA_MRSHPC_IO + 0x1f0 + 8,
	72	.flags = IORESOURCE_MEM,
	73	},
	74	[1] = {
	75	.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
	76	.end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
	77	.flags = IORESOURCE_MEM,
	78	},
	79	[2] = {
2a8ff459	80	.start = IRQ_CFCARD,
f987fc88 NI	81	.flags = IORESOURCE_IRQ,
	82	},
	83	};
	84
	85	static struct platform_device cf_ide_device = {
	86	.name = "pata_platform",
	87	.id = -1,
	88	.num_resources = ARRAY_SIZE(cf_ide_resources),
	89	.resource = cf_ide_resources,
	90	};
	91
3b4d9539 PM	92	static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
3b4d9539 PM	93
8786c952 PM	94	static struct heartbeat_data heartbeat_data = {
	95	.bit_pos = heartbeat_bit_pos,
	96	.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
	97	};
	98
3b4d9539 PM	99	static struct resource heartbeat_resources[] = {
	100	[0] = {
	101	.start = PA_LED,
a1fd306b	102	.end = PA_LED,
3b4d9539 PM	103	.flags = IORESOURCE_MEM,
	104	},
	105	};
	106
	107	static struct platform_device heartbeat_device = {
	108	.name = "heartbeat",
	109	.id = -1,
	110	.dev = {
a1fd306b	111	.platform_data = &heartbeat_data,
3b4d9539 PM	112	},
	113	.num_resources = ARRAY_SIZE(heartbeat_resources),
	114	.resource = heartbeat_resources,
	115	};
	116
	117	static struct platform_device *se_devices[] __initdata = {
	118	&heartbeat_device,
f987fc88	119	&cf_ide_device,
3b4d9539 PM	120	};
	121
	122	static int __init se_devices_setup(void)
	123	{
	124	return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
	125	}
9465a54f	126	device_initcall(se_devices_setup);
3b4d9539	127
1da177e4	128	/*
2c7834a6	129	* The Machine Vector
1da177e4	130	*/
82f81f47	131	static struct sh_machine_vector mv_se __initmv = {
2c7834a6 PM	132	.mv_name = "SolutionEngine",
	133	.mv_setup = smsc_setup,
	134	#if defined(CONFIG_CPU_SH4)
	135	.mv_nr_irqs = 48,
	136	#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
	137	.mv_nr_irqs = 32,
	138	#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
	139	.mv_nr_irqs = 61,
	140	#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
	141	.mv_nr_irqs = 86,
9465a54f NI	142	#elif defined(CONFIG_CPU_SUBTYPE_SH7710) \|\| defined(CONFIG_CPU_SUBTYPE_SH7712)
9465a54f NI	143	.mv_nr_irqs = 104,
2c7834a6 PM	144	#endif
	145
	146	.mv_inb = se_inb,
	147	.mv_inw = se_inw,
	148	.mv_inl = se_inl,
	149	.mv_outb = se_outb,
	150	.mv_outw = se_outw,
	151	.mv_outl = se_outl,
	152
	153	.mv_inb_p = se_inb_p,
	154	.mv_inw_p = se_inw,
	155	.mv_inl_p = se_inl,
	156	.mv_outb_p = se_outb_p,
	157	.mv_outw_p = se_outw,
	158	.mv_outl_p = se_outl,
	159
	160	.mv_insb = se_insb,
	161	.mv_insw = se_insw,
	162	.mv_insl = se_insl,
	163	.mv_outsb = se_outsb,
	164	.mv_outsw = se_outsw,
	165	.mv_outsl = se_outsl,
	166
	167	.mv_init_irq = init_se_IRQ,
2c7834a6	168	};