[deliverable/linux.git] / arch / sh / drivers / dma / dma-sh.c

/*
 * arch/sh/drivers/dma/dma-sh.c
 *
 * SuperH On-chip DMAC Support
 *
 * Copyright (C) 2000 Takashi YOSHII
 * Copyright (C) 2003, 2004 Paul Mundt
 * Copyright (C) 2005 Andriy Skulysh
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <mach-dreamcast/mach/dma.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/dma-sh.h>

#if defined(DMAE1_IRQ)
#define NR_DMAE		2
#else
#define NR_DMAE		1
#endif

static const char *dmae_name[] = {
	"DMAC Address Error0", "DMAC Address Error1"
};

static inline unsigned int get_dmte_irq(unsigned int chan)
{
	unsigned int irq = 0;
	if (chan < ARRAY_SIZE(dmte_irq_map))
		irq = dmte_irq_map[chan];

#if defined(CONFIG_SH_DMA_IRQ_MULTI)
	if (irq > DMTE6_IRQ)
		return DMTE6_IRQ;
	return DMTE0_IRQ;
#else
	return irq;
#endif
}

/*
 * We determine the correct shift size based off of the CHCR transmit size
 * for the given channel. Since we know that it will take:
 *
 *	info->count >> ts_shift[transmit_size]
 *
 * iterations to complete the transfer.
 */
static unsigned int ts_shift[] = TS_SHIFT;
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
	u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
	int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
		((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);

	return ts_shift[cnt];
}

/*
 * The transfer end interrupt must read the chcr register to end the
 * hardware interrupt active condition.
 * Besides that it needs to waken any waiting process, which should handle
 * setting up the next transfer.
 */
static irqreturn_t dma_tei(int irq, void *dev_id)
{
	struct dma_channel *chan = dev_id;
	u32 chcr;

	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);

	if (!(chcr & CHCR_TE))
		return IRQ_NONE;

	chcr &= ~(CHCR_IE | CHCR_DE);
	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

	wake_up(&chan->wait_queue);

	return IRQ_HANDLED;
}

static int sh_dmac_request_dma(struct dma_channel *chan)
{
	if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
		return 0;

	return request_irq(get_dmte_irq(chan->chan), dma_tei,
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
				IRQF_SHARED,
#else
				IRQF_DISABLED,
#endif
				chan->dev_id, chan);
}

static void sh_dmac_free_dma(struct dma_channel *chan)
{
	free_irq(get_dmte_irq(chan->chan), chan);
}

static int
sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
{
	if (!chcr)
		chcr = RS_DUAL | CHCR_IE;

	if (chcr & CHCR_IE) {
		chcr &= ~CHCR_IE;
		chan->flags |= DMA_TEI_CAPABLE;
	} else {
		chan->flags &= ~DMA_TEI_CAPABLE;
	}

	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

	chan->flags |= DMA_CONFIGURED;
	return 0;
}

static void sh_dmac_enable_dma(struct dma_channel *chan)
{
	int irq;
	u32 chcr;

	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
	chcr |= CHCR_DE;

	if (chan->flags & DMA_TEI_CAPABLE)
		chcr |= CHCR_IE;

	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

	if (chan->flags & DMA_TEI_CAPABLE) {
		irq = get_dmte_irq(chan->chan);
		enable_irq(irq);
	}
}

static void sh_dmac_disable_dma(struct dma_channel *chan)
{
	int irq;
	u32 chcr;

	if (chan->flags & DMA_TEI_CAPABLE) {
		irq = get_dmte_irq(chan->chan);
		disable_irq(irq);
	}

	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
	chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
}

static int sh_dmac_xfer_dma(struct dma_channel *chan)
{
	/*
	 * If we haven't pre-configured the channel with special flags, use
	 * the defaults.
	 */
	if (unlikely(!(chan->flags & DMA_CONFIGURED)))
		sh_dmac_configure_channel(chan, 0);

	sh_dmac_disable_dma(chan);

	/*
	 * Single-address mode usage note!
	 *
	 * It's important that we don't accidentally write any value to SAR/DAR
	 * (this includes 0) that hasn't been directly specified by the user if
	 * we're in single-address mode.
	 *
	 * In this case, only one address can be defined, anything else will
	 * result in a DMA address error interrupt (at least on the SH-4),
	 * which will subsequently halt the transfer.
	 *
	 * Channel 2 on the Dreamcast is a special case, as this is used for
	 * cascading to the PVR2 DMAC. In this case, we still need to write
	 * SAR and DAR, regardless of value, in order for cascading to work.
	 */
	if (chan->sar || (mach_is_dreamcast() &&
			  chan->chan == PVR2_CASCADE_CHAN))
		ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
	if (chan->dar || (mach_is_dreamcast() &&
			  chan->chan == PVR2_CASCADE_CHAN))
		ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));

	ctrl_outl(chan->count >> calc_xmit_shift(chan),
		(dma_base_addr[chan->chan] + TCR));

	sh_dmac_enable_dma(chan);

	return 0;
}

static int sh_dmac_get_dma_residue(struct dma_channel *chan)
{
	if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
		return 0;

	return ctrl_inl(dma_base_addr[chan->chan] + TCR)
		 << calc_xmit_shift(chan);
}

static inline int dmaor_reset(int no)
{
	unsigned long dmaor = dmaor_read_reg(no);

	/* Try to clear the error flags first, incase they are set */
	dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
	dmaor_write_reg(no, dmaor);

	dmaor |= DMAOR_INIT;
	dmaor_write_reg(no, dmaor);

	/* See if we got an error again */
	if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
		printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
		return -EINVAL;
	}

	return 0;
}

#if defined(CONFIG_CPU_SH4)
static irqreturn_t dma_err(int irq, void *dummy)
{
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
	int cnt = 0;
	switch (irq) {
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
	case DMTE6_IRQ:
		cnt++;
#endif
	case DMTE0_IRQ:
		if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
			disable_irq(irq);
			/* DMA multi and error IRQ */
			return IRQ_HANDLED;
		}
	default:
		return IRQ_NONE;
	}
#else
	dmaor_reset(0);
#if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
		defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
		defined(CONFIG_CPU_SUBTYPE_SH7785)
	dmaor_reset(1);
#endif
	disable_irq(irq);

	return IRQ_HANDLED;
#endif
}
#endif

static struct dma_ops sh_dmac_ops = {
	.request	= sh_dmac_request_dma,
	.free		= sh_dmac_free_dma,
	.get_residue	= sh_dmac_get_dma_residue,
	.xfer		= sh_dmac_xfer_dma,
	.configure	= sh_dmac_configure_channel,
};

static struct dma_info sh_dmac_info = {
	.name		= "sh_dmac",
	.nr_channels	= CONFIG_NR_ONCHIP_DMA_CHANNELS,
	.ops		= &sh_dmac_ops,
	.flags		= DMAC_CHANNELS_TEI_CAPABLE,
};

#ifdef CONFIG_CPU_SH4
static unsigned int get_dma_error_irq(int n)
{
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
	return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
#else
	return (n == 0) ? DMAE0_IRQ :
#if defined(DMAE1_IRQ)
				DMAE1_IRQ;
#else
				-1;
#endif
#endif
}
#endif

static int __init sh_dmac_init(void)
{
	struct dma_info *info = &sh_dmac_info;
	int i;

#ifdef CONFIG_CPU_SH4
	int n;

	for (n = 0; n < NR_DMAE; n++) {
		i = request_irq(get_dma_error_irq(n), dma_err,
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
				IRQF_SHARED,
#else
				IRQF_DISABLED,
#endif
				dmae_name[n], (void *)dmae_name[n]);
		if (unlikely(i < 0)) {
			printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
			return i;
		}
	}
#endif /* CONFIG_CPU_SH4 */

	/*
	 * Initialize DMAOR, and clean up any error flags that may have
	 * been set.
	 */
	i = dmaor_reset(0);
	if (unlikely(i != 0))
		return i;
#if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
		defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
		defined(CONFIG_CPU_SUBTYPE_SH7785)
	i = dmaor_reset(1);
	if (unlikely(i != 0))
		return i;
#endif

	return register_dmac(info);
}

static void __exit sh_dmac_exit(void)
{
#ifdef CONFIG_CPU_SH4
	int n;

	for (n = 0; n < NR_DMAE; n++) {
		free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
	}
#endif /* CONFIG_CPU_SH4 */
	unregister_dmac(&sh_dmac_info);
}

subsys_initcall(sh_dmac_init);
module_exit(sh_dmac_exit);

MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/drivers/dma/dma-sh.c
	3	*
	4	* SuperH On-chip DMAC Support
	5	*
	6	* Copyright (C) 2000 Takashi YOSHII
	7	* Copyright (C) 2003, 2004 Paul Mundt
0d831770	8	* Copyright (C) 2005 Andriy Skulysh
1da177e4 LT	9	*
	10	* This file is subject to the terms and conditions of the GNU General Public
	11	* License. See the file "COPYING" in the main directory of this archive
	12	* for more details.
	13	*/
1da177e4	14	#include <linux/init.h>
1da177e4 LT	15	#include <linux/interrupt.h>
1da177e4 LT	16	#include <linux/module.h>
71b8064e	17	#include <mach-dreamcast/mach/dma.h>
1da177e4 LT	18	#include <asm/dma.h>
1da177e4 LT	19	#include <asm/io.h>
71b973a4 NI	20	#include <asm/dma-sh.h>
71b973a4 NI	21
71b973a4 NI	22	#if defined(DMAE1_IRQ)
	23	#define NR_DMAE 2
	24	#else
	25	#define NR_DMAE 1
bd71ab88	26	#endif
71b973a4 NI	27
	28	static const char *dmae_name[] = {
	29	"DMAC Address Error0", "DMAC Address Error1"
bd71ab88	30	};
1da177e4	31
bd71ab88 JL	32	static inline unsigned int get_dmte_irq(unsigned int chan)
	33	{
	34	unsigned int irq = 0;
9f8a5e3a ML	35	if (chan < ARRAY_SIZE(dmte_irq_map))
9f8a5e3a ML	36	irq = dmte_irq_map[chan];
71b973a4	37
988f831d	38	#if defined(CONFIG_SH_DMA_IRQ_MULTI)
71b973a4 NI	39	if (irq > DMTE6_IRQ)
	40	return DMTE6_IRQ;
	41	return DMTE0_IRQ;
	42	#else
1da177e4	43	return irq;
71b973a4	44	#endif
1da177e4 LT	45	}
	46
	47	/*
	48	* We determine the correct shift size based off of the CHCR transmit size
	49	* for the given channel. Since we know that it will take:
	50	*
	51	* info->count >> ts_shift[transmit_size]
	52	*
	53	* iterations to complete the transfer.
	54	*/
623b4ac4	55	static unsigned int ts_shift[] = TS_SHIFT;
1da177e4 LT	56	static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
1da177e4 LT	57	{
71b973a4	58	u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
623b4ac4 GL	59	int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) \|
623b4ac4 GL	60	((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
1da177e4	61
623b4ac4	62	return ts_shift[cnt];
1da177e4 LT	63	}
	64
	65	/*
	66	* The transfer end interrupt must read the chcr register to end the
	67	* hardware interrupt active condition.
	68	* Besides that it needs to waken any waiting process, which should handle
	69	* setting up the next transfer.
	70	*/
35f3c518	71	static irqreturn_t dma_tei(int irq, void *dev_id)
1da177e4	72	{
35f3c518	73	struct dma_channel *chan = dev_id;
1da177e4 LT	74	u32 chcr;
1da177e4 LT	75
71b973a4	76	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
1da177e4 LT	77
	78	if (!(chcr & CHCR_TE))
	79	return IRQ_NONE;
	80
	81	chcr &= ~(CHCR_IE \| CHCR_DE);
71b973a4	82	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
1da177e4 LT	83
	84	wake_up(&chan->wait_queue);
	85
	86	return IRQ_HANDLED;
	87	}
	88
	89	static int sh_dmac_request_dma(struct dma_channel *chan)
	90	{
b2d7c7f7	91	if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
9e3043c0 PM	92	return 0;
9e3043c0 PM	93
1da177e4	94	return request_irq(get_dmte_irq(chan->chan), dma_tei,
988f831d	95	#if defined(CONFIG_SH_DMA_IRQ_MULTI)
71b973a4 NI	96	IRQF_SHARED,
	97	#else
	98	IRQF_DISABLED,
	99	#endif
	100	chan->dev_id, chan);
1da177e4 LT	101	}
	102
	103	static void sh_dmac_free_dma(struct dma_channel *chan)
	104	{
	105	free_irq(get_dmte_irq(chan->chan), chan);
	106	}
	107
9f8a5e3a	108	static int
0d831770	109	sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
1da177e4 LT	110	{
1da177e4 LT	111	if (!chcr)
0d831770 PM	112	chcr = RS_DUAL \| CHCR_IE;
	113
	114	if (chcr & CHCR_IE) {
	115	chcr &= ~CHCR_IE;
	116	chan->flags \|= DMA_TEI_CAPABLE;
	117	} else {
	118	chan->flags &= ~DMA_TEI_CAPABLE;
	119	}
1da177e4	120
71b973a4	121	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
1da177e4 LT	122
1da177e4 LT	123	chan->flags \|= DMA_CONFIGURED;
9f8a5e3a	124	return 0;
1da177e4 LT	125	}
	126
	127	static void sh_dmac_enable_dma(struct dma_channel *chan)
	128	{
0d831770	129	int irq;
1da177e4 LT	130	u32 chcr;
1da177e4 LT	131
71b973a4	132	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
0d831770 PM	133	chcr \|= CHCR_DE;
	134
	135	if (chan->flags & DMA_TEI_CAPABLE)
	136	chcr \|= CHCR_IE;
	137
71b973a4	138	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
1da177e4	139
0d831770 PM	140	if (chan->flags & DMA_TEI_CAPABLE) {
	141	irq = get_dmte_irq(chan->chan);
	142	enable_irq(irq);
	143	}
1da177e4 LT	144	}
	145
	146	static void sh_dmac_disable_dma(struct dma_channel *chan)
	147	{
0d831770	148	int irq;
1da177e4 LT	149	u32 chcr;
1da177e4 LT	150
0d831770 PM	151	if (chan->flags & DMA_TEI_CAPABLE) {
	152	irq = get_dmte_irq(chan->chan);
	153	disable_irq(irq);
	154	}
1da177e4	155
71b973a4	156	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
1da177e4	157	chcr &= ~(CHCR_DE \| CHCR_TE \| CHCR_IE);
71b973a4	158	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
1da177e4 LT	159	}
	160
	161	static int sh_dmac_xfer_dma(struct dma_channel *chan)
	162	{
	163	/*
	164	* If we haven't pre-configured the channel with special flags, use
	165	* the defaults.
	166	*/
0d831770	167	if (unlikely(!(chan->flags & DMA_CONFIGURED)))
1da177e4 LT	168	sh_dmac_configure_channel(chan, 0);
	169
	170	sh_dmac_disable_dma(chan);
	171
	172	/*
	173	* Single-address mode usage note!
	174	*
	175	* It's important that we don't accidentally write any value to SAR/DAR
	176	* (this includes 0) that hasn't been directly specified by the user if
	177	* we're in single-address mode.
	178	*
	179	* In this case, only one address can be defined, anything else will
	180	* result in a DMA address error interrupt (at least on the SH-4),
	181	* which will subsequently halt the transfer.
	182	*
	183	* Channel 2 on the Dreamcast is a special case, as this is used for
	184	* cascading to the PVR2 DMAC. In this case, we still need to write
	185	* SAR and DAR, regardless of value, in order for cascading to work.
	186	*/
0d831770 PM	187	if (chan->sar \|\| (mach_is_dreamcast() &&
0d831770 PM	188	chan->chan == PVR2_CASCADE_CHAN))
71b973a4	189	ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
0d831770 PM	190	if (chan->dar \|\| (mach_is_dreamcast() &&
0d831770 PM	191	chan->chan == PVR2_CASCADE_CHAN))
71b973a4	192	ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
1da177e4	193
71b973a4 NI	194	ctrl_outl(chan->count >> calc_xmit_shift(chan),
71b973a4 NI	195	(dma_base_addr[chan->chan] + TCR));
1da177e4 LT	196
	197	sh_dmac_enable_dma(chan);
	198
	199	return 0;
	200	}
	201
	202	static int sh_dmac_get_dma_residue(struct dma_channel *chan)
	203	{
71b973a4	204	if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
1da177e4 LT	205	return 0;
1da177e4 LT	206
71b973a4 NI	207	return ctrl_inl(dma_base_addr[chan->chan] + TCR)
71b973a4 NI	208	<< calc_xmit_shift(chan);
1da177e4 LT	209	}
1da177e4 LT	210
71b973a4	211	static inline int dmaor_reset(int no)
1da177e4	212	{
71b973a4	213	unsigned long dmaor = dmaor_read_reg(no);
0d831770 PM	214
	215	/* Try to clear the error flags first, incase they are set */
	216	dmaor &= ~(DMAOR_NMIF \| DMAOR_AE);
71b973a4	217	dmaor_write_reg(no, dmaor);
1da177e4	218
0d831770	219	dmaor \|= DMAOR_INIT;
71b973a4	220	dmaor_write_reg(no, dmaor);
1da177e4	221
0d831770	222	/* See if we got an error again */
71b973a4	223	if ((dmaor_read_reg(no) & (DMAOR_AE \| DMAOR_NMIF))) {
0d831770 PM	224	printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
	225	return -EINVAL;
	226	}
1da177e4	227
0d831770 PM	228	return 0;
	229	}
	230
	231	#if defined(CONFIG_CPU_SH4)
35f3c518	232	static irqreturn_t dma_err(int irq, void *dummy)
0d831770	233	{
988f831d	234	#if defined(CONFIG_SH_DMA_IRQ_MULTI)
71b973a4 NI	235	int cnt = 0;
	236	switch (irq) {
	237	#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
	238	case DMTE6_IRQ:
	239	cnt++;
	240	#endif
	241	case DMTE0_IRQ:
	242	if (dmaor_read_reg(cnt) & (DMAOR_NMIF \| DMAOR_AE)) {
	243	disable_irq(irq);
	244	/* DMA multi and error IRQ */
	245	return IRQ_HANDLED;
	246	}
	247	default:
	248	return IRQ_NONE;
	249	}
	250	#else
	251	dmaor_reset(0);
	252	#if defined(CONFIG_CPU_SUBTYPE_SH7723) \|\| \
	253	defined(CONFIG_CPU_SUBTYPE_SH7780) \|\| \
	254	defined(CONFIG_CPU_SUBTYPE_SH7785)
	255	dmaor_reset(1);
	256	#endif
1da177e4 LT	257	disable_irq(irq);
	258
	259	return IRQ_HANDLED;
71b973a4	260	#endif
1da177e4 LT	261	}
	262	#endif
	263
	264	static struct dma_ops sh_dmac_ops = {
	265	.request = sh_dmac_request_dma,
	266	.free = sh_dmac_free_dma,
	267	.get_residue = sh_dmac_get_dma_residue,
	268	.xfer = sh_dmac_xfer_dma,
	269	.configure = sh_dmac_configure_channel,
	270	};
	271
	272	static struct dma_info sh_dmac_info = {
0d831770 PM	273	.name = "sh_dmac",
0d831770 PM	274	.nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
1da177e4 LT	275	.ops = &sh_dmac_ops,
	276	.flags = DMAC_CHANNELS_TEI_CAPABLE,
	277	};
	278
02ebd32f	279	#ifdef CONFIG_CPU_SH4
71b973a4 NI	280	static unsigned int get_dma_error_irq(int n)
71b973a4 NI	281	{
988f831d	282	#if defined(CONFIG_SH_DMA_IRQ_MULTI)
71b973a4 NI	283	return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
	284	#else
	285	return (n == 0) ? DMAE0_IRQ :
	286	#if defined(DMAE1_IRQ)
	287	DMAE1_IRQ;
	288	#else
	289	-1;
	290	#endif
	291	#endif
	292	}
02ebd32f	293	#endif
71b973a4	294
1da177e4 LT	295	static int __init sh_dmac_init(void)
	296	{
	297	struct dma_info *info = &sh_dmac_info;
	298	int i;
	299
	300	#ifdef CONFIG_CPU_SH4
71b973a4 NI	301	int n;
	302
	303	for (n = 0; n < NR_DMAE; n++) {
	304	i = request_irq(get_dma_error_irq(n), dma_err,
988f831d	305	#if defined(CONFIG_SH_DMA_IRQ_MULTI)
71b973a4 NI	306	IRQF_SHARED,
	307	#else
	308	IRQF_DISABLED,
1da177e4	309	#endif
71b973a4 NI	310	dmae_name[n], (void *)dmae_name[n]);
	311	if (unlikely(i < 0)) {
	312	printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
	313	return i;
	314	}
	315	}
	316	#endif /* CONFIG_CPU_SH4 */
1da177e4	317
0d831770 PM	318	/*
	319	* Initialize DMAOR, and clean up any error flags that may have
	320	* been set.
	321	*/
71b973a4 NI	322	i = dmaor_reset(0);
	323	if (unlikely(i != 0))
	324	return i;
	325	#if defined(CONFIG_CPU_SUBTYPE_SH7723) \|\| \
	326	defined(CONFIG_CPU_SUBTYPE_SH7780) \|\| \
	327	defined(CONFIG_CPU_SUBTYPE_SH7785)
	328	i = dmaor_reset(1);
9e3043c0	329	if (unlikely(i != 0))
0d831770	330	return i;
71b973a4	331	#endif
1da177e4 LT	332
	333	return register_dmac(info);
	334	}
	335
	336	static void __exit sh_dmac_exit(void)
	337	{
	338	#ifdef CONFIG_CPU_SH4
71b973a4 NI	339	int n;
	340
	341	for (n = 0; n < NR_DMAE; n++) {
	342	free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
	343	}
	344	#endif /* CONFIG_CPU_SH4 */
0d831770	345	unregister_dmac(&sh_dmac_info);
1da177e4 LT	346	}
	347
	348	subsys_initcall(sh_dmac_init);
	349	module_exit(sh_dmac_exit);
	350
0d831770 PM	351	MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
0d831770 PM	352	MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
1da177e4	353	MODULE_LICENSE("GPL");