[deliverable/linux.git] / arch / sh / drivers / pci / ops-sh4.c

/*
 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
 *
 * Copyright (C) 2002 - 2009  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License v2. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/addrspace.h>
#include "pci-sh4.h"

/*
 * Direct access to PCI hardware...
 */
#define CONFIG_CMD(bus, devfn, where) \
	(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))

/*
 * Functions for accessing PCI configuration space with type 1 accesses
 */
static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
			   int where, int size, u32 *val)
{
	struct pci_channel *chan = bus->sysdata;
	unsigned long flags;
	u32 data;

	/*
	 * PCIPDR may only be accessed as 32 bit words,
	 * so we must do byte alignment by hand
	 */
	raw_spin_lock_irqsave(&pci_config_lock, flags);
	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
	data = pci_read_reg(chan, SH4_PCIPDR);
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);

	switch (size) {
	case 1:
		*val = (data >> ((where & 3) << 3)) & 0xff;
		break;
	case 2:
		*val = (data >> ((where & 2) << 3)) & 0xffff;
		break;
	case 4:
		*val = data;
		break;
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}

	return PCIBIOS_SUCCESSFUL;
}

/*
 * Since SH4 only does 32bit access we'll have to do a read,
 * mask,write operation.
 * We'll allow an odd byte offset, though it should be illegal.
 */
static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
			 int where, int size, u32 val)
{
	struct pci_channel *chan = bus->sysdata;
	unsigned long flags;
	int shift;
	u32 data;

	raw_spin_lock_irqsave(&pci_config_lock, flags);
	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
	data = pci_read_reg(chan, SH4_PCIPDR);
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);

	switch (size) {
	case 1:
		shift = (where & 3) << 3;
		data &= ~(0xff << shift);
		data |= ((val & 0xff) << shift);
		break;
	case 2:
		shift = (where & 2) << 3;
		data &= ~(0xffff << shift);
		data |= ((val & 0xffff) << shift);
		break;
	case 4:
		data = val;
		break;
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}

	pci_write_reg(chan, data, SH4_PCIPDR);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops sh4_pci_ops = {
	.read		= sh4_pci_read,
	.write		= sh4_pci_write,
};

int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
{
	/* Nothing to do. */
	return 0;
}
Commit	Line	Data
959f85f8 PM	1	/*
	2	* Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
	3	*
7e4ba0d7	4	* Copyright (C) 2002 - 2009 Paul Mundt
959f85f8 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License v2. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/pci.h>
7e4ba0d7	11	#include <linux/io.h>
39a90865	12	#include <linux/spinlock.h>
959f85f8	13	#include <asm/addrspace.h>
959f85f8 PM	14	#include "pci-sh4.h"
	15
	16	/*
	17	* Direct access to PCI hardware...
	18	*/
	19	#define CONFIG_CMD(bus, devfn, where) \
ef407bee	20	(0x80000000 \| (bus->number << 16) \| (devfn << 8) \| (where & ~3))
959f85f8	21
959f85f8 PM	22	/*
	23	* Functions for accessing PCI configuration space with type 1 accesses
	24	*/
	25	static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
	26	int where, int size, u32 *val)
	27	{
b6706ef1	28	struct pci_channel *chan = bus->sysdata;
959f85f8 PM	29	unsigned long flags;
	30	u32 data;
	31
	32	/*
	33	* PCIPDR may only be accessed as 32 bit words,
	34	* so we must do byte alignment by hand
	35	*/
39a90865	36	raw_spin_lock_irqsave(&pci_config_lock, flags);
b6706ef1 MD	37	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
b6706ef1 MD	38	data = pci_read_reg(chan, SH4_PCIPDR);
39a90865	39	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
959f85f8 PM	40
	41	switch (size) {
	42	case 1:
	43	*val = (data >> ((where & 3) << 3)) & 0xff;
	44	break;
	45	case 2:
	46	*val = (data >> ((where & 2) << 3)) & 0xffff;
	47	break;
	48	case 4:
	49	*val = data;
	50	break;
	51	default:
	52	return PCIBIOS_FUNC_NOT_SUPPORTED;
	53	}
	54
	55	return PCIBIOS_SUCCESSFUL;
	56	}
	57
	58	/*
	59	* Since SH4 only does 32bit access we'll have to do a read,
	60	* mask,write operation.
	61	* We'll allow an odd byte offset, though it should be illegal.
	62	*/
	63	static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
	64	int where, int size, u32 val)
	65	{
b6706ef1	66	struct pci_channel *chan = bus->sysdata;
959f85f8 PM	67	unsigned long flags;
	68	int shift;
	69	u32 data;
	70
39a90865	71	raw_spin_lock_irqsave(&pci_config_lock, flags);
b6706ef1 MD	72	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
b6706ef1 MD	73	data = pci_read_reg(chan, SH4_PCIPDR);
39a90865	74	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
959f85f8 PM	75
	76	switch (size) {
	77	case 1:
	78	shift = (where & 3) << 3;
	79	data &= ~(0xff << shift);
	80	data \|= ((val & 0xff) << shift);
	81	break;
	82	case 2:
	83	shift = (where & 2) << 3;
	84	data &= ~(0xffff << shift);
	85	data \|= ((val & 0xffff) << shift);
	86	break;
	87	case 4:
	88	data = val;
	89	break;
	90	default:
	91	return PCIBIOS_FUNC_NOT_SUPPORTED;
	92	}
	93
b6706ef1	94	pci_write_reg(chan, data, SH4_PCIPDR);
959f85f8 PM	95
	96	return PCIBIOS_SUCCESSFUL;
	97	}
	98
	99	struct pci_ops sh4_pci_ops = {
	100	.read = sh4_pci_read,
	101	.write = sh4_pci_write,
	102	};
	103
b8b47bfb	104	int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
cd6c7ea2 PM	105	{
	106	/* Nothing to do. */
	107	return 0;
	108	}