[deliverable/linux.git] / arch / sh / drivers / pci / pci-sh7780.h

/*
 *	Low-Level PCI Support for SH7780 targets
 *
 *  Dustin McIntire (dustin@sensoria.com) (c) 2001
 *  Paul Mundt (lethal@linux-sh.org) (c) 2003
 *
 *  May be copied or modified under the terms of the GNU General Public
 *  License.  See linux/COPYING for more information.
 *
 */

#ifndef _PCI_SH7780_H_
#define _PCI_SH7780_H_

/* Platform Specific Values */
#define SH7780_VENDOR_ID	0x1912
#define SH7781_DEVICE_ID	0x0001
#define SH7780_DEVICE_ID	0x0002
#define SH7763_DEVICE_ID	0x0004
#define SH7785_DEVICE_ID	0x0007

/* SH7780 Control Registers */
#define	SH7780_PCI_VCR0		0xFE000000
#define	SH7780_PCI_VCR1		0xFE000004
#define	SH7780_PCI_VCR2		0xFE000008

/* SH7780 Specific Values */
#define SH7780_PCI_CONFIG_BASE	0xFD000000	/* Config space base addr */
#define SH7780_PCI_CONFIG_SIZE	0x01000000	/* Config space size */

#define SH7780_PCI_MEMORY_BASE	0xFD000000	/* Memory space base addr */
#define SH7780_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */

#define SH7780_PCI_IO_BASE	0xFE200000	/* IO space base address */
#define SH7780_PCI_IO_SIZE	0x00400000	/* Size of IO window */

#define SH7780_PCIREG_BASE	0xFE040000	/* PCI regs base address */
#define PCI_REG(n)		(SH7780_PCIREG_BASE+n)

/* SH7780 PCI Config Registers */
#define SH7780_PCIVID		0x000		/* Vendor ID */
#define SH7780_PCIDID		0x002		/* Device ID */
#define SH7780_PCICMD		0x004		/* Command */
#define SH7780_PCISTATUS	0x006		/* Status */
#define SH7780_PCIRID		0x008		/* Revision ID */
#define SH7780_PCIPIF		0x009		/* Program Interface */
#define SH7780_PCISUB		0x00a		/* Sub class code */
#define SH7780_PCIBCC		0x00b		/* Base class code */
#define SH7780_PCICLS		0x00c		/* Cache line size */
#define SH7780_PCILTM		0x00d		/* latency timer */
#define SH7780_PCIHDR		0x00e		/* Header type */
#define SH7780_PCIBIST		0x00f		/* BIST */
#define SH7780_PCIIBAR		0x010		/* IO Base address */
#define SH7780_PCIMBAR0		0x014		/* Memory base address0 */
#define SH7780_PCIMBAR1		0x018		/* Memory base address1 */
#define SH7780_PCISVID		0x02c		/* Sub system vendor ID */
#define SH7780_PCISID		0x02e		/* Sub system ID */
#define SH7780_PCICP		0x034
#define SH7780_PCIINTLINE	0x03c		/* Interrupt line */
#define SH7780_PCIINTPIN	0x03d		/* Interrupt pin */
#define SH7780_PCIMINGNT	0x03e		/* Minumum grand */
#define SH7780_PCIMAXLAT	0x03f		/* Maxmum latency */
#define SH7780_PCICID		0x040
#define SH7780_PCINIP		0x041
#define SH7780_PCIPMC		0x042
#define SH7780_PCIPMCSR		0x044
#define SH7780_PCIPMCSR_BSE	0x046
#define SH7780_PCICDD		0x047

#define SH7780_PCICR		0x100		/* PCI Control Register */
#define SH7780_PCILSR		0x104		/* PCI Local Space Register0 */
#define SH7780_PCILSR1		0x108		/* PCI Local Space Register1 */
#define SH7780_PCILAR0		0x10C		/* PCI Local Address Register1 */
#define SH7780_PCILAR1		0x110		/* PCI Local Address Register1 */
#define SH7780_PCIIR		0x114		/* PCI Interrupt Register */
#define SH7780_PCIIMR		0x118		/* PCI Interrupt Mask Register */
#define SH7780_PCIAIR		0x11C		/* Error Address Register */
#define SH7780_PCICIR		0x120		/* Error Command/Data Register */
#define SH7780_PCIAINT		0x130		/* Arbiter Interrupt Register */
#define SH7780_PCIAINTM		0x134		/* Arbiter Int. Mask Register */
#define SH7780_PCIBMIR		0x138		/* Error Bus Master Register */
#define SH7780_PCIPAR		0x1C0		/* PIO Address Register */
#define SH7780_PCIPINT		0x1CC		/* Power Mgmnt Int. Register */
#define SH7780_PCIPINTM		0x1D0		/* Power Mgmnt Mask Register */

#define SH7780_PCIMBR0		0x1E0
#define SH7780_PCIMBMR0		0x1E4
#define SH7780_PCIMBR2		0x1F0
#define SH7780_PCIMBMR2		0x1F4
#define SH7780_PCIIOBR		0x1F8
#define SH7780_PCIIOBMR		0x1FC
#define SH7780_PCICSCR0		0x210		/* Cache Snoop1 Cnt. Register */
#define SH7780_PCICSCR1		0x214		/* Cache Snoop2 Cnt. Register */
#define SH7780_PCICSAR0		0x218	/* Cache Snoop1 Addr. Register */
#define SH7780_PCICSAR1		0x21C	/* Cache Snoop2 Addr. Register */

/* General Memory Config Addresses */
#define SH7780_CS0_BASE_ADDR	0x0
#define SH7780_MEM_REGION_SIZE	0x04000000
#define SH7780_CS1_BASE_ADDR	(SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS2_BASE_ADDR	(SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS3_BASE_ADDR	(SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS4_BASE_ADDR	(SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS5_BASE_ADDR	(SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS6_BASE_ADDR	(SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)

struct sh4_pci_address_map;

/* arch/sh/drivers/pci/pci-sh7780.c */
int sh7780_pcic_init(struct sh4_pci_address_map *map);

#endif /* _PCI_SH7780_H_ */
Commit	Line	Data
5283ecb5 PM	1	/*
	2	* Low-Level PCI Support for SH7780 targets
	3	*
	4	* Dustin McIntire (dustin@sensoria.com) (c) 2001
	5	* Paul Mundt (lethal@linux-sh.org) (c) 2003
	6	*
	7	* May be copied or modified under the terms of the GNU General Public
	8	* License. See linux/COPYING for more information.
	9	*
	10	*/
	11
	12	#ifndef _PCI_SH7780_H_
	13	#define _PCI_SH7780_H_
	14
5283ecb5 PM	15	/* Platform Specific Values */
5283ecb5 PM	16	#define SH7780_VENDOR_ID 0x1912
5283ecb5	17	#define SH7781_DEVICE_ID 0x0001
32351a28	18	#define SH7780_DEVICE_ID 0x0002
7d740a06	19	#define SH7763_DEVICE_ID 0x0004
32351a28	20	#define SH7785_DEVICE_ID 0x0007
5283ecb5 PM	21
	22	/* SH7780 Control Registers */
	23	#define SH7780_PCI_VCR0 0xFE000000
	24	#define SH7780_PCI_VCR1 0xFE000004
	25	#define SH7780_PCI_VCR2 0xFE000008
	26
	27	/* SH7780 Specific Values */
	28	#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
	29	#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
959f85f8	30
5283ecb5 PM	31	#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
5283ecb5 PM	32	#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
959f85f8	33
78ffeec4	34	#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
5283ecb5	35	#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
5283ecb5 PM	36
	37	#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
	38	#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
	39
	40	/* SH7780 PCI Config Registers */
	41	#define SH7780_PCIVID 0x000 /* Vendor ID */
	42	#define SH7780_PCIDID 0x002 /* Device ID */
	43	#define SH7780_PCICMD 0x004 /* Command */
	44	#define SH7780_PCISTATUS 0x006 /* Status */
	45	#define SH7780_PCIRID 0x008 /* Revision ID */
	46	#define SH7780_PCIPIF 0x009 /* Program Interface */
	47	#define SH7780_PCISUB 0x00a /* Sub class code */
	48	#define SH7780_PCIBCC 0x00b /* Base class code */
	49	#define SH7780_PCICLS 0x00c /* Cache line size */
	50	#define SH7780_PCILTM 0x00d /* latency timer */
	51	#define SH7780_PCIHDR 0x00e /* Header type */
	52	#define SH7780_PCIBIST 0x00f /* BIST */
	53	#define SH7780_PCIIBAR 0x010 /* IO Base address */
	54	#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
	55	#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
	56	#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
	57	#define SH7780_PCISID 0x02e /* Sub system ID */
	58	#define SH7780_PCICP 0x034
	59	#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
	60	#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
	61	#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
	62	#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
	63	#define SH7780_PCICID 0x040
	64	#define SH7780_PCINIP 0x041
	65	#define SH7780_PCIPMC 0x042
	66	#define SH7780_PCIPMCSR 0x044
	67	#define SH7780_PCIPMCSR_BSE 0x046
	68	#define SH7780_PCICDD 0x047
	69
b7576230 NI	70	#define SH7780_PCICR 0x100 /* PCI Control Register */
	71	#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
	72	#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
	73	#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
	74	#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
	75	#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
	76	#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
	77	#define SH7780_PCIAIR 0x11C /* Error Address Register */
	78	#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
	79	#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
	80	#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
	81	#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
	82	#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
	83	#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
	84	#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
	85
959f85f8 PM	86	#define SH7780_PCIMBR0 0x1E0
	87	#define SH7780_PCIMBMR0 0x1E4
	88	#define SH7780_PCIMBR2 0x1F0
	89	#define SH7780_PCIMBMR2 0x1F4
	90	#define SH7780_PCIIOBR 0x1F8
	91	#define SH7780_PCIIOBMR 0x1FC
5283ecb5 PM	92	#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
	93	#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
	94	#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
	95	#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
5283ecb5 PM	96
	97	/* General Memory Config Addresses */
	98	#define SH7780_CS0_BASE_ADDR 0x0
	99	#define SH7780_MEM_REGION_SIZE 0x04000000
	100	#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	101	#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	102	#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	103	#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	104	#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	105	#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
	106
959f85f8	107	struct sh4_pci_address_map;
5283ecb5 PM	108
5283ecb5 PM	109	/* arch/sh/drivers/pci/pci-sh7780.c */
959f85f8	110	int sh7780_pcic_init(struct sh4_pci_address_map *map);
5283ecb5 PM	111
5283ecb5 PM	112	#endif /* _PCI_SH7780_H_ */