[deliverable/linux.git] / arch / sh / drivers / pci / pci.c

/*
 * New-style PCI core.
 *
 * Copyright (c) 2004 - 2009  Paul Mundt
 * Copyright (c) 2002  M. R. Brown
 *
 * Modelled after arch/mips/pci/pci.c:
 *  Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/dma-debug.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/export.h>

unsigned long PCIBIOS_MIN_IO = 0x0000;
unsigned long PCIBIOS_MIN_MEM = 0;

/*
 * The PCI controller list.
 */
static struct pci_channel *hose_head, **hose_tail = &hose_head;

static int pci_initialized;

static void __devinit pcibios_scanbus(struct pci_channel *hose)
{
	static int next_busno;
	static int need_domain_info;
	struct pci_bus *bus;

	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->subordinate + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		pci_bus_size_bridges(bus);
		pci_bus_assign_resources(bus);
		pci_enable_bridges(bus);
	}
}

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */
DEFINE_RAW_SPINLOCK(pci_config_lock);
static DEFINE_MUTEX(pci_scan_mutex);

int __devinit register_pci_controller(struct pci_channel *hose)
{
	int i;

	for (i = 0; i < hose->nr_resources; i++) {
		struct resource *res = hose->resources + i;

		if (res->flags & IORESOURCE_IO) {
			if (request_resource(&ioport_resource, res) < 0)
				goto out;
		} else {
			if (request_resource(&iomem_resource, res) < 0)
				goto out;
		}
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might happen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Setup the ERR/PERR and SERR timers, if available.
	 */
	pcibios_enable_timers(hose);

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return 0;

out:
	for (--i; i >= 0; i--)
		release_resource(&hose->resources[i]);

	printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
	return -1;
}

static int __init pcibios_init(void)
{
	struct pci_channel *hose;

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);

	dma_debug_add_bus(&pci_bus_type);

	pci_initialized = 1;

	return 0;
}
subsys_initcall(pcibios_init);

static void pcibios_fixup_device_resources(struct pci_dev *dev,
	struct pci_bus *bus)
{
	/* Update device resources.  */
	struct pci_channel *hose = bus->sysdata;
	unsigned long offset = 0;
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!dev->resource[i].start)
			continue;
		if (dev->resource[i].flags & IORESOURCE_IO)
			offset = hose->io_offset;
		else if (dev->resource[i].flags & IORESOURCE_MEM)
			offset = hose->mem_offset;

		dev->resource[i].start += offset;
		dev->resource[i].end += offset;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;
	struct list_head *ln;
	struct pci_channel *hose = bus->sysdata;

	if (!dev) {
		int i;

		for (i = 0; i < hose->nr_resources; i++)
			bus->resource[i] = hose->resources + i;
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		dev = pci_dev_b(ln);

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
				resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_channel *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
			start = PCIBIOS_MIN_IO + hose->resources[0].start;

		/*
                 * Put everything into 0x00-0xff region modulo 0x400.
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}

	return start;
}

void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			     struct resource *res)
{
	struct pci_channel *hose = dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	region->start = res->start - offset;
	region->end = res->end - offset;
}

void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			     struct pci_bus_region *region)
{
	struct pci_channel *hose = dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	res->start = region->start + offset;
	res->end = region->end + offset;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	return pci_enable_resources(dev, mask);
}

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

char * __devinit __weak pcibios_setup(char *str)
{
	return str;
}

static void __init
pcibios_bus_report_status_early(struct pci_channel *hose,
				int top_bus, int current_bus,
				unsigned int status_mask, int warn)
{
	unsigned int pci_devfn;
	u16 status;
	int ret;

	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
		if (PCI_FUNC(pci_devfn))
			continue;
		ret = early_read_config_word(hose, top_bus, current_bus,
					     pci_devfn, PCI_STATUS, &status);
		if (ret != PCIBIOS_SUCCESSFUL)
			continue;
		if (status == 0xffff)
			continue;

		early_write_config_word(hose, top_bus, current_bus,
					pci_devfn, PCI_STATUS,
					status & status_mask);
		if (warn)
			printk("(%02x:%02x: %04X) ", current_bus,
			       pci_devfn, status);
	}
}

/*
 * We can't use pci_find_device() here since we are
 * called from interrupt context.
 */
static void __init_refok
pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
			  int warn)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		/*
		 * ignore host bridge - we handle
		 * that separately
		 */
		if (dev->bus->number == 0 && dev->devfn == 0)
			continue;

		pci_read_config_word(dev, PCI_STATUS, &status);
		if (status == 0xffff)
			continue;

		if ((status & status_mask) == 0)
			continue;

		/* clear the status errors */
		pci_write_config_word(dev, PCI_STATUS, status & status_mask);

		if (warn)
			printk("(%s: %04X) ", pci_name(dev), status);
	}

	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->subordinate)
			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}

void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
{
	struct pci_channel *hose;

	for (hose = hose_head; hose; hose = hose->next) {
		if (unlikely(!hose->bus))
			pcibios_bus_report_status_early(hose, hose_head->index,
					hose->index, status_mask, warn);
		else
			pcibios_bus_report_status(hose->bus, status_mask, warn);
	}
}

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot);
}

#ifndef CONFIG_GENERIC_IOMAP

static void __iomem *ioport_map_pci(struct pci_dev *dev,
				    unsigned long port, unsigned int nr)
{
	struct pci_channel *chan = dev->sysdata;

	if (unlikely(!chan->io_map_base)) {
		chan->io_map_base = sh_io_port_base;

		if (pci_domains_supported)
			panic("To avoid data corruption io_map_base MUST be "
			      "set with multiple PCI domains.");
	}

	return (void __iomem *)(chan->io_map_base + port);
}

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
	resource_size_t start = pci_resource_start(dev, bar);
	resource_size_t len = pci_resource_len(dev, bar);
	unsigned long flags = pci_resource_flags(dev, bar);

	if (unlikely(!len || !start))
		return NULL;
	if (maxlen && len > maxlen)
		len = maxlen;

	if (flags & IORESOURCE_IO)
		return ioport_map_pci(dev, start, len);
	if (flags & IORESOURCE_MEM) {
		if (flags & IORESOURCE_CACHEABLE)
			return ioremap(start, len);
		return ioremap_nocache(start, len);
	}

	return NULL;
}
EXPORT_SYMBOL(pci_iomap);

void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
{
	iounmap(addr);
}
EXPORT_SYMBOL(pci_iounmap);

#endif /* CONFIG_GENERIC_IOMAP */

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
#endif
Commit	Line	Data
4c5107e4 PM	1	/*
	2	* New-style PCI core.
	3	*
4c5107e4	4	* Copyright (c) 2004 - 2009 Paul Mundt
35bcfffd PM	5	* Copyright (c) 2002 M. R. Brown
	6	*
	7	* Modelled after arch/mips/pci/pci.c:
	8	* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
4c5107e4 PM	9	*
	10	* This file is subject to the terms and conditions of the GNU General Public
	11	* License. See the file "COPYING" in the main directory of this archive
	12	* for more details.
	13	*/
	14	#include <linux/kernel.h>
35bcfffd	15	#include <linux/mm.h>
4c5107e4 PM	16	#include <linux/pci.h>
4c5107e4 PM	17	#include <linux/init.h>
35bcfffd	18	#include <linux/types.h>
4c5107e4 PM	19	#include <linux/dma-debug.h>
4c5107e4 PM	20	#include <linux/io.h>
e79066a6	21	#include <linux/mutex.h>
39a90865	22	#include <linux/spinlock.h>
f7be3455	23	#include <linux/export.h>
4c5107e4	24
35bcfffd PM	25	unsigned long PCIBIOS_MIN_IO = 0x0000;
	26	unsigned long PCIBIOS_MIN_MEM = 0;
	27
e79066a6 PM	28	/*
	29	* The PCI controller list.
	30	*/
	31	static struct pci_channel hose_head, *hose_tail = &hose_head;
	32
	33	static int pci_initialized;
	34
	35	static void __devinit pcibios_scanbus(struct pci_channel *hose)
4c5107e4	36	{
e79066a6	37	static int next_busno;
320e68da	38	static int need_domain_info;
4c5107e4	39	struct pci_bus *bus;
e79066a6	40
e79066a6	41	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
320e68da PM	42	hose->bus = bus;
	43
	44	need_domain_info = need_domain_info \|\| hose->index;
	45	hose->need_domain_info = need_domain_info;
e79066a6 PM	46	if (bus) {
	47	next_busno = bus->subordinate + 1;
	48	/* Don't allow 8-bit bus number overflow inside the hose -
	49	reserve some space for bridges. */
320e68da	50	if (next_busno > 224) {
e79066a6	51	next_busno = 0;
320e68da PM	52	need_domain_info = 1;
320e68da PM	53	}
e79066a6 PM	54
	55	pci_bus_size_bridges(bus);
	56	pci_bus_assign_resources(bus);
	57	pci_enable_bridges(bus);
4c5107e4	58	}
e79066a6	59	}
4c5107e4	60
39a90865 PM	61	/*
	62	* This interrupt-safe spinlock protects all accesses to PCI
	63	* configuration space.
	64	*/
	65	DEFINE_RAW_SPINLOCK(pci_config_lock);
e79066a6	66	static DEFINE_MUTEX(pci_scan_mutex);
4c5107e4	67
bcf39352	68	int __devinit register_pci_controller(struct pci_channel *hose)
e79066a6	69	{
b6c58b1d PM	70	int i;
	71
	72	for (i = 0; i < hose->nr_resources; i++) {
	73	struct resource *res = hose->resources + i;
	74
	75	if (res->flags & IORESOURCE_IO) {
	76	if (request_resource(&ioport_resource, res) < 0)
	77	goto out;
	78	} else {
	79	if (request_resource(&iomem_resource, res) < 0)
	80	goto out;
	81	}
ac8ab54a	82	}
e79066a6 PM	83
	84	*hose_tail = hose;
	85	hose_tail = &hose->next;
	86
	87	/*
25985edc	88	* Do not panic here but later - this might happen before console init.
e79066a6 PM	89	*/
	90	if (!hose->io_map_base) {
	91	printk(KERN_WARNING
	92	"registering PCI controller with io_map_base unset\n");
	93	}
	94
ef407bee PM	95	/*
	96	* Setup the ERR/PERR and SERR timers, if available.
	97	*/
	98	pcibios_enable_timers(hose);
	99
e79066a6 PM	100	/*
	101	* Scan the bus if it is register after the PCI subsystem
	102	* initialization.
	103	*/
	104	if (pci_initialized) {
	105	mutex_lock(&pci_scan_mutex);
	106	pcibios_scanbus(hose);
	107	mutex_unlock(&pci_scan_mutex);
4c5107e4	108	}
ac8ab54a	109
bcf39352	110	return 0;
85b59f5b	111
ac8ab54a	112	out:
b6c58b1d PM	113	for (--i; i >= 0; i--)
	114	release_resource(&hose->resources[i]);
	115
ac8ab54a	116	printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
bcf39352	117	return -1;
e79066a6 PM	118	}
	119
	120	static int __init pcibios_init(void)
	121	{
	122	struct pci_channel *hose;
	123
	124	/* Scan all of the recorded PCI controllers. */
	125	for (hose = hose_head; hose; hose = hose->next)
	126	pcibios_scanbus(hose);
	127
4c5107e4 PM	128	pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
	129
	130	dma_debug_add_bus(&pci_bus_type);
	131
e79066a6 PM	132	pci_initialized = 1;
e79066a6 PM	133
4c5107e4 PM	134	return 0;
	135	}
	136	subsys_initcall(pcibios_init);
	137
	138	static void pcibios_fixup_device_resources(struct pci_dev *dev,
	139	struct pci_bus *bus)
	140	{
	141	/* Update device resources. */
09cfeb13	142	struct pci_channel *hose = bus->sysdata;
4c5107e4 PM	143	unsigned long offset = 0;
	144	int i;
	145
	146	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	147	if (!dev->resource[i].start)
	148	continue;
4c5107e4	149	if (dev->resource[i].flags & IORESOURCE_IO)
09cfeb13	150	offset = hose->io_offset;
4c5107e4	151	else if (dev->resource[i].flags & IORESOURCE_MEM)
09cfeb13	152	offset = hose->mem_offset;
4c5107e4 PM	153
	154	dev->resource[i].start += offset;
	155	dev->resource[i].end += offset;
	156	}
	157	}
	158
4c5107e4 PM	159	/*
	160	* Called after each bus is probed, but before its children
	161	* are examined.
	162	*/
35bcfffd	163	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
4c5107e4 PM	164	{
	165	struct pci_dev *dev = bus->self;
	166	struct list_head *ln;
b6c58b1d	167	struct pci_channel *hose = bus->sysdata;
4c5107e4 PM	168
4c5107e4 PM	169	if (!dev) {
b6c58b1d PM	170	int i;
	171
	172	for (i = 0; i < hose->nr_resources; i++)
	173	bus->resource[i] = hose->resources + i;
4c5107e4 PM	174	}
	175
	176	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
	177	dev = pci_dev_b(ln);
	178
	179	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	180	pcibios_fixup_device_resources(dev, bus);
	181	}
	182	}
35bcfffd PM	183
	184	/*
	185	* We need to avoid collisions with `mirrored' VGA ports
	186	* and other strange ISA hardware, so we always want the
	187	* addresses to be allocated in the 0x000-0x0ff region
	188	* modulo 0x400.
	189	*/
3b7a17fc	190	resource_size_t pcibios_align_resource(void data, const struct resource res,
b26b2d49	191	resource_size_t size, resource_size_t align)
35bcfffd PM	192	{
35bcfffd PM	193	struct pci_dev *dev = data;
b6c58b1d	194	struct pci_channel *hose = dev->sysdata;
35bcfffd PM	195	resource_size_t start = res->start;
	196
	197	if (res->flags & IORESOURCE_IO) {
b6c58b1d PM	198	if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
b6c58b1d PM	199	start = PCIBIOS_MIN_IO + hose->resources[0].start;
35bcfffd PM	200
	201	/*
	202	* Put everything into 0x00-0xff region modulo 0x400.
	203	*/
84959359	204	if (start & 0x300)
35bcfffd	205	start = (start + 0x3ff) & ~0x3ff;
35bcfffd PM	206	}
35bcfffd PM	207
b26b2d49	208	return start;
35bcfffd PM	209	}
	210
	211	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
9ad62ec4	212	struct resource *res)
35bcfffd PM	213	{
	214	struct pci_channel *hose = dev->sysdata;
	215	unsigned long offset = 0;
	216
	217	if (res->flags & IORESOURCE_IO)
	218	offset = hose->io_offset;
	219	else if (res->flags & IORESOURCE_MEM)
	220	offset = hose->mem_offset;
	221
	222	region->start = res->start - offset;
	223	region->end = res->end - offset;
	224	}
	225
9ad62ec4 PM	226	void pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
9ad62ec4 PM	227	struct pci_bus_region *region)
35bcfffd PM	228	{
	229	struct pci_channel *hose = dev->sysdata;
	230	unsigned long offset = 0;
	231
	232	if (res->flags & IORESOURCE_IO)
	233	offset = hose->io_offset;
	234	else if (res->flags & IORESOURCE_MEM)
	235	offset = hose->mem_offset;
	236
	237	res->start = region->start + offset;
	238	res->end = region->end + offset;
	239	}
	240
	241	int pcibios_enable_device(struct pci_dev *dev, int mask)
	242	{
c62e3fae	243	return pci_enable_resources(dev, mask);
35bcfffd PM	244	}
35bcfffd PM	245
35bcfffd PM	246	void pcibios_set_master(struct pci_dev *dev)
	247	{
	248	u8 lat;
	249	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	250	if (lat < 16)
	251	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	252	else if (lat > pcibios_max_latency)
	253	lat = pcibios_max_latency;
	254	else
	255	return;
	256	printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
	257	pci_name(dev), lat);
	258	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	259	}
	260
	261	void __init pcibios_update_irq(struct pci_dev *dev, int irq)
	262	{
	263	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	264	}
	265
61a46766	266	char * __devinit __weak pcibios_setup(char *str)
35bcfffd PM	267	{
	268	return str;
	269	}
	270
9ad62ec4 PM	271	static void __init
	272	pcibios_bus_report_status_early(struct pci_channel *hose,
	273	int top_bus, int current_bus,
	274	unsigned int status_mask, int warn)
	275	{
	276	unsigned int pci_devfn;
	277	u16 status;
	278	int ret;
	279
	280	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
	281	if (PCI_FUNC(pci_devfn))
	282	continue;
	283	ret = early_read_config_word(hose, top_bus, current_bus,
	284	pci_devfn, PCI_STATUS, &status);
	285	if (ret != PCIBIOS_SUCCESSFUL)
	286	continue;
	287	if (status == 0xffff)
	288	continue;
	289
	290	early_write_config_word(hose, top_bus, current_bus,
	291	pci_devfn, PCI_STATUS,
	292	status & status_mask);
	293	if (warn)
	294	printk("(%02x:%02x: %04X) ", current_bus,
	295	pci_devfn, status);
	296	}
	297	}
	298
ef407bee PM	299	/*
	300	* We can't use pci_find_device() here since we are
	301	* called from interrupt context.
	302	*/
9ad62ec4 PM	303	static void __init_refok
	304	pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
	305	int warn)
ef407bee PM	306	{
	307	struct pci_dev *dev;
	308
	309	list_for_each_entry(dev, &bus->devices, bus_list) {
	310	u16 status;
	311
	312	/*
	313	* ignore host bridge - we handle
	314	* that separately
	315	*/
	316	if (dev->bus->number == 0 && dev->devfn == 0)
	317	continue;
	318
	319	pci_read_config_word(dev, PCI_STATUS, &status);
	320	if (status == 0xffff)
	321	continue;
	322
	323	if ((status & status_mask) == 0)
	324	continue;
	325
	326	/* clear the status errors */
	327	pci_write_config_word(dev, PCI_STATUS, status & status_mask);
	328
	329	if (warn)
	330	printk("(%s: %04X) ", pci_name(dev), status);
	331	}
	332
	333	list_for_each_entry(dev, &bus->devices, bus_list)
	334	if (dev->subordinate)
	335	pcibios_bus_report_status(dev->subordinate, status_mask, warn);
	336	}
	337
9ad62ec4	338	void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
ef407bee PM	339	{
	340	struct pci_channel *hose;
	341
9ad62ec4 PM	342	for (hose = hose_head; hose; hose = hose->next) {
	343	if (unlikely(!hose->bus))
	344	pcibios_bus_report_status_early(hose, hose_head->index,
	345	hose->index, status_mask, warn);
	346	else
	347	pcibios_bus_report_status(hose->bus, status_mask, warn);
	348	}
ef407bee PM	349	}
ef407bee PM	350
35bcfffd PM	351	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	352	enum pci_mmap_state mmap_state, int write_combine)
	353	{
	354	/*
	355	* I/O space can be accessed via normal processor loads and stores on
	356	* this platform but for now we elect not to do this and portable
	357	* drivers should not do this anyway.
	358	*/
	359	if (mmap_state == pci_mmap_io)
	360	return -EINVAL;
	361
	362	/*
	363	* Ignore write-combine; for now only return uncached mappings.
	364	*/
	365	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	366
	367	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	368	vma->vm_end - vma->vm_start,
	369	vma->vm_page_prot);
	370	}
	371
15444a89 DM	372	#ifndef CONFIG_GENERIC_IOMAP
15444a89 DM	373
35bcfffd PM	374	static void __iomem ioport_map_pci(struct pci_dev dev,
	375	unsigned long port, unsigned int nr)
	376	{
	377	struct pci_channel *chan = dev->sysdata;
	378
320e68da	379	if (unlikely(!chan->io_map_base)) {
37b7a978	380	chan->io_map_base = sh_io_port_base;
35bcfffd	381
320e68da PM	382	if (pci_domains_supported)
	383	panic("To avoid data corruption io_map_base MUST be "
	384	"set with multiple PCI domains.");
	385	}
	386
35bcfffd PM	387	return (void __iomem *)(chan->io_map_base + port);
	388	}
	389
	390	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen)
	391	{
	392	resource_size_t start = pci_resource_start(dev, bar);
	393	resource_size_t len = pci_resource_len(dev, bar);
	394	unsigned long flags = pci_resource_flags(dev, bar);
	395
	396	if (unlikely(!len \|\| !start))
	397	return NULL;
	398	if (maxlen && len > maxlen)
	399	len = maxlen;
	400
	401	if (flags & IORESOURCE_IO)
	402	return ioport_map_pci(dev, start, len);
35bcfffd PM	403	if (flags & IORESOURCE_MEM) {
	404	if (flags & IORESOURCE_CACHEABLE)
	405	return ioremap(start, len);
35bcfffd PM	406	return ioremap_nocache(start, len);
	407	}
	408
	409	return NULL;
	410	}
	411	EXPORT_SYMBOL(pci_iomap);
	412
	413	void pci_iounmap(struct pci_dev dev, void __iomem addr)
	414	{
	415	iounmap(addr);
	416	}
	417	EXPORT_SYMBOL(pci_iounmap);
	418
15444a89 DM	419	#endif /* CONFIG_GENERIC_IOMAP */
15444a89 DM	420
35bcfffd PM	421	#ifdef CONFIG_HOTPLUG
	422	EXPORT_SYMBOL(pcibios_resource_to_bus);
	423	EXPORT_SYMBOL(pcibios_bus_to_resource);
	424	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
	425	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
	426	#endif