[deliverable/linux.git] / arch / sh / include / asm / dma.h

/*
 * include/asm-sh/dma.h
 *
 * Copyright (C) 2003, 2004  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef __ASM_SH_DMA_H
#define __ASM_SH_DMA_H
#ifdef __KERNEL__

#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/sysdev.h>
#include <cpu/dma.h>
#include <asm-generic/dma.h>

#ifdef CONFIG_NR_DMA_CHANNELS
#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
#else
#  define MAX_DMA_CHANNELS	0
#endif

/*
 * Read and write modes can mean drastically different things depending on the
 * channel configuration. Consult your DMAC documentation and module
 * implementation for further clues.
 */
#define DMA_MODE_READ		0x00
#define DMA_MODE_WRITE		0x01
#define DMA_MODE_MASK		0x01

#define DMA_AUTOINIT		0x10

/*
 * DMAC (dma_info) flags
 */
enum {
	DMAC_CHANNELS_CONFIGURED	= 0x01,
	DMAC_CHANNELS_TEI_CAPABLE	= 0x02,	/* Transfer end interrupt */
};

/*
 * DMA channel capabilities / flags
 */
enum {
	DMA_CONFIGURED			= 0x01,

	/*
	 * Transfer end interrupt, inherited from DMAC.
	 * wait_queue used in dma_wait_for_completion.
	 */
	DMA_TEI_CAPABLE			= 0x02,
};

extern spinlock_t dma_spin_lock;

struct dma_channel;

struct dma_ops {
	int (*request)(struct dma_channel *chan);
	void (*free)(struct dma_channel *chan);

	int (*get_residue)(struct dma_channel *chan);
	int (*xfer)(struct dma_channel *chan);
	int (*configure)(struct dma_channel *chan, unsigned long flags);
	int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
};

struct dma_channel {
	char dev_id[16];		/* unique name per DMAC of channel */

	unsigned int chan;		/* DMAC channel number */
	unsigned int vchan;		/* Virtual channel number */

	unsigned int mode;
	unsigned int count;

	unsigned long sar;
	unsigned long dar;

	const char **caps;

	unsigned long flags;
	atomic_t busy;

	wait_queue_head_t wait_queue;

	struct sys_device dev;
	void *priv_data;
};

struct dma_info {
	struct platform_device *pdev;

	const char *name;
	unsigned int nr_channels;
	unsigned long flags;

	struct dma_ops *ops;
	struct dma_channel *channels;

	struct list_head list;
	int first_channel_nr;
	int first_vchannel_nr;
};

struct dma_chan_caps {
	int ch_num;
	const char **caplist;
};

#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)

/* arch/sh/drivers/dma/dma-api.c */
extern int dma_xfer(unsigned int chan, unsigned long from,
		    unsigned long to, size_t size, unsigned int mode);

#define dma_write(chan, from, to, size)	\
	dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
#define dma_write_page(chan, from, to)	\
	dma_write(chan, from, to, PAGE_SIZE)

#define dma_read(chan, from, to, size)	\
	dma_xfer(chan, from, to, size, DMA_MODE_READ)
#define dma_read_page(chan, from, to)	\
	dma_read(chan, from, to, PAGE_SIZE)

extern int request_dma_bycap(const char **dmac, const char **caps,
			     const char *dev_id);
extern int get_dma_residue(unsigned int chan);
extern struct dma_info *get_dma_info(unsigned int chan);
extern struct dma_channel *get_dma_channel(unsigned int chan);
extern void dma_wait_for_completion(unsigned int chan);
extern void dma_configure_channel(unsigned int chan, unsigned long flags);

extern int register_dmac(struct dma_info *info);
extern void unregister_dmac(struct dma_info *info);
extern struct dma_info *get_dma_info_by_name(const char *dmac_name);

extern int dma_extend(unsigned int chan, unsigned long op, void *param);
extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);

/* arch/sh/drivers/dma/dma-sysfs.c */
extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy	(0)
#endif

#endif /* __KERNEL__ */
#endif /* __ASM_SH_DMA_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-sh/dma.h
	3	*
	4	* Copyright (C) 2003, 2004 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#ifndef __ASM_SH_DMA_H
	11	#define __ASM_SH_DMA_H
	12	#ifdef __KERNEL__
	13
1da177e4 LT	14	#include <linux/spinlock.h>
1da177e4 LT	15	#include <linux/wait.h>
66c5227e	16	#include <linux/sched.h>
1da177e4	17	#include <linux/sysdev.h>
f15cbe6f	18	#include <cpu/dma.h>
9deaa3bc	19	#include <asm-generic/dma.h>
1da177e4 LT	20
1da177e4 LT	21	#ifdef CONFIG_NR_DMA_CHANNELS
2f7bb2df PM	22	# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
	23	#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
	24	# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
1da177e4	25	#else
2f7bb2df	26	# define MAX_DMA_CHANNELS 0
1da177e4 LT	27	#endif
	28
	29	/*
	30	* Read and write modes can mean drastically different things depending on the
	31	* channel configuration. Consult your DMAC documentation and module
	32	* implementation for further clues.
	33	*/
	34	#define DMA_MODE_READ 0x00
	35	#define DMA_MODE_WRITE 0x01
	36	#define DMA_MODE_MASK 0x01
	37
	38	#define DMA_AUTOINIT 0x10
	39
	40	/*
	41	* DMAC (dma_info) flags
	42	*/
	43	enum {
db9b99d4 MG	44	DMAC_CHANNELS_CONFIGURED = 0x01,
db9b99d4 MG	45	DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
1da177e4 LT	46	};
	47
	48	/*
	49	* DMA channel capabilities / flags
	50	*/
	51	enum {
db9b99d4 MG	52	DMA_CONFIGURED = 0x01,
	53
	54	/*
	55	* Transfer end interrupt, inherited from DMAC.
	56	* wait_queue used in dma_wait_for_completion.
	57	*/
	58	DMA_TEI_CAPABLE = 0x02,
1da177e4 LT	59	};
	60
	61	extern spinlock_t dma_spin_lock;
	62
	63	struct dma_channel;
	64
	65	struct dma_ops {
	66	int (request)(struct dma_channel chan);
	67	void (free)(struct dma_channel chan);
	68
	69	int (get_residue)(struct dma_channel chan);
	70	int (xfer)(struct dma_channel chan);
db9b99d4 MG	71	int (configure)(struct dma_channel chan, unsigned long flags);
db9b99d4 MG	72	int (extend)(struct dma_channel chan, unsigned long op, void *param);
1da177e4 LT	73	};
	74
	75	struct dma_channel {
db9b99d4	76	char dev_id[16]; /* unique name per DMAC of channel */
1da177e4	77
db9b99d4	78	unsigned int chan; /* DMAC channel number */
0d831770	79	unsigned int vchan; /* Virtual channel number */
db9b99d4	80
1da177e4 LT	81	unsigned int mode;
	82	unsigned int count;
	83
	84	unsigned long sar;
	85	unsigned long dar;
	86
db9b99d4 MG	87	const char **caps;
db9b99d4 MG	88
1da177e4 LT	89	unsigned long flags;
	90	atomic_t busy;
	91
1da177e4 LT	92	wait_queue_head_t wait_queue;
	93
	94	struct sys_device dev;
db9b99d4	95	void *priv_data;
1da177e4 LT	96	};
	97
	98	struct dma_info {
0d831770 PM	99	struct platform_device *pdev;
0d831770 PM	100
1da177e4 LT	101	const char *name;
	102	unsigned int nr_channels;
	103	unsigned long flags;
	104
	105	struct dma_ops *ops;
	106	struct dma_channel *channels;
	107
	108	struct list_head list;
db9b99d4	109	int first_channel_nr;
eb695dbf	110	int first_vchannel_nr;
db9b99d4 MG	111	};
	112
	113	struct dma_chan_caps {
	114	int ch_num;
	115	const char **caplist;
1da177e4 LT	116	};
	117
	118	#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
	119
	120	/* arch/sh/drivers/dma/dma-api.c */
	121	extern int dma_xfer(unsigned int chan, unsigned long from,
	122	unsigned long to, size_t size, unsigned int mode);
	123
	124	#define dma_write(chan, from, to, size) \
	125	dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
	126	#define dma_write_page(chan, from, to) \
	127	dma_write(chan, from, to, PAGE_SIZE)
	128
	129	#define dma_read(chan, from, to, size) \
	130	dma_xfer(chan, from, to, size, DMA_MODE_READ)
	131	#define dma_read_page(chan, from, to) \
	132	dma_read(chan, from, to, PAGE_SIZE)
	133
db9b99d4 MG	134	extern int request_dma_bycap(const char dmac, const char caps,
db9b99d4 MG	135	const char *dev_id);
1da177e4 LT	136	extern int get_dma_residue(unsigned int chan);
	137	extern struct dma_info *get_dma_info(unsigned int chan);
	138	extern struct dma_channel *get_dma_channel(unsigned int chan);
	139	extern void dma_wait_for_completion(unsigned int chan);
	140	extern void dma_configure_channel(unsigned int chan, unsigned long flags);
	141
	142	extern int register_dmac(struct dma_info *info);
	143	extern void unregister_dmac(struct dma_info *info);
db9b99d4 MG	144	extern struct dma_info get_dma_info_by_name(const char dmac_name);
	145
	146	extern int dma_extend(unsigned int chan, unsigned long op, void *param);
	147	extern int register_chan_caps(const char dmac, struct dma_chan_caps capslist);
1da177e4	148
1da177e4	149	/* arch/sh/drivers/dma/dma-sysfs.c */
0d831770 PM	150	extern int dma_create_sysfs_files(struct dma_channel , struct dma_info );
0d831770 PM	151	extern void dma_remove_sysfs_files(struct dma_channel , struct dma_info );
1da177e4 LT	152
	153	#ifdef CONFIG_PCI
	154	extern int isa_dma_bridge_buggy;
	155	#else
	156	#define isa_dma_bridge_buggy (0)
	157	#endif
	158
	159	#endif /* __KERNEL__ */
	160	#endif /* __ASM_SH_DMA_H */