[deliverable/linux.git] / arch / sh / include / asm / pci.h

#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H

#ifdef __KERNEL__

/* Can be used to override the logic in pci_scan_bus for skipping
   already-configured bus numbers - to be used for buggy BIOSes
   or architectures with incomplete PCI setup by the loader */

#define pcibios_assign_all_busses()	1

/*
 * A board can define one or more PCI channels that represent built-in (or
 * external) PCI controllers.
 */
struct pci_channel {
	struct pci_channel	*next;
	struct pci_bus		*bus;

	struct pci_ops		*pci_ops;

	struct resource		*resources;
	unsigned int		nr_resources;

	unsigned long		io_offset;
	unsigned long		mem_offset;

	unsigned long		reg_base;
	unsigned long		io_map_base;

	unsigned int		index;
	unsigned int		need_domain_info;

	/* Optional error handling */
	struct timer_list	err_timer, serr_timer;
	unsigned int		err_irq, serr_irq;
};

/* arch/sh/drivers/pci/pci.c */
extern raw_spinlock_t pci_config_lock;

extern int register_pci_controller(struct pci_channel *hose);
extern void pcibios_report_status(unsigned int status_mask, int warn);

/* arch/sh/drivers/pci/common.c */
extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
				  int bus, int devfn, int offset, u8 *value);
extern int early_read_config_word(struct pci_channel *hose, int top_bus,
				  int bus, int devfn, int offset, u16 *value);
extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u32 *value);
extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u8 value);
extern int early_write_config_word(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u16 value);
extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
				    int bus, int devfn, int offset, u32 value);
extern void pcibios_enable_timers(struct pci_channel *hose);
extern unsigned int pcibios_handle_status_errors(unsigned long addr,
				 unsigned int status, struct pci_channel *hose);
extern int pci_is_66mhz_capable(struct pci_channel *hose,
				int top_bus, int current_bus);

extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;

struct pci_dev;

#define HAVE_PCI_MMAP
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
	enum pci_mmap_state mmap_state, int write_combine);
extern void pcibios_set_master(struct pci_dev *dev);

/* Dynamic DMA mapping stuff.
 * SuperH has everything mapped statically like x86.
 */

/* The PCI address space does equal the physical memory
 * address space.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS	(dma_ops->is_phys)

#ifdef CONFIG_PCI
/*
 * None of the SH PCI controllers support MWI, it is always treated as a
 * direct memory write.
 */
#define PCI_DISABLE_MWI

static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);

	if (byte == 0)
		cacheline_size = L1_CACHE_BYTES;
	else
		cacheline_size = byte << 2;

	*strat = PCI_DMA_BURST_MULTIPLE;
	*strategy_parameter = cacheline_size;
}
#endif

/* Board-specific fixup routines. */
int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);

#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index

static inline int pci_proc_domain(struct pci_bus *bus)
{
	struct pci_channel *hose = bus->sysdata;
	return hose->need_domain_info;
}

/* Chances are this interrupt is wired PC-style ...  */
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

/* generic DMA-mapping stuff */
#include <asm-generic/pci-dma-compat.h>

#endif /* __KERNEL__ */
#endif /* __ASM_SH_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_PCI_H
	2	#define __ASM_SH_PCI_H
	3
	4	#ifdef __KERNEL__
	5
1da177e4 LT	6	/* Can be used to override the logic in pci_scan_bus for skipping
	7	already-configured bus numbers - to be used for buggy BIOSes
	8	or architectures with incomplete PCI setup by the loader */
	9
	10	#define pcibios_assign_all_busses() 1
1da177e4 LT	11
	12	/*
	13	* A board can define one or more PCI channels that represent built-in (or
	14	* external) PCI controllers.
	15	*/
	16	struct pci_channel {
e79066a6	17	struct pci_channel *next;
320e68da	18	struct pci_bus *bus;
e79066a6	19
e79066a6	20	struct pci_ops *pci_ops;
b6c58b1d PM	21
	22	struct resource *resources;
	23	unsigned int nr_resources;
e79066a6	24
09cfeb13 PM	25	unsigned long io_offset;
	26	unsigned long mem_offset;
	27
e79066a6	28	unsigned long reg_base;
e79066a6	29	unsigned long io_map_base;
320e68da PM	30
	31	unsigned int index;
	32	unsigned int need_domain_info;
ef407bee PM	33
	34	/* Optional error handling */
	35	struct timer_list err_timer, serr_timer;
	36	unsigned int err_irq, serr_irq;
1da177e4 LT	37	};
1da177e4 LT	38
ef407bee	39	/* arch/sh/drivers/pci/pci.c */
39a90865 PM	40	extern raw_spinlock_t pci_config_lock;
39a90865 PM	41
bcf39352	42	extern int register_pci_controller(struct pci_channel *hose);
ef407bee PM	43	extern void pcibios_report_status(unsigned int status_mask, int warn);
	44
	45	/* arch/sh/drivers/pci/common.c */
9ad62ec4 PM	46	extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
	47	int bus, int devfn, int offset, u8 *value);
	48	extern int early_read_config_word(struct pci_channel *hose, int top_bus,
	49	int bus, int devfn, int offset, u16 *value);
	50	extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
	51	int bus, int devfn, int offset, u32 *value);
	52	extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
	53	int bus, int devfn, int offset, u8 value);
	54	extern int early_write_config_word(struct pci_channel *hose, int top_bus,
	55	int bus, int devfn, int offset, u16 value);
	56	extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
	57	int bus, int devfn, int offset, u32 value);
ef407bee PM	58	extern void pcibios_enable_timers(struct pci_channel *hose);
	59	extern unsigned int pcibios_handle_status_errors(unsigned long addr,
	60	unsigned int status, struct pci_channel *hose);
85b59f5b PM	61	extern int pci_is_66mhz_capable(struct pci_channel *hose,
85b59f5b PM	62	int top_bus, int current_bus);
e79066a6	63
a3c0e0d0	64	extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
1da177e4 LT	65
	66	struct pci_dev;
	67
98333851 PM	68	#define HAVE_PCI_MMAP
	69	extern int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	70	enum pci_mmap_state mmap_state, int write_combine);
1da177e4 LT	71	extern void pcibios_set_master(struct pci_dev *dev);
1da177e4 LT	72
1da177e4 LT	73	/* Dynamic DMA mapping stuff.
	74	* SuperH has everything mapped statically like x86.
	75	*/
	76
	77	/* The PCI address space does equal the physical memory
	78	* address space. The networking and block device layers use
	79	* this boolean for bounce buffer decisions.
	80	*/
73c926be	81	#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
1da177e4	82
3e98f9f1	83	#ifdef CONFIG_PCI
b7e2ac61 PM	84	/*
	85	* None of the SH PCI controllers support MWI, it is always treated as a
	86	* direct memory write.
	87	*/
	88	#define PCI_DISABLE_MWI
	89
e24c2d96 DM	90	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	91	enum pci_dma_burst_strategy *strat,
	92	unsigned long *strategy_parameter)
	93	{
b7e2ac61 PM	94	unsigned long cacheline_size;
	95	u8 byte;
	96
	97	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	98
	99	if (byte == 0)
	100	cacheline_size = L1_CACHE_BYTES;
	101	else
	102	cacheline_size = byte << 2;
	103
	104	*strat = PCI_DMA_BURST_MULTIPLE;
	105	*strategy_parameter = cacheline_size;
e24c2d96	106	}
3e98f9f1	107	#endif
ef339f24	108
1da177e4	109	/* Board-specific fixup routines. */
d5341942	110	int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
1da177e4	111
320e68da PM	112	#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
	113
	114	static inline int pci_proc_domain(struct pci_bus *bus)
	115	{
	116	struct pci_channel *hose = bus->sysdata;
	117	return hose->need_domain_info;
	118	}
	119
9ade1217 PM	120	/* Chances are this interrupt is wired PC-style ... */
	121	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	122	{
	123	return channel ? 15 : 14;
	124	}
1da177e4 LT	125
	126	/* generic DMA-mapping stuff */
	127	#include <asm-generic/pci-dma-compat.h>
	128
9ade1217	129	#endif /* __KERNEL__ */
1da177e4 LT	130	#endif /* __ASM_SH_PCI_H */
1da177e4 LT	131