[deliverable/linux.git] / arch / sh / include / cpu-sh4 / cpu / dma-sh4a.h

#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H

#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
	defined(CONFIG_CPU_SUBTYPE_SH7730)
#define DMTE0_IRQ	48
#define DMTE4_IRQ	76
#define DMAE0_IRQ	78	/* DMA Error IRQ*/
#define SH_DMAC_BASE0	0xFE008020
#define SH_DMARS_BASE	0xFE009000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0
#define CHCR_TS_HIGH_SHIFT	0
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
#define DMTE0_IRQ	48
#define DMTE4_IRQ	76
#define DMAE0_IRQ	78	/* DMA Error IRQ*/
#define SH_DMAC_BASE0	0xFE008020
#define SH_DMARS_BASE	0xFE009000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0x00300000
#define CHCR_TS_HIGH_SHIFT	20
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
	defined(CONFIG_CPU_SUBTYPE_SH7764)
#define DMTE0_IRQ	34
#define DMTE4_IRQ	44
#define DMAE0_IRQ	38
#define SH_DMAC_BASE0	0xFF608020
#define SH_DMARS_BASE	0xFF609000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0
#define CHCR_TS_HIGH_SHIFT	0
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define DMTE0_IRQ	48	/* DMAC0A*/
#define DMTE4_IRQ	76	/* DMAC0B */
#define DMTE6_IRQ	40
#define DMTE8_IRQ	42	/* DMAC1A */
#define DMTE9_IRQ	43
#define DMTE10_IRQ	72	/* DMAC1B */
#define DMTE11_IRQ	73
#define DMAE0_IRQ	78	/* DMA Error IRQ*/
#define DMAE1_IRQ	74	/* DMA Error IRQ*/
#define SH_DMAC_BASE0	0xFE008020
#define SH_DMAC_BASE1	0xFDC08020
#define SH_DMARS_BASE	0xFDC09000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0
#define CHCR_TS_HIGH_SHIFT	0
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
#define DMTE0_IRQ	48	/* DMAC0A*/
#define DMTE4_IRQ	76	/* DMAC0B */
#define DMTE6_IRQ	40
#define DMTE8_IRQ	42	/* DMAC1A */
#define DMTE9_IRQ	43
#define DMTE10_IRQ	72	/* DMAC1B */
#define DMTE11_IRQ	73
#define DMAE0_IRQ	78	/* DMA Error IRQ*/
#define DMAE1_IRQ	74	/* DMA Error IRQ*/
#define SH_DMAC_BASE0	0xFE008020
#define SH_DMAC_BASE1	0xFDC08020
#define SH_DMARS_BASE	0xFDC09000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0x00600000
#define CHCR_TS_HIGH_SHIFT	21
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define DMTE0_IRQ	34
#define DMTE4_IRQ	44
#define DMTE6_IRQ	46
#define DMTE8_IRQ	92
#define DMTE9_IRQ	93
#define DMTE10_IRQ	94
#define DMTE11_IRQ	95
#define DMAE0_IRQ	38	/* DMA Error IRQ */
#define SH_DMAC_BASE0	0xFC808020
#define SH_DMAC_BASE1	0xFC818020
#define SH_DMARS_BASE	0xFC809000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0
#define CHCR_TS_HIGH_SHIFT	0
#else /* SH7785 */
#define DMTE0_IRQ	33
#define DMTE4_IRQ	37
#define DMTE6_IRQ	52
#define DMTE8_IRQ	54
#define DMTE9_IRQ	55
#define DMTE10_IRQ	56
#define DMTE11_IRQ	57
#define DMAE0_IRQ	39	/* DMA Error IRQ0 */
#define DMAE1_IRQ	58	/* DMA Error IRQ1 */
#define SH_DMAC_BASE0	0xFC808020
#define SH_DMAC_BASE1	0xFCC08020
#define SH_DMARS_BASE	0xFC809000
#define CHCR_TS_LOW_MASK	0x00000018
#define CHCR_TS_LOW_SHIFT	3
#define CHCR_TS_HIGH_MASK	0
#define CHCR_TS_HIGH_SHIFT	0
#endif

#define REQ_HE		0x000000C0
#define REQ_H		0x00000080
#define REQ_LE		0x00000040
#define TM_BURST	0x00000020

/*
 * The SuperH DMAC supports a number of transmit sizes, we list them here,
 * with their respective values as they appear in the CHCR registers.
 *
 * Defaults to a 64-bit transfer size.
 */
enum {
	XMIT_SZ_8BIT		= 0,
	XMIT_SZ_16BIT		= 1,
	XMIT_SZ_32BIT		= 2,
	XMIT_SZ_64BIT		= 7,
	XMIT_SZ_128BIT		= 3,
	XMIT_SZ_256BIT		= 4,
	XMIT_SZ_128BIT_BLK	= 0xb,
	XMIT_SZ_256BIT_BLK	= 0xc,
};

/*
 * The DMA count is defined as the number of bytes to transfer.
 */
#define TS_SHIFT {			\
	[XMIT_SZ_8BIT]		= 0,	\
	[XMIT_SZ_16BIT]		= 1,	\
	[XMIT_SZ_32BIT]		= 2,	\
	[XMIT_SZ_64BIT]		= 3,	\
	[XMIT_SZ_128BIT]	= 4,	\
	[XMIT_SZ_256BIT]	= 5,	\
	[XMIT_SZ_128BIT_BLK]	= 4,	\
	[XMIT_SZ_256BIT_BLK]	= 5,	\
}

#define TS_INDEX2VAL(i)	((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
			 ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))

#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
Commit	Line	Data
71b973a4 NI	1	#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
	2	#define __ASM_SH_CPU_SH4_DMA_SH7780_H
	3
	4	#if defined(CONFIG_CPU_SUBTYPE_SH7343) \|\| \
71b973a4 NI	5	defined(CONFIG_CPU_SUBTYPE_SH7730)
	6	#define DMTE0_IRQ 48
	7	#define DMTE4_IRQ 76
	8	#define DMAE0_IRQ 78 /* DMA Error IRQ*/
	9	#define SH_DMAC_BASE0 0xFE008020
	10	#define SH_DMARS_BASE 0xFE009000
623b4ac4 GL	11	#define CHCR_TS_LOW_MASK 0x00000018
	12	#define CHCR_TS_LOW_SHIFT 3
	13	#define CHCR_TS_HIGH_MASK 0
	14	#define CHCR_TS_HIGH_SHIFT 0
	15	#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
	16	#define DMTE0_IRQ 48
	17	#define DMTE4_IRQ 76
	18	#define DMAE0_IRQ 78 /* DMA Error IRQ*/
	19	#define SH_DMAC_BASE0 0xFE008020
	20	#define SH_DMARS_BASE 0xFE009000
	21	#define CHCR_TS_LOW_MASK 0x00000018
	22	#define CHCR_TS_LOW_SHIFT 3
	23	#define CHCR_TS_HIGH_MASK 0x00300000
	24	#define CHCR_TS_HIGH_SHIFT 20
71b973a4 NI	25	#elif defined(CONFIG_CPU_SUBTYPE_SH7763) \|\| \
	26	defined(CONFIG_CPU_SUBTYPE_SH7764)
	27	#define DMTE0_IRQ 34
	28	#define DMTE4_IRQ 44
	29	#define DMAE0_IRQ 38
	30	#define SH_DMAC_BASE0 0xFF608020
	31	#define SH_DMARS_BASE 0xFF609000
623b4ac4 GL	32	#define CHCR_TS_LOW_MASK 0x00000018
	33	#define CHCR_TS_LOW_SHIFT 3
	34	#define CHCR_TS_HIGH_MASK 0
	35	#define CHCR_TS_HIGH_SHIFT 0
	36	#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
71b973a4	37	#define DMTE0_IRQ 48 /* DMAC0A*/
39b27f4c GL	38	#define DMTE4_IRQ 76 /* DMAC0B */
	39	#define DMTE6_IRQ 40
	40	#define DMTE8_IRQ 42 /* DMAC1A */
	41	#define DMTE9_IRQ 43
71b973a4 NI	42	#define DMTE10_IRQ 72 /* DMAC1B */
	43	#define DMTE11_IRQ 73
	44	#define DMAE0_IRQ 78 /* DMA Error IRQ*/
	45	#define DMAE1_IRQ 74 /* DMA Error IRQ*/
	46	#define SH_DMAC_BASE0 0xFE008020
	47	#define SH_DMAC_BASE1 0xFDC08020
	48	#define SH_DMARS_BASE 0xFDC09000
623b4ac4 GL	49	#define CHCR_TS_LOW_MASK 0x00000018
	50	#define CHCR_TS_LOW_SHIFT 3
	51	#define CHCR_TS_HIGH_MASK 0
	52	#define CHCR_TS_HIGH_SHIFT 0
	53	#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
	54	#define DMTE0_IRQ 48 /* DMAC0A*/
	55	#define DMTE4_IRQ 76 /* DMAC0B */
	56	#define DMTE6_IRQ 40
	57	#define DMTE8_IRQ 42 /* DMAC1A */
	58	#define DMTE9_IRQ 43
	59	#define DMTE10_IRQ 72 /* DMAC1B */
	60	#define DMTE11_IRQ 73
	61	#define DMAE0_IRQ 78 /* DMA Error IRQ*/
	62	#define DMAE1_IRQ 74 /* DMA Error IRQ*/
	63	#define SH_DMAC_BASE0 0xFE008020
	64	#define SH_DMAC_BASE1 0xFDC08020
	65	#define SH_DMARS_BASE 0xFDC09000
	66	#define CHCR_TS_LOW_MASK 0x00000018
	67	#define CHCR_TS_LOW_SHIFT 3
	68	#define CHCR_TS_HIGH_MASK 0x00600000
	69	#define CHCR_TS_HIGH_SHIFT 21
71b973a4 NI	70	#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
	71	#define DMTE0_IRQ 34
	72	#define DMTE4_IRQ 44
	73	#define DMTE6_IRQ 46
	74	#define DMTE8_IRQ 92
	75	#define DMTE9_IRQ 93
	76	#define DMTE10_IRQ 94
	77	#define DMTE11_IRQ 95
	78	#define DMAE0_IRQ 38 /* DMA Error IRQ */
	79	#define SH_DMAC_BASE0 0xFC808020
	80	#define SH_DMAC_BASE1 0xFC818020
	81	#define SH_DMARS_BASE 0xFC809000
623b4ac4 GL	82	#define CHCR_TS_LOW_MASK 0x00000018
	83	#define CHCR_TS_LOW_SHIFT 3
	84	#define CHCR_TS_HIGH_MASK 0
	85	#define CHCR_TS_HIGH_SHIFT 0
71b973a4 NI	86	#else /* SH7785 */
	87	#define DMTE0_IRQ 33
	88	#define DMTE4_IRQ 37
	89	#define DMTE6_IRQ 52
	90	#define DMTE8_IRQ 54
	91	#define DMTE9_IRQ 55
	92	#define DMTE10_IRQ 56
	93	#define DMTE11_IRQ 57
	94	#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
	95	#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
	96	#define SH_DMAC_BASE0 0xFC808020
	97	#define SH_DMAC_BASE1 0xFCC08020
	98	#define SH_DMARS_BASE 0xFC809000
623b4ac4 GL	99	#define CHCR_TS_LOW_MASK 0x00000018
	100	#define CHCR_TS_LOW_SHIFT 3
	101	#define CHCR_TS_HIGH_MASK 0
	102	#define CHCR_TS_HIGH_SHIFT 0
71b973a4 NI	103	#endif
71b973a4 NI	104
623b4ac4 GL	105	#define REQ_HE 0x000000C0
	106	#define REQ_H 0x00000080
	107	#define REQ_LE 0x00000040
	108	#define TM_BURST 0x00000020
71b973a4 NI	109
	110	/*
	111	* The SuperH DMAC supports a number of transmit sizes, we list them here,
	112	* with their respective values as they appear in the CHCR registers.
	113	*
	114	* Defaults to a 64-bit transfer size.
	115	*/
	116	enum {
623b4ac4 GL	117	XMIT_SZ_8BIT = 0,
	118	XMIT_SZ_16BIT = 1,
	119	XMIT_SZ_32BIT = 2,
	120	XMIT_SZ_64BIT = 7,
	121	XMIT_SZ_128BIT = 3,
	122	XMIT_SZ_256BIT = 4,
	123	XMIT_SZ_128BIT_BLK = 0xb,
	124	XMIT_SZ_256BIT_BLK = 0xc,
71b973a4 NI	125	};
	126
	127	/*
	128	* The DMA count is defined as the number of bytes to transfer.
	129	*/
623b4ac4 GL	130	#define TS_SHIFT { \
	131	[XMIT_SZ_8BIT] = 0, \
	132	[XMIT_SZ_16BIT] = 1, \
	133	[XMIT_SZ_32BIT] = 2, \
	134	[XMIT_SZ_64BIT] = 3, \
	135	[XMIT_SZ_128BIT] = 4, \
	136	[XMIT_SZ_256BIT] = 5, \
	137	[XMIT_SZ_128BIT_BLK] = 4, \
	138	[XMIT_SZ_256BIT_BLK] = 5, \
	139	}
	140
	141	#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) \| \
	142	((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
71b973a4 NI	143
71b973a4 NI	144	#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */