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1 | #ifndef __ASM_SH_CPU_FEATURES_H |
2 | #define __ASM_SH_CPU_FEATURES_H | |
3 | ||
4 | /* | |
5 | * Processor flags | |
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6 | * |
7 | * Note: When adding a new flag, keep cpu_flags[] in | |
8 | * arch/sh/kernel/setup.c in sync so symbolic name | |
9 | * mapping of the processor flags has a chance of being | |
10 | * reasonably accurate. | |
11 | * | |
12 | * These flags are also available through the ELF | |
13 | * auxiliary vector as AT_HWCAP. | |
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14 | */ |
15 | #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ | |
16 | #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ | |
17 | #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ | |
18 | #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ | |
19 | #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ | |
20 | #define CPU_HAS_PTEA 0x0020 /* PTEA register */ | |
21 | #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ | |
72c35543 | 22 | #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ |
074f98df | 23 | #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ |
8263a67e | 24 | #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ |
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25 | |
26 | #endif /* __ASM_SH_CPU_FEATURES_H */ |