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1da177e4 | 1 | /* |
a23ba435 | 2 | * arch/sh/kernel/cpu/irq/intc-sh5.c |
1da177e4 | 3 | * |
a23ba435 | 4 | * Interrupt Controller support for SH5 INTC. |
1da177e4 LT |
5 | * |
6 | * Copyright (C) 2000, 2001 Paolo Alberelli | |
7 | * Copyright (C) 2003 Paul Mundt | |
8 | * | |
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9 | * Per-interrupt selective. IRLM=0 (Fixed priority) is not |
10 | * supported being useless without a cascaded interrupt | |
11 | * controller. | |
12 | * | |
a23ba435 PM |
13 | * This file is subject to the terms and conditions of the GNU General Public |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
1da177e4 | 16 | */ |
1da177e4 | 17 | #include <linux/init.h> |
da9d5108 | 18 | #include <linux/interrupt.h> |
1da177e4 | 19 | #include <linux/irq.h> |
18bc8131 | 20 | #include <linux/io.h> |
1da177e4 | 21 | #include <linux/kernel.h> |
18bc8131 PM |
22 | #include <linux/bitops.h> |
23 | #include <asm/cpu/irq.h> | |
1da177e4 | 24 | #include <asm/page.h> |
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25 | |
26 | /* | |
27 | * Maybe the generic Peripheral block could move to a more | |
28 | * generic include file. INTC Block will be defined here | |
29 | * and only here to make INTC self-contained in a single | |
30 | * file. | |
31 | */ | |
32 | #define INTC_BLOCK_OFFSET 0x01000000 | |
33 | ||
34 | /* Base */ | |
35 | #define INTC_BASE PHYS_PERIPHERAL_BLOCK + \ | |
36 | INTC_BLOCK_OFFSET | |
37 | ||
38 | /* Address */ | |
39 | #define INTC_ICR_SET (intc_virt + 0x0) | |
40 | #define INTC_ICR_CLEAR (intc_virt + 0x8) | |
41 | #define INTC_INTPRI_0 (intc_virt + 0x10) | |
42 | #define INTC_INTSRC_0 (intc_virt + 0x50) | |
43 | #define INTC_INTSRC_1 (intc_virt + 0x58) | |
44 | #define INTC_INTREQ_0 (intc_virt + 0x60) | |
45 | #define INTC_INTREQ_1 (intc_virt + 0x68) | |
46 | #define INTC_INTENB_0 (intc_virt + 0x70) | |
47 | #define INTC_INTENB_1 (intc_virt + 0x78) | |
48 | #define INTC_INTDSB_0 (intc_virt + 0x80) | |
49 | #define INTC_INTDSB_1 (intc_virt + 0x88) | |
50 | ||
51 | #define INTC_ICR_IRLM 0x1 | |
52 | #define INTC_INTPRI_PREGS 8 /* 8 Priority Registers */ | |
53 | #define INTC_INTPRI_PPREG 8 /* 8 Priorities per Register */ | |
54 | ||
55 | ||
56 | /* | |
57 | * Mapper between the vector ordinal and the IRQ number | |
58 | * passed to kernel/device drivers. | |
59 | */ | |
60 | int intc_evt_to_irq[(0xE20/0x20)+1] = { | |
61 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */ | |
62 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */ | |
63 | 0, 0, 0, 0, 0, 1, 0, 0, /* 0x200 - 0x2E0 */ | |
64 | 2, 0, 0, 3, 0, 0, 0, -1, /* 0x300 - 0x3E0 */ | |
65 | 32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */ | |
66 | -1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */ | |
67 | -1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */ | |
68 | 39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */ | |
69 | 4, 5, 6, 7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */ | |
70 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */ | |
71 | 12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */ | |
72 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */ | |
73 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */ | |
74 | -1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */ | |
75 | -1, -1 /* 0xE00 - 0xE20 */ | |
76 | }; | |
77 | ||
78 | /* | |
79 | * Opposite mapper. | |
80 | */ | |
81 | static int IRQ_to_vectorN[NR_INTC_IRQS] = { | |
82 | 0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */ | |
83 | -1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */ | |
84 | 0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */ | |
85 | -1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */ | |
86 | 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */ | |
87 | 0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */ | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */ | |
89 | -1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */ | |
90 | ||
91 | }; | |
92 | ||
93 | static unsigned long intc_virt; | |
94 | ||
95 | static unsigned int startup_intc_irq(unsigned int irq); | |
96 | static void shutdown_intc_irq(unsigned int irq); | |
97 | static void enable_intc_irq(unsigned int irq); | |
98 | static void disable_intc_irq(unsigned int irq); | |
99 | static void mask_and_ack_intc(unsigned int); | |
100 | static void end_intc_irq(unsigned int irq); | |
101 | ||
102 | static struct hw_interrupt_type intc_irq_type = { | |
c05e0664 TG |
103 | .typename = "INTC", |
104 | .startup = startup_intc_irq, | |
105 | .shutdown = shutdown_intc_irq, | |
106 | .enable = enable_intc_irq, | |
107 | .disable = disable_intc_irq, | |
108 | .ack = mask_and_ack_intc, | |
109 | .end = end_intc_irq | |
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110 | }; |
111 | ||
112 | static int irlm; /* IRL mode */ | |
113 | ||
114 | static unsigned int startup_intc_irq(unsigned int irq) | |
115 | { | |
116 | enable_intc_irq(irq); | |
117 | return 0; /* never anything pending */ | |
118 | } | |
119 | ||
120 | static void shutdown_intc_irq(unsigned int irq) | |
121 | { | |
122 | disable_intc_irq(irq); | |
123 | } | |
124 | ||
125 | static void enable_intc_irq(unsigned int irq) | |
126 | { | |
127 | unsigned long reg; | |
128 | unsigned long bitmask; | |
129 | ||
130 | if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY)) | |
131 | printk("Trying to use straight IRL0-3 with an encoding platform.\n"); | |
132 | ||
133 | if (irq < 32) { | |
134 | reg = INTC_INTENB_0; | |
135 | bitmask = 1 << irq; | |
136 | } else { | |
137 | reg = INTC_INTENB_1; | |
138 | bitmask = 1 << (irq - 32); | |
139 | } | |
140 | ||
141 | ctrl_outl(bitmask, reg); | |
142 | } | |
143 | ||
144 | static void disable_intc_irq(unsigned int irq) | |
145 | { | |
146 | unsigned long reg; | |
147 | unsigned long bitmask; | |
148 | ||
149 | if (irq < 32) { | |
150 | reg = INTC_INTDSB_0; | |
151 | bitmask = 1 << irq; | |
152 | } else { | |
153 | reg = INTC_INTDSB_1; | |
154 | bitmask = 1 << (irq - 32); | |
155 | } | |
156 | ||
157 | ctrl_outl(bitmask, reg); | |
158 | } | |
159 | ||
160 | static void mask_and_ack_intc(unsigned int irq) | |
161 | { | |
162 | disable_intc_irq(irq); | |
163 | } | |
164 | ||
165 | static void end_intc_irq(unsigned int irq) | |
166 | { | |
167 | enable_intc_irq(irq); | |
168 | } | |
169 | ||
170 | /* For future use, if we ever support IRLM=0) */ | |
171 | void make_intc_irq(unsigned int irq) | |
172 | { | |
173 | disable_irq_nosync(irq); | |
d1bef4ed | 174 | irq_desc[irq].chip = &intc_irq_type; |
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175 | disable_intc_irq(irq); |
176 | } | |
177 | ||
178 | #if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL) | |
179 | int intc_irq_describe(char* p, int irq) | |
180 | { | |
181 | if (irq < NR_INTC_IRQS) | |
182 | return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20); | |
183 | else | |
184 | return 0; | |
185 | } | |
186 | #endif | |
187 | ||
18bc8131 | 188 | void __init plat_irq_setup(void) |
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189 | { |
190 | unsigned long long __dummy0, __dummy1=~0x00000000100000f0; | |
191 | unsigned long reg; | |
192 | unsigned long data; | |
193 | int i; | |
194 | ||
195 | intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); | |
196 | if (!intc_virt) { | |
197 | panic("Unable to remap INTC\n"); | |
198 | } | |
199 | ||
200 | ||
201 | /* Set default: per-line enable/disable, priority driven ack/eoi */ | |
202 | for (i = 0; i < NR_INTC_IRQS; i++) { | |
203 | if (platform_int_priority[i] != NO_PRIORITY) { | |
d1bef4ed | 204 | irq_desc[i].chip = &intc_irq_type; |
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205 | } |
206 | } | |
207 | ||
208 | ||
209 | /* Disable all interrupts and set all priorities to 0 to avoid trouble */ | |
210 | ctrl_outl(-1, INTC_INTDSB_0); | |
211 | ctrl_outl(-1, INTC_INTDSB_1); | |
212 | ||
213 | for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8) | |
214 | ctrl_outl( NO_PRIORITY, reg); | |
215 | ||
216 | ||
217 | /* Set IRLM */ | |
218 | /* If all the priorities are set to 'no priority', then | |
219 | * assume we are using encoded mode. | |
220 | */ | |
221 | irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \ | |
222 | platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; | |
223 | ||
224 | if (irlm == NO_PRIORITY) { | |
225 | /* IRLM = 0 */ | |
226 | reg = INTC_ICR_CLEAR; | |
227 | i = IRQ_INTA; | |
228 | printk("Trying to use encoded IRL0-3. IRLs unsupported.\n"); | |
229 | } else { | |
230 | /* IRLM = 1 */ | |
231 | reg = INTC_ICR_SET; | |
232 | i = IRQ_IRL0; | |
233 | } | |
234 | ctrl_outl(INTC_ICR_IRLM, reg); | |
235 | ||
236 | /* Set interrupt priorities according to platform description */ | |
237 | for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { | |
238 | data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); | |
239 | if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { | |
240 | /* Upon the 7th, set Priority Register */ | |
241 | ctrl_outl(data, reg); | |
242 | data = 0; | |
243 | reg += 8; | |
244 | } | |
245 | } | |
246 | ||
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247 | /* |
248 | * And now let interrupts come in. | |
249 | * sti() is not enough, we need to | |
250 | * lower priority, too. | |
251 | */ | |
252 | __asm__ __volatile__("getcon " __SR ", %0\n\t" | |
253 | "and %0, %1, %0\n\t" | |
254 | "putcon %0, " __SR "\n\t" | |
255 | : "=&r" (__dummy0) | |
256 | : "r" (__dummy1)); | |
257 | } |