[deliverable/linux.git] / arch / sh / kernel / cpu / irq / intc.c

/*
 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
 *
 * Copyright (C) 2007, 2008 Magnus Damm
 *
 * Based on intc2.c and ipr.c
 *
 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
 * Copyright (C) 2000  Kazumoto Kojima
 * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
 * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
 * Copyright (C) 2005, 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>

#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
	 ((addr_e) << 16) | ((addr_d << 24)))

#define _INTC_SHIFT(h) (h & 0x1f)
#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
#define _INTC_FN(h) ((h >> 9) & 0xf)
#define _INTC_MODE(h) ((h >> 13) & 0x7)
#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)

struct intc_handle_int {
	unsigned int irq;
	unsigned long handle;
};

struct intc_desc_int {
	unsigned long *reg;
#ifdef CONFIG_SMP
	unsigned long *smp;
#endif
	unsigned int nr_reg;
	struct intc_handle_int *prio;
	unsigned int nr_prio;
	struct intc_handle_int *sense;
	unsigned int nr_sense;
	struct irq_chip chip;
};

#ifdef CONFIG_SMP
#define IS_SMP(x) x.smp
#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
#else
#define IS_SMP(x) 0
#define INTC_REG(d, x, c) (d->reg[(x)])
#define SMP_NR(d, x) 1
#endif

static unsigned int intc_prio_level[NR_IRQS]; /* for now */
#ifdef CONFIG_CPU_SH3
static unsigned long ack_handle[NR_IRQS];
#endif

static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
{
	struct irq_chip *chip = get_irq_chip(irq);
	return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
}

static inline unsigned int set_field(unsigned int value,
				     unsigned int field_value,
				     unsigned int handle)
{
	unsigned int width = _INTC_WIDTH(handle);
	unsigned int shift = _INTC_SHIFT(handle);

	value &= ~(((1 << width) - 1) << shift);
	value |= field_value << shift;
	return value;
}

static void write_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(0, data, h), addr);
}

static void write_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(0, data, h), addr);
}

static void write_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(0, data, h), addr);
}

static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
}

static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
}

static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
}

enum {	REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };

static void (*intc_reg_fns[])(unsigned long addr,
			      unsigned long h,
			      unsigned long data) = {
	[REG_FN_WRITE_BASE + 0] = write_8,
	[REG_FN_WRITE_BASE + 1] = write_16,
	[REG_FN_WRITE_BASE + 3] = write_32,
	[REG_FN_MODIFY_BASE + 0] = modify_8,
	[REG_FN_MODIFY_BASE + 1] = modify_16,
	[REG_FN_MODIFY_BASE + 3] = modify_32,
};

enum {	MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	MODE_MASK_REG,       /* Bit(s) set -> interrupt disabled */
	MODE_DUAL_REG,       /* Two registers, set bit to enable / disable */
	MODE_PRIO_REG,       /* Priority value written to enable interrupt */
	MODE_PCLR_REG,       /* Above plus all bits set to disable interrupt */
};

static void intc_mode_field(unsigned long addr,
			    unsigned long handle,
			    void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			    unsigned int irq)
{
	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
}

static void intc_mode_zero(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, 0);
}

static void intc_mode_prio(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, intc_prio_level[irq]);
}

static void (*intc_enable_fns[])(unsigned long addr,
				 unsigned long handle,
				 void (*fn)(unsigned long,
					    unsigned long,
					    unsigned long),
				 unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_field,
	[MODE_MASK_REG] = intc_mode_zero,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_prio,
	[MODE_PCLR_REG] = intc_mode_prio,
};

static void (*intc_disable_fns[])(unsigned long addr,
				  unsigned long handle,
				  void (*fn)(unsigned long,
					     unsigned long,
					     unsigned long),
				  unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_zero,
	[MODE_MASK_REG] = intc_mode_field,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_zero,
	[MODE_PCLR_REG] = intc_mode_field,
};

static inline void _intc_enable(unsigned int irq, unsigned long handle)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long addr;
	unsigned int cpu;

	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
		addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
		intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
						    [_INTC_FN(handle)], irq);
	}
}

static void intc_enable(unsigned int irq)
{
	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
}

static void intc_disable(unsigned int irq)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
	unsigned long addr;
	unsigned int cpu;

	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
		addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
		intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
						     [_INTC_FN(handle)], irq);
	}
}

#ifdef CONFIG_CPU_SH3
static void intc_mask_ack(unsigned int irq)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long handle = ack_handle[irq];
	unsigned long addr;

	intc_disable(irq);

	/* read register and write zero only to the assocaited bit */

	if (handle) {
		addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
		ctrl_inb(addr);
		ctrl_outb(0x3f ^ set_field(0, 1, handle), addr);
	}
}
#endif

static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
					     unsigned int nr_hp,
					     unsigned int irq)
{
	int i;

	/* this doesn't scale well, but...
	 *
	 * this function should only be used for cerain uncommon
	 * operations such as intc_set_priority() and intc_set_sense()
	 * and in those rare cases performance doesn't matter that much.
	 * keeping the memory footprint low is more important.
	 *
	 * one rather simple way to speed this up and still keep the
	 * memory footprint down is to make sure the array is sorted
	 * and then perform a bisect to lookup the irq.
	 */

	for (i = 0; i < nr_hp; i++) {
		if ((hp + i)->irq != irq)
			continue;

		return hp + i;
	}

	return NULL;
}

int intc_set_priority(unsigned int irq, unsigned int prio)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	struct intc_handle_int *ihp;

	if (!intc_prio_level[irq] || prio <= 1)
		return -EINVAL;

	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	if (ihp) {
		if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
			return -EINVAL;

		intc_prio_level[irq] = prio;

		/*
		 * only set secondary masking method directly
		 * primary masking method is using intc_prio_level[irq]
		 * priority level will be set during next enable()
		 */

		if (_INTC_FN(ihp->handle) != REG_FN_ERR)
			_intc_enable(irq, ihp->handle);
	}
	return 0;
}

#define VALID(x) (x | 0x80)

static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
	/* SH7706, SH7707 and SH7709 do not support high level triggered */
#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7709)
	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
#endif
};

static int intc_set_sense(unsigned int irq, unsigned int type)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct intc_handle_int *ihp;
	unsigned long addr;

	if (!value)
		return -EINVAL;

	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
	if (ihp) {
		addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
		intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
	}
	return 0;
}

static unsigned int __init intc_get_reg(struct intc_desc_int *d,
				 unsigned long address)
{
	unsigned int k;

	for (k = 0; k < d->nr_reg; k++) {
		if (d->reg[k] == address)
			return k;
	}

	BUG();
	return 0;
}

static intc_enum __init intc_grp_id(struct intc_desc *desc,
				    intc_enum enum_id)
{
	struct intc_group *g = desc->groups;
	unsigned int i, j;

	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
		g = desc->groups + i;

		for (j = 0; g->enum_ids[j]; j++) {
			if (g->enum_ids[j] != enum_id)
				continue;

			return g->enum_id;
		}
	}

	return 0;
}

static unsigned int __init intc_mask_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_mask_reg *mr = desc->mask_regs;
	unsigned int i, j, fn, mode;
	unsigned long reg_e, reg_d;

	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
		mr = desc->mask_regs + i;

		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
			if (mr->enum_ids[j] != enum_id)
				continue;

			if (mr->set_reg && mr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_DUAL_REG;
				reg_e = mr->clr_reg;
				reg_d = mr->set_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				if (mr->set_reg) {
					mode = MODE_ENABLE_REG;
					reg_e = mr->set_reg;
					reg_d = mr->set_reg;
				} else {
					mode = MODE_MASK_REG;
					reg_e = mr->clr_reg;
					reg_d = mr->clr_reg;
				}
			}

			fn += (mr->reg_width >> 3) - 1;
			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					1,
					(mr->reg_width - 1) - j);
		}
	}

	if (do_grps)
		return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

static unsigned int __init intc_prio_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_prio_reg *pr = desc->prio_regs;
	unsigned int i, j, fn, mode, bit;
	unsigned long reg_e, reg_d;

	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
		pr = desc->prio_regs + i;

		for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
			if (pr->enum_ids[j] != enum_id)
				continue;

			if (pr->set_reg && pr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_PCLR_REG;
				reg_e = pr->set_reg;
				reg_d = pr->clr_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				mode = MODE_PRIO_REG;
				if (!pr->set_reg)
					BUG();
				reg_e = pr->set_reg;
				reg_d = pr->set_reg;
			}

			fn += (pr->reg_width >> 3) - 1;
			bit = pr->reg_width - ((j + 1) * pr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					pr->field_width, bit);
		}
	}

	if (do_grps)
		return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

#ifdef CONFIG_CPU_SH3
static unsigned int __init intc_ack_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id)
{
	struct intc_mask_reg *mr = desc->ack_regs;
	unsigned int i, j, fn, mode;
	unsigned long reg_e, reg_d;

	for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
		mr = desc->ack_regs + i;

		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
			if (mr->enum_ids[j] != enum_id)
				continue;

			fn = REG_FN_MODIFY_BASE;
			mode = MODE_ENABLE_REG;
			reg_e = mr->set_reg;
			reg_d = mr->set_reg;

			fn += (mr->reg_width >> 3) - 1;
			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					1,
					(mr->reg_width - 1) - j);
		}
	}

	return 0;
}
#endif

static unsigned int __init intc_sense_data(struct intc_desc *desc,
					   struct intc_desc_int *d,
					   intc_enum enum_id)
{
	struct intc_sense_reg *sr = desc->sense_regs;
	unsigned int i, j, fn, bit;

	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
		sr = desc->sense_regs + i;

		for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
			if (sr->enum_ids[j] != enum_id)
				continue;

			fn = REG_FN_MODIFY_BASE;
			fn += (sr->reg_width >> 3) - 1;
			bit = sr->reg_width - ((j + 1) * sr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
					0, sr->field_width, bit);
		}
	}

	return 0;
}

static void __init intc_register_irq(struct intc_desc *desc,
				     struct intc_desc_int *d,
				     intc_enum enum_id,
				     unsigned int irq)
{
	struct intc_handle_int *hp;
	unsigned int data[2], primary;

	/* Prefer single interrupt source bitmap over other combinations:
	 * 1. bitmap, single interrupt source
	 * 2. priority, single interrupt source
	 * 3. bitmap, multiple interrupt sources (groups)
	 * 4. priority, multiple interrupt sources (groups)
	 */

	data[0] = intc_mask_data(desc, d, enum_id, 0);
	data[1] = intc_prio_data(desc, d, enum_id, 0);

	primary = 0;
	if (!data[0] && data[1])
		primary = 1;

	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);

	if (!data[primary])
		primary ^= 1;

	BUG_ON(!data[primary]); /* must have primary masking method */

	disable_irq_nosync(irq);
	set_irq_chip_and_handler_name(irq, &d->chip,
				      handle_level_irq, "level");
	set_irq_chip_data(irq, (void *)data[primary]);

	/* set priority level
	 * - this needs to be at least 2 for 5-bit priorities on 7780
	 */
	intc_prio_level[irq] = 2;

	/* enable secondary masking method if present */
	if (data[!primary])
		_intc_enable(irq, data[!primary]);

	/* add irq to d->prio list if priority is available */
	if (data[1]) {
		hp = d->prio + d->nr_prio;
		hp->irq = irq;
		hp->handle = data[1];

		if (primary) {
			/*
			 * only secondary priority should access registers, so
			 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
			 */

			hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
			hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
		}
		d->nr_prio++;
	}

	/* add irq to d->sense list if sense is available */
	data[0] = intc_sense_data(desc, d, enum_id);
	if (data[0]) {
		(d->sense + d->nr_sense)->irq = irq;
		(d->sense + d->nr_sense)->handle = data[0];
		d->nr_sense++;
	}

	/* irq should be disabled by default */
	d->chip.mask(irq);

#ifdef CONFIG_CPU_SH3
	if (desc->ack_regs)
		ack_handle[irq] = intc_ack_data(desc, d, enum_id);
#endif
}

static unsigned int __init save_reg(struct intc_desc_int *d,
				    unsigned int cnt,
				    unsigned long value,
				    unsigned int smp)
{
	if (value) {
		d->reg[cnt] = value;
#ifdef CONFIG_SMP
		d->smp[cnt] = smp;
#endif
		return 1;
	}

	return 0;
}


void __init register_intc_controller(struct intc_desc *desc)
{
	unsigned int i, k, smp;
	struct intc_desc_int *d;

	d = alloc_bootmem(sizeof(*d));

	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;

#ifdef CONFIG_CPU_SH3
	d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
#endif
	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
#ifdef CONFIG_SMP
	d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
#endif
	k = 0;

	if (desc->mask_regs) {
		for (i = 0; i < desc->nr_mask_regs; i++) {
			smp = IS_SMP(desc->mask_regs[i]);
			k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
			k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
		}
	}

	if (desc->prio_regs) {
		d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));

		for (i = 0; i < desc->nr_prio_regs; i++) {
			smp = IS_SMP(desc->prio_regs[i]);
			k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
			k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
		}
	}

	if (desc->sense_regs) {
		d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));

		for (i = 0; i < desc->nr_sense_regs; i++) {
			k += save_reg(d, k, desc->sense_regs[i].reg, 0);
		}
	}

	d->chip.name = desc->name;
	d->chip.mask = intc_disable;
	d->chip.unmask = intc_enable;
	d->chip.mask_ack = intc_disable;
	d->chip.set_type = intc_set_sense;

#ifdef CONFIG_CPU_SH3
	if (desc->ack_regs) {
		for (i = 0; i < desc->nr_ack_regs; i++)
			k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);

		d->chip.mask_ack = intc_mask_ack;
	}
#endif

	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */

	for (i = 0; i < desc->nr_vectors; i++) {
		struct intc_vect *vect = desc->vectors + i;

		intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
	}
}
Commit	Line	Data
02ab3f70 MD	1	/*
	2	* Shared interrupt handling code for IPR and INTC2 types of IRQs.
	3	*
d58876e2	4	* Copyright (C) 2007, 2008 Magnus Damm
02ab3f70 MD	5	*
	6	* Based on intc2.c and ipr.c
	7	*
	8	* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
	9	* Copyright (C) 2000 Kazumoto Kojima
	10	* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
	11	* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
	12	* Copyright (C) 2005, 2006 Paul Mundt
	13	*
	14	* This file is subject to the terms and conditions of the GNU General Public
	15	* License. See the file "COPYING" in the main directory of this archive
	16	* for more details.
	17	*/
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/module.h>
	21	#include <linux/io.h>
	22	#include <linux/interrupt.h>
73505b44 MD	23	#include <linux/bootmem.h>
	24
	25	#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	26	((shift) \| ((width) << 5) \| ((fn) << 9) \| ((mode) << 13) \| \
	27	((addr_e) << 16) \| ((addr_d << 24)))
	28
	29	#define _INTC_SHIFT(h) (h & 0x1f)
	30	#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
	31	#define _INTC_FN(h) ((h >> 9) & 0xf)
	32	#define _INTC_MODE(h) ((h >> 13) & 0x7)
	33	#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
	34	#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
	35
	36	struct intc_handle_int {
	37	unsigned int irq;
	38	unsigned long handle;
	39	};
02ab3f70	40
73505b44 MD	41	struct intc_desc_int {
73505b44 MD	42	unsigned long *reg;
f18d533e MD	43	#ifdef CONFIG_SMP
	44	unsigned long *smp;
	45	#endif
73505b44 MD	46	unsigned int nr_reg;
	47	struct intc_handle_int *prio;
	48	unsigned int nr_prio;
	49	struct intc_handle_int *sense;
	50	unsigned int nr_sense;
	51	struct irq_chip chip;
	52	};
02ab3f70	53
f18d533e MD	54	#ifdef CONFIG_SMP
	55	#define IS_SMP(x) x.smp
	56	#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
	57	#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
	58	#else
	59	#define IS_SMP(x) 0
	60	#define INTC_REG(d, x, c) (d->reg[(x)])
	61	#define SMP_NR(d, x) 1
	62	#endif
	63
73505b44	64	static unsigned int intc_prio_level[NR_IRQS]; /* for now */
d58876e2 MD	65	#ifdef CONFIG_CPU_SH3
	66	static unsigned long ack_handle[NR_IRQS];
	67	#endif
02ab3f70	68
73505b44	69	static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
02ab3f70 MD	70	{
02ab3f70 MD	71	struct irq_chip *chip = get_irq_chip(irq);
73505b44	72	return (void )((char )chip - offsetof(struct intc_desc_int, chip));
02ab3f70 MD	73	}
	74
	75	static inline unsigned int set_field(unsigned int value,
	76	unsigned int field_value,
73505b44	77	unsigned int handle)
02ab3f70	78	{
73505b44 MD	79	unsigned int width = _INTC_WIDTH(handle);
	80	unsigned int shift = _INTC_SHIFT(handle);
	81
02ab3f70 MD	82	value &= ~(((1 << width) - 1) << shift);
	83	value \|= field_value << shift;
	84	return value;
	85	}
	86
73505b44	87	static void write_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	88	{
73505b44	89	ctrl_outb(set_field(0, data, h), addr);
02ab3f70 MD	90	}
02ab3f70 MD	91
73505b44	92	static void write_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	93	{
73505b44	94	ctrl_outw(set_field(0, data, h), addr);
02ab3f70 MD	95	}
02ab3f70 MD	96
73505b44	97	static void write_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	98	{
73505b44	99	ctrl_outl(set_field(0, data, h), addr);
02ab3f70 MD	100	}
02ab3f70 MD	101
73505b44	102	static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	103	{
73505b44	104	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
02ab3f70 MD	105	}
02ab3f70 MD	106
73505b44	107	static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	108	{
73505b44	109	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
02ab3f70 MD	110	}
02ab3f70 MD	111
73505b44	112	static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	113	{
73505b44	114	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
02ab3f70 MD	115	}
02ab3f70 MD	116
73505b44 MD	117	enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
	118
	119	static void (*intc_reg_fns[])(unsigned long addr,
	120	unsigned long h,
	121	unsigned long data) = {
	122	[REG_FN_WRITE_BASE + 0] = write_8,
	123	[REG_FN_WRITE_BASE + 1] = write_16,
	124	[REG_FN_WRITE_BASE + 3] = write_32,
	125	[REG_FN_MODIFY_BASE + 0] = modify_8,
	126	[REG_FN_MODIFY_BASE + 1] = modify_16,
	127	[REG_FN_MODIFY_BASE + 3] = modify_32,
	128	};
02ab3f70	129
73505b44 MD	130	enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	131	MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
	132	MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
	133	MODE_PRIO_REG, /* Priority value written to enable interrupt */
	134	MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
	135	};
02ab3f70	136
73505b44 MD	137	static void intc_mode_field(unsigned long addr,
	138	unsigned long handle,
	139	void (*fn)(unsigned long,
	140	unsigned long,
	141	unsigned long),
	142	unsigned int irq)
02ab3f70	143	{
73505b44	144	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
02ab3f70 MD	145	}
02ab3f70 MD	146
73505b44 MD	147	static void intc_mode_zero(unsigned long addr,
	148	unsigned long handle,
	149	void (*fn)(unsigned long,
	150	unsigned long,
	151	unsigned long),
	152	unsigned int irq)
51da6426	153	{
73505b44	154	fn(addr, handle, 0);
51da6426 MD	155	}
51da6426 MD	156
73505b44 MD	157	static void intc_mode_prio(unsigned long addr,
	158	unsigned long handle,
	159	void (*fn)(unsigned long,
	160	unsigned long,
	161	unsigned long),
	162	unsigned int irq)
51da6426	163	{
73505b44	164	fn(addr, handle, intc_prio_level[irq]);
51da6426 MD	165	}
51da6426 MD	166
73505b44 MD	167	static void (*intc_enable_fns[])(unsigned long addr,
	168	unsigned long handle,
	169	void (*fn)(unsigned long,
	170	unsigned long,
	171	unsigned long),
	172	unsigned int irq) = {
	173	[MODE_ENABLE_REG] = intc_mode_field,
	174	[MODE_MASK_REG] = intc_mode_zero,
	175	[MODE_DUAL_REG] = intc_mode_field,
	176	[MODE_PRIO_REG] = intc_mode_prio,
	177	[MODE_PCLR_REG] = intc_mode_prio,
	178	};
51da6426	179
73505b44 MD	180	static void (*intc_disable_fns[])(unsigned long addr,
	181	unsigned long handle,
	182	void (*fn)(unsigned long,
	183	unsigned long,
	184	unsigned long),
	185	unsigned int irq) = {
	186	[MODE_ENABLE_REG] = intc_mode_zero,
	187	[MODE_MASK_REG] = intc_mode_field,
	188	[MODE_DUAL_REG] = intc_mode_field,
	189	[MODE_PRIO_REG] = intc_mode_zero,
	190	[MODE_PCLR_REG] = intc_mode_field,
	191	};
51da6426	192
73505b44	193	static inline void _intc_enable(unsigned int irq, unsigned long handle)
51da6426	194	{
73505b44	195	struct intc_desc_int *d = get_intc_desc(irq);
f18d533e MD	196	unsigned long addr;
f18d533e MD	197	unsigned int cpu;
51da6426	198
f18d533e MD	199	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
	200	addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
	201	intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
	202	[_INTC_FN(handle)], irq);
	203	}
51da6426 MD	204	}
51da6426 MD	205
02ab3f70 MD	206	static void intc_enable(unsigned int irq)
02ab3f70 MD	207	{
73505b44	208	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
02ab3f70 MD	209	}
	210
	211	static void intc_disable(unsigned int irq)
	212	{
f18d533e	213	struct intc_desc_int *d = get_intc_desc(irq);
73505b44	214	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
f18d533e MD	215	unsigned long addr;
f18d533e MD	216	unsigned int cpu;
02ab3f70	217
f18d533e MD	218	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
	219	addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
	220	intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
	221	[_INTC_FN(handle)], irq);
	222	}
02ab3f70 MD	223	}
02ab3f70 MD	224
d58876e2 MD	225	#ifdef CONFIG_CPU_SH3
	226	static void intc_mask_ack(unsigned int irq)
	227	{
	228	struct intc_desc_int *d = get_intc_desc(irq);
	229	unsigned long handle = ack_handle[irq];
	230	unsigned long addr;
	231
	232	intc_disable(irq);
	233
	234	/* read register and write zero only to the assocaited bit */
	235
	236	if (handle) {
	237	addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
	238	ctrl_inb(addr);
	239	ctrl_outb(0x3f ^ set_field(0, 1, handle), addr);
	240	}
	241	}
	242	#endif
	243
73505b44 MD	244	static struct intc_handle_int intc_find_irq(struct intc_handle_int hp,
	245	unsigned int nr_hp,
	246	unsigned int irq)
02ab3f70	247	{
73505b44 MD	248	int i;
73505b44 MD	249
3d37d94e MD	250	/* this doesn't scale well, but...
	251	*
	252	* this function should only be used for cerain uncommon
	253	* operations such as intc_set_priority() and intc_set_sense()
	254	* and in those rare cases performance doesn't matter that much.
	255	* keeping the memory footprint low is more important.
	256	*
	257	* one rather simple way to speed this up and still keep the
	258	* memory footprint down is to make sure the array is sorted
	259	* and then perform a bisect to lookup the irq.
	260	*/
	261
73505b44 MD	262	for (i = 0; i < nr_hp; i++) {
	263	if ((hp + i)->irq != irq)
	264	continue;
	265
	266	return hp + i;
	267	}
02ab3f70	268
73505b44	269	return NULL;
02ab3f70 MD	270	}
02ab3f70 MD	271
73505b44	272	int intc_set_priority(unsigned int irq, unsigned int prio)
02ab3f70	273	{
73505b44 MD	274	struct intc_desc_int *d = get_intc_desc(irq);
	275	struct intc_handle_int *ihp;
	276
	277	if (!intc_prio_level[irq] \|\| prio <= 1)
	278	return -EINVAL;
	279
	280	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	281	if (ihp) {
3d37d94e	282	if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
73505b44	283	return -EINVAL;
02ab3f70	284
73505b44 MD	285	intc_prio_level[irq] = prio;
	286
	287	/*
	288	* only set secondary masking method directly
	289	* primary masking method is using intc_prio_level[irq]
	290	* priority level will be set during next enable()
	291	*/
	292
3d37d94e	293	if (_INTC_FN(ihp->handle) != REG_FN_ERR)
73505b44 MD	294	_intc_enable(irq, ihp->handle);
	295	}
	296	return 0;
02ab3f70 MD	297	}
	298
	299	#define VALID(x) (x \| 0x80)
	300
	301	static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	302	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	303	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	304	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
720be990 MD	305	/* SH7706, SH7707 and SH7709 do not support high level triggered */
	306	#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
	307	!defined(CONFIG_CPU_SUBTYPE_SH7707) && \
	308	!defined(CONFIG_CPU_SUBTYPE_SH7709)
02ab3f70	309	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
720be990	310	#endif
02ab3f70 MD	311	};
	312
	313	static int intc_set_sense(unsigned int irq, unsigned int type)
	314	{
73505b44	315	struct intc_desc_int *d = get_intc_desc(irq);
02ab3f70	316	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
73505b44 MD	317	struct intc_handle_int *ihp;
73505b44 MD	318	unsigned long addr;
02ab3f70	319
73505b44	320	if (!value)
02ab3f70 MD	321	return -EINVAL;
02ab3f70 MD	322
73505b44 MD	323	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
73505b44 MD	324	if (ihp) {
f18d533e	325	addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
73505b44	326	intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
02ab3f70	327	}
73505b44	328	return 0;
02ab3f70 MD	329	}
02ab3f70 MD	330
73505b44 MD	331	static unsigned int __init intc_get_reg(struct intc_desc_int *d,
73505b44 MD	332	unsigned long address)
02ab3f70	333	{
73505b44	334	unsigned int k;
02ab3f70	335
73505b44 MD	336	for (k = 0; k < d->nr_reg; k++) {
	337	if (d->reg[k] == address)
	338	return k;
51da6426 MD	339	}
	340
	341	BUG();
73505b44	342	return 0;
51da6426 MD	343	}
51da6426 MD	344
73505b44 MD	345	static intc_enum __init intc_grp_id(struct intc_desc *desc,
73505b44 MD	346	intc_enum enum_id)
680c4598 MD	347	{
	348	struct intc_group *g = desc->groups;
	349	unsigned int i, j;
	350
	351	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
	352	g = desc->groups + i;
	353
	354	for (j = 0; g->enum_ids[j]; j++) {
	355	if (g->enum_ids[j] != enum_id)
	356	continue;
	357
	358	return g->enum_id;
	359	}
	360	}
	361
	362	return 0;
	363	}
	364
02ab3f70	365	static unsigned int __init intc_mask_data(struct intc_desc *desc,
73505b44	366	struct intc_desc_int *d,
680c4598	367	intc_enum enum_id, int do_grps)
02ab3f70	368	{
680c4598	369	struct intc_mask_reg *mr = desc->mask_regs;
73505b44 MD	370	unsigned int i, j, fn, mode;
73505b44 MD	371	unsigned long reg_e, reg_d;
02ab3f70	372
680c4598 MD	373	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
680c4598 MD	374	mr = desc->mask_regs + i;
02ab3f70 MD	375
	376	for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
	377	if (mr->enum_ids[j] != enum_id)
	378	continue;
	379
73505b44 MD	380	if (mr->set_reg && mr->clr_reg) {
	381	fn = REG_FN_WRITE_BASE;
	382	mode = MODE_DUAL_REG;
	383	reg_e = mr->clr_reg;
	384	reg_d = mr->set_reg;
	385	} else {
	386	fn = REG_FN_MODIFY_BASE;
	387	if (mr->set_reg) {
	388	mode = MODE_ENABLE_REG;
	389	reg_e = mr->set_reg;
	390	reg_d = mr->set_reg;
	391	} else {
	392	mode = MODE_MASK_REG;
	393	reg_e = mr->clr_reg;
	394	reg_d = mr->clr_reg;
	395	}
51da6426 MD	396	}
51da6426 MD	397
73505b44 MD	398	fn += (mr->reg_width >> 3) - 1;
	399	return _INTC_MK(fn, mode,
	400	intc_get_reg(d, reg_e),
	401	intc_get_reg(d, reg_d),
	402	1,
	403	(mr->reg_width - 1) - j);
02ab3f70 MD	404	}
	405	}
	406
680c4598	407	if (do_grps)
73505b44	408	return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
680c4598	409
02ab3f70 MD	410	return 0;
	411	}
	412
	413	static unsigned int __init intc_prio_data(struct intc_desc *desc,
73505b44	414	struct intc_desc_int *d,
680c4598	415	intc_enum enum_id, int do_grps)
02ab3f70	416	{
680c4598	417	struct intc_prio_reg *pr = desc->prio_regs;
73505b44 MD	418	unsigned int i, j, fn, mode, bit;
73505b44 MD	419	unsigned long reg_e, reg_d;
02ab3f70	420
680c4598 MD	421	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
680c4598 MD	422	pr = desc->prio_regs + i;
02ab3f70 MD	423
	424	for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
	425	if (pr->enum_ids[j] != enum_id)
	426	continue;
	427
73505b44 MD	428	if (pr->set_reg && pr->clr_reg) {
	429	fn = REG_FN_WRITE_BASE;
	430	mode = MODE_PCLR_REG;
	431	reg_e = pr->set_reg;
	432	reg_d = pr->clr_reg;
	433	} else {
	434	fn = REG_FN_MODIFY_BASE;
	435	mode = MODE_PRIO_REG;
	436	if (!pr->set_reg)
	437	BUG();
	438	reg_e = pr->set_reg;
	439	reg_d = pr->set_reg;
	440	}
02ab3f70	441
73505b44	442	fn += (pr->reg_width >> 3) - 1;
02ab3f70 MD	443	bit = pr->reg_width - ((j + 1) * pr->field_width);
	444
	445	BUG_ON(bit < 0);
	446
73505b44 MD	447	return _INTC_MK(fn, mode,
	448	intc_get_reg(d, reg_e),
	449	intc_get_reg(d, reg_d),
	450	pr->field_width, bit);
02ab3f70 MD	451	}
	452	}
	453
680c4598	454	if (do_grps)
73505b44 MD	455	return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
	456
	457	return 0;
	458	}
	459
d58876e2 MD	460	#ifdef CONFIG_CPU_SH3
	461	static unsigned int __init intc_ack_data(struct intc_desc *desc,
	462	struct intc_desc_int *d,
	463	intc_enum enum_id)
	464	{
	465	struct intc_mask_reg *mr = desc->ack_regs;
	466	unsigned int i, j, fn, mode;
	467	unsigned long reg_e, reg_d;
	468
	469	for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
	470	mr = desc->ack_regs + i;
	471
	472	for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
	473	if (mr->enum_ids[j] != enum_id)
	474	continue;
	475
	476	fn = REG_FN_MODIFY_BASE;
	477	mode = MODE_ENABLE_REG;
	478	reg_e = mr->set_reg;
	479	reg_d = mr->set_reg;
	480
	481	fn += (mr->reg_width >> 3) - 1;
	482	return _INTC_MK(fn, mode,
	483	intc_get_reg(d, reg_e),
	484	intc_get_reg(d, reg_d),
	485	1,
	486	(mr->reg_width - 1) - j);
	487	}
	488	}
	489
	490	return 0;
	491	}
	492	#endif
	493
73505b44 MD	494	static unsigned int __init intc_sense_data(struct intc_desc *desc,
	495	struct intc_desc_int *d,
	496	intc_enum enum_id)
	497	{
	498	struct intc_sense_reg *sr = desc->sense_regs;
	499	unsigned int i, j, fn, bit;
	500
	501	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
	502	sr = desc->sense_regs + i;
	503
	504	for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
	505	if (sr->enum_ids[j] != enum_id)
	506	continue;
	507
	508	fn = REG_FN_MODIFY_BASE;
	509	fn += (sr->reg_width >> 3) - 1;
	510	bit = sr->reg_width - ((j + 1) * sr->field_width);
	511
	512	BUG_ON(bit < 0);
	513
	514	return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
	515	0, sr->field_width, bit);
	516	}
	517	}
680c4598	518
02ab3f70 MD	519	return 0;
	520	}
	521
73505b44 MD	522	static void __init intc_register_irq(struct intc_desc *desc,
	523	struct intc_desc_int *d,
	524	intc_enum enum_id,
02ab3f70 MD	525	unsigned int irq)
02ab3f70 MD	526	{
3d37d94e	527	struct intc_handle_int *hp;
680c4598 MD	528	unsigned int data[2], primary;
	529
	530	/* Prefer single interrupt source bitmap over other combinations:
	531	* 1. bitmap, single interrupt source
	532	* 2. priority, single interrupt source
	533	* 3. bitmap, multiple interrupt sources (groups)
	534	* 4. priority, multiple interrupt sources (groups)
	535	*/
02ab3f70	536
73505b44 MD	537	data[0] = intc_mask_data(desc, d, enum_id, 0);
73505b44 MD	538	data[1] = intc_prio_data(desc, d, enum_id, 0);
680c4598 MD	539
	540	primary = 0;
	541	if (!data[0] && data[1])
	542	primary = 1;
	543
73505b44 MD	544	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
73505b44 MD	545	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
680c4598 MD	546
	547	if (!data[primary])
	548	primary ^= 1;
	549
	550	BUG_ON(!data[primary]); /* must have primary masking method */
02ab3f70 MD	551
02ab3f70 MD	552	disable_irq_nosync(irq);
73505b44	553	set_irq_chip_and_handler_name(irq, &d->chip,
02ab3f70	554	handle_level_irq, "level");
680c4598	555	set_irq_chip_data(irq, (void *)data[primary]);
02ab3f70	556
7f3edee8 MD	557	/* set priority level
	558	* - this needs to be at least 2 for 5-bit priorities on 7780
	559	*/
	560	intc_prio_level[irq] = 2;
73505b44	561
680c4598 MD	562	/* enable secondary masking method if present */
680c4598 MD	563	if (data[!primary])
73505b44 MD	564	_intc_enable(irq, data[!primary]);
	565
	566	/* add irq to d->prio list if priority is available */
	567	if (data[1]) {
3d37d94e MD	568	hp = d->prio + d->nr_prio;
	569	hp->irq = irq;
	570	hp->handle = data[1];
	571
	572	if (primary) {
	573	/*
	574	* only secondary priority should access registers, so
	575	* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
	576	*/
	577
	578	hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
	579	hp->handle \|= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
	580	}
73505b44 MD	581	d->nr_prio++;
	582	}
	583
	584	/* add irq to d->sense list if sense is available */
	585	data[0] = intc_sense_data(desc, d, enum_id);
	586	if (data[0]) {
	587	(d->sense + d->nr_sense)->irq = irq;
	588	(d->sense + d->nr_sense)->handle = data[0];
	589	d->nr_sense++;
	590	}
02ab3f70 MD	591
02ab3f70 MD	592	/* irq should be disabled by default */
73505b44	593	d->chip.mask(irq);
d58876e2 MD	594
	595	#ifdef CONFIG_CPU_SH3
	596	if (desc->ack_regs)
	597	ack_handle[irq] = intc_ack_data(desc, d, enum_id);
	598	#endif
02ab3f70 MD	599	}
02ab3f70 MD	600
f18d533e MD	601	static unsigned int __init save_reg(struct intc_desc_int *d,
	602	unsigned int cnt,
	603	unsigned long value,
	604	unsigned int smp)
	605	{
	606	if (value) {
	607	d->reg[cnt] = value;
	608	#ifdef CONFIG_SMP
	609	d->smp[cnt] = smp;
	610	#endif
	611	return 1;
	612	}
	613
	614	return 0;
	615	}
	616
	617
02ab3f70 MD	618	void __init register_intc_controller(struct intc_desc *desc)
02ab3f70 MD	619	{
f18d533e	620	unsigned int i, k, smp;
73505b44 MD	621	struct intc_desc_int *d;
	622
	623	d = alloc_bootmem(sizeof(*d));
	624
	625	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	626	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	627	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
	628
d58876e2 MD	629	#ifdef CONFIG_CPU_SH3
	630	d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
	631	#endif
73505b44	632	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
f18d533e MD	633	#ifdef CONFIG_SMP
	634	d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
	635	#endif
73505b44 MD	636	k = 0;
	637
	638	if (desc->mask_regs) {
	639	for (i = 0; i < desc->nr_mask_regs; i++) {
f18d533e MD	640	smp = IS_SMP(desc->mask_regs[i]);
	641	k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
	642	k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
73505b44 MD	643	}
	644	}
	645
	646	if (desc->prio_regs) {
	647	d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
	648
	649	for (i = 0; i < desc->nr_prio_regs; i++) {
f18d533e MD	650	smp = IS_SMP(desc->prio_regs[i]);
	651	k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
	652	k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
73505b44 MD	653	}
	654	}
	655
	656	if (desc->sense_regs) {
	657	d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
	658
	659	for (i = 0; i < desc->nr_sense_regs; i++) {
f18d533e	660	k += save_reg(d, k, desc->sense_regs[i].reg, 0);
73505b44 MD	661	}
	662	}
	663
73505b44 MD	664	d->chip.name = desc->name;
	665	d->chip.mask = intc_disable;
	666	d->chip.unmask = intc_enable;
	667	d->chip.mask_ack = intc_disable;
	668	d->chip.set_type = intc_set_sense;
02ab3f70	669
d58876e2 MD	670	#ifdef CONFIG_CPU_SH3
	671	if (desc->ack_regs) {
	672	for (i = 0; i < desc->nr_ack_regs; i++)
	673	k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
	674
	675	d->chip.mask_ack = intc_mask_ack;
	676	}
	677	#endif
	678
	679	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
	680
02ab3f70 MD	681	for (i = 0; i < desc->nr_vectors; i++) {
	682	struct intc_vect *vect = desc->vectors + i;
	683
73505b44	684	intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
02ab3f70 MD	685	}
02ab3f70 MD	686	}