Commit | Line | Data |
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02ab3f70 MD |
1 | /* |
2 | * Shared interrupt handling code for IPR and INTC2 types of IRQs. | |
3 | * | |
d58876e2 | 4 | * Copyright (C) 2007, 2008 Magnus Damm |
02ab3f70 MD |
5 | * |
6 | * Based on intc2.c and ipr.c | |
7 | * | |
8 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
9 | * Copyright (C) 2000 Kazumoto Kojima | |
10 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | |
11 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | |
12 | * Copyright (C) 2005, 2006 Paul Mundt | |
13 | * | |
14 | * This file is subject to the terms and conditions of the GNU General Public | |
15 | * License. See the file "COPYING" in the main directory of this archive | |
16 | * for more details. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/interrupt.h> | |
73505b44 MD |
23 | #include <linux/bootmem.h> |
24 | ||
25 | #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ | |
26 | ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ | |
27 | ((addr_e) << 16) | ((addr_d << 24))) | |
28 | ||
29 | #define _INTC_SHIFT(h) (h & 0x1f) | |
30 | #define _INTC_WIDTH(h) ((h >> 5) & 0xf) | |
31 | #define _INTC_FN(h) ((h >> 9) & 0xf) | |
32 | #define _INTC_MODE(h) ((h >> 13) & 0x7) | |
33 | #define _INTC_ADDR_E(h) ((h >> 16) & 0xff) | |
34 | #define _INTC_ADDR_D(h) ((h >> 24) & 0xff) | |
35 | ||
36 | struct intc_handle_int { | |
37 | unsigned int irq; | |
38 | unsigned long handle; | |
39 | }; | |
02ab3f70 | 40 | |
73505b44 MD |
41 | struct intc_desc_int { |
42 | unsigned long *reg; | |
f18d533e MD |
43 | #ifdef CONFIG_SMP |
44 | unsigned long *smp; | |
45 | #endif | |
73505b44 MD |
46 | unsigned int nr_reg; |
47 | struct intc_handle_int *prio; | |
48 | unsigned int nr_prio; | |
49 | struct intc_handle_int *sense; | |
50 | unsigned int nr_sense; | |
51 | struct irq_chip chip; | |
52 | }; | |
02ab3f70 | 53 | |
f18d533e MD |
54 | #ifdef CONFIG_SMP |
55 | #define IS_SMP(x) x.smp | |
56 | #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) | |
57 | #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) | |
58 | #else | |
59 | #define IS_SMP(x) 0 | |
60 | #define INTC_REG(d, x, c) (d->reg[(x)]) | |
61 | #define SMP_NR(d, x) 1 | |
62 | #endif | |
63 | ||
73505b44 | 64 | static unsigned int intc_prio_level[NR_IRQS]; /* for now */ |
6bdfb22a | 65 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
66 | static unsigned long ack_handle[NR_IRQS]; |
67 | #endif | |
02ab3f70 | 68 | |
73505b44 | 69 | static inline struct intc_desc_int *get_intc_desc(unsigned int irq) |
02ab3f70 MD |
70 | { |
71 | struct irq_chip *chip = get_irq_chip(irq); | |
73505b44 | 72 | return (void *)((char *)chip - offsetof(struct intc_desc_int, chip)); |
02ab3f70 MD |
73 | } |
74 | ||
75 | static inline unsigned int set_field(unsigned int value, | |
76 | unsigned int field_value, | |
73505b44 | 77 | unsigned int handle) |
02ab3f70 | 78 | { |
73505b44 MD |
79 | unsigned int width = _INTC_WIDTH(handle); |
80 | unsigned int shift = _INTC_SHIFT(handle); | |
81 | ||
02ab3f70 MD |
82 | value &= ~(((1 << width) - 1) << shift); |
83 | value |= field_value << shift; | |
84 | return value; | |
85 | } | |
86 | ||
73505b44 | 87 | static void write_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 88 | { |
62429e03 | 89 | __raw_writeb(set_field(0, data, h), addr); |
02ab3f70 MD |
90 | } |
91 | ||
73505b44 | 92 | static void write_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 93 | { |
62429e03 | 94 | __raw_writew(set_field(0, data, h), addr); |
02ab3f70 MD |
95 | } |
96 | ||
73505b44 | 97 | static void write_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 98 | { |
62429e03 | 99 | __raw_writel(set_field(0, data, h), addr); |
02ab3f70 MD |
100 | } |
101 | ||
73505b44 | 102 | static void modify_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 103 | { |
4370fe1c MD |
104 | unsigned long flags; |
105 | local_irq_save(flags); | |
62429e03 | 106 | __raw_writeb(set_field(__raw_readb(addr), data, h), addr); |
4370fe1c | 107 | local_irq_restore(flags); |
02ab3f70 MD |
108 | } |
109 | ||
73505b44 | 110 | static void modify_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 111 | { |
4370fe1c MD |
112 | unsigned long flags; |
113 | local_irq_save(flags); | |
62429e03 | 114 | __raw_writew(set_field(__raw_readw(addr), data, h), addr); |
4370fe1c | 115 | local_irq_restore(flags); |
02ab3f70 MD |
116 | } |
117 | ||
73505b44 | 118 | static void modify_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 119 | { |
4370fe1c MD |
120 | unsigned long flags; |
121 | local_irq_save(flags); | |
62429e03 | 122 | __raw_writel(set_field(__raw_readl(addr), data, h), addr); |
4370fe1c | 123 | local_irq_restore(flags); |
02ab3f70 MD |
124 | } |
125 | ||
73505b44 MD |
126 | enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; |
127 | ||
128 | static void (*intc_reg_fns[])(unsigned long addr, | |
129 | unsigned long h, | |
130 | unsigned long data) = { | |
131 | [REG_FN_WRITE_BASE + 0] = write_8, | |
132 | [REG_FN_WRITE_BASE + 1] = write_16, | |
133 | [REG_FN_WRITE_BASE + 3] = write_32, | |
134 | [REG_FN_MODIFY_BASE + 0] = modify_8, | |
135 | [REG_FN_MODIFY_BASE + 1] = modify_16, | |
136 | [REG_FN_MODIFY_BASE + 3] = modify_32, | |
137 | }; | |
02ab3f70 | 138 | |
73505b44 MD |
139 | enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ |
140 | MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ | |
141 | MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ | |
142 | MODE_PRIO_REG, /* Priority value written to enable interrupt */ | |
143 | MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ | |
144 | }; | |
02ab3f70 | 145 | |
73505b44 MD |
146 | static void intc_mode_field(unsigned long addr, |
147 | unsigned long handle, | |
148 | void (*fn)(unsigned long, | |
149 | unsigned long, | |
150 | unsigned long), | |
151 | unsigned int irq) | |
02ab3f70 | 152 | { |
73505b44 | 153 | fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); |
02ab3f70 MD |
154 | } |
155 | ||
73505b44 MD |
156 | static void intc_mode_zero(unsigned long addr, |
157 | unsigned long handle, | |
158 | void (*fn)(unsigned long, | |
159 | unsigned long, | |
160 | unsigned long), | |
161 | unsigned int irq) | |
51da6426 | 162 | { |
73505b44 | 163 | fn(addr, handle, 0); |
51da6426 MD |
164 | } |
165 | ||
73505b44 MD |
166 | static void intc_mode_prio(unsigned long addr, |
167 | unsigned long handle, | |
168 | void (*fn)(unsigned long, | |
169 | unsigned long, | |
170 | unsigned long), | |
171 | unsigned int irq) | |
51da6426 | 172 | { |
73505b44 | 173 | fn(addr, handle, intc_prio_level[irq]); |
51da6426 MD |
174 | } |
175 | ||
73505b44 MD |
176 | static void (*intc_enable_fns[])(unsigned long addr, |
177 | unsigned long handle, | |
178 | void (*fn)(unsigned long, | |
179 | unsigned long, | |
180 | unsigned long), | |
181 | unsigned int irq) = { | |
182 | [MODE_ENABLE_REG] = intc_mode_field, | |
183 | [MODE_MASK_REG] = intc_mode_zero, | |
184 | [MODE_DUAL_REG] = intc_mode_field, | |
185 | [MODE_PRIO_REG] = intc_mode_prio, | |
186 | [MODE_PCLR_REG] = intc_mode_prio, | |
187 | }; | |
51da6426 | 188 | |
73505b44 MD |
189 | static void (*intc_disable_fns[])(unsigned long addr, |
190 | unsigned long handle, | |
191 | void (*fn)(unsigned long, | |
192 | unsigned long, | |
193 | unsigned long), | |
194 | unsigned int irq) = { | |
195 | [MODE_ENABLE_REG] = intc_mode_zero, | |
196 | [MODE_MASK_REG] = intc_mode_field, | |
197 | [MODE_DUAL_REG] = intc_mode_field, | |
198 | [MODE_PRIO_REG] = intc_mode_zero, | |
199 | [MODE_PCLR_REG] = intc_mode_field, | |
200 | }; | |
51da6426 | 201 | |
73505b44 | 202 | static inline void _intc_enable(unsigned int irq, unsigned long handle) |
51da6426 | 203 | { |
73505b44 | 204 | struct intc_desc_int *d = get_intc_desc(irq); |
f18d533e MD |
205 | unsigned long addr; |
206 | unsigned int cpu; | |
51da6426 | 207 | |
f18d533e MD |
208 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { |
209 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | |
210 | intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ | |
211 | [_INTC_FN(handle)], irq); | |
212 | } | |
51da6426 MD |
213 | } |
214 | ||
02ab3f70 MD |
215 | static void intc_enable(unsigned int irq) |
216 | { | |
73505b44 | 217 | _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); |
02ab3f70 MD |
218 | } |
219 | ||
220 | static void intc_disable(unsigned int irq) | |
221 | { | |
f18d533e | 222 | struct intc_desc_int *d = get_intc_desc(irq); |
73505b44 | 223 | unsigned long handle = (unsigned long) get_irq_chip_data(irq); |
f18d533e MD |
224 | unsigned long addr; |
225 | unsigned int cpu; | |
02ab3f70 | 226 | |
f18d533e MD |
227 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { |
228 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | |
229 | intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ | |
230 | [_INTC_FN(handle)], irq); | |
231 | } | |
02ab3f70 MD |
232 | } |
233 | ||
6bdfb22a | 234 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
235 | static void intc_mask_ack(unsigned int irq) |
236 | { | |
237 | struct intc_desc_int *d = get_intc_desc(irq); | |
238 | unsigned long handle = ack_handle[irq]; | |
239 | unsigned long addr; | |
240 | ||
241 | intc_disable(irq); | |
242 | ||
243 | /* read register and write zero only to the assocaited bit */ | |
244 | ||
245 | if (handle) { | |
246 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
6bdfb22a YS |
247 | switch (_INTC_FN(handle)) { |
248 | case REG_FN_MODIFY_BASE + 0: /* 8bit */ | |
62429e03 PM |
249 | __raw_readb(addr); |
250 | __raw_writeb(0xff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
251 | break; |
252 | case REG_FN_MODIFY_BASE + 1: /* 16bit */ | |
62429e03 PM |
253 | __raw_readw(addr); |
254 | __raw_writew(0xffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
255 | break; |
256 | case REG_FN_MODIFY_BASE + 3: /* 32bit */ | |
62429e03 PM |
257 | __raw_readl(addr); |
258 | __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
259 | break; |
260 | default: | |
261 | BUG(); | |
262 | break; | |
263 | } | |
d58876e2 MD |
264 | } |
265 | } | |
266 | #endif | |
267 | ||
73505b44 MD |
268 | static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, |
269 | unsigned int nr_hp, | |
270 | unsigned int irq) | |
02ab3f70 | 271 | { |
73505b44 MD |
272 | int i; |
273 | ||
3d37d94e MD |
274 | /* this doesn't scale well, but... |
275 | * | |
276 | * this function should only be used for cerain uncommon | |
277 | * operations such as intc_set_priority() and intc_set_sense() | |
278 | * and in those rare cases performance doesn't matter that much. | |
279 | * keeping the memory footprint low is more important. | |
280 | * | |
281 | * one rather simple way to speed this up and still keep the | |
282 | * memory footprint down is to make sure the array is sorted | |
283 | * and then perform a bisect to lookup the irq. | |
284 | */ | |
285 | ||
73505b44 MD |
286 | for (i = 0; i < nr_hp; i++) { |
287 | if ((hp + i)->irq != irq) | |
288 | continue; | |
289 | ||
290 | return hp + i; | |
291 | } | |
02ab3f70 | 292 | |
73505b44 | 293 | return NULL; |
02ab3f70 MD |
294 | } |
295 | ||
73505b44 | 296 | int intc_set_priority(unsigned int irq, unsigned int prio) |
02ab3f70 | 297 | { |
73505b44 MD |
298 | struct intc_desc_int *d = get_intc_desc(irq); |
299 | struct intc_handle_int *ihp; | |
300 | ||
301 | if (!intc_prio_level[irq] || prio <= 1) | |
302 | return -EINVAL; | |
303 | ||
304 | ihp = intc_find_irq(d->prio, d->nr_prio, irq); | |
305 | if (ihp) { | |
3d37d94e | 306 | if (prio >= (1 << _INTC_WIDTH(ihp->handle))) |
73505b44 | 307 | return -EINVAL; |
02ab3f70 | 308 | |
73505b44 MD |
309 | intc_prio_level[irq] = prio; |
310 | ||
311 | /* | |
312 | * only set secondary masking method directly | |
313 | * primary masking method is using intc_prio_level[irq] | |
314 | * priority level will be set during next enable() | |
315 | */ | |
316 | ||
3d37d94e | 317 | if (_INTC_FN(ihp->handle) != REG_FN_ERR) |
73505b44 MD |
318 | _intc_enable(irq, ihp->handle); |
319 | } | |
320 | return 0; | |
02ab3f70 MD |
321 | } |
322 | ||
323 | #define VALID(x) (x | 0x80) | |
324 | ||
325 | static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { | |
326 | [IRQ_TYPE_EDGE_FALLING] = VALID(0), | |
327 | [IRQ_TYPE_EDGE_RISING] = VALID(1), | |
328 | [IRQ_TYPE_LEVEL_LOW] = VALID(2), | |
720be990 MD |
329 | /* SH7706, SH7707 and SH7709 do not support high level triggered */ |
330 | #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ | |
331 | !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ | |
332 | !defined(CONFIG_CPU_SUBTYPE_SH7709) | |
02ab3f70 | 333 | [IRQ_TYPE_LEVEL_HIGH] = VALID(3), |
720be990 | 334 | #endif |
02ab3f70 MD |
335 | }; |
336 | ||
337 | static int intc_set_sense(unsigned int irq, unsigned int type) | |
338 | { | |
73505b44 | 339 | struct intc_desc_int *d = get_intc_desc(irq); |
02ab3f70 | 340 | unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; |
73505b44 MD |
341 | struct intc_handle_int *ihp; |
342 | unsigned long addr; | |
02ab3f70 | 343 | |
73505b44 | 344 | if (!value) |
02ab3f70 MD |
345 | return -EINVAL; |
346 | ||
73505b44 MD |
347 | ihp = intc_find_irq(d->sense, d->nr_sense, irq); |
348 | if (ihp) { | |
f18d533e | 349 | addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); |
73505b44 | 350 | intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); |
02ab3f70 | 351 | } |
73505b44 | 352 | return 0; |
02ab3f70 MD |
353 | } |
354 | ||
73505b44 MD |
355 | static unsigned int __init intc_get_reg(struct intc_desc_int *d, |
356 | unsigned long address) | |
02ab3f70 | 357 | { |
73505b44 | 358 | unsigned int k; |
02ab3f70 | 359 | |
73505b44 MD |
360 | for (k = 0; k < d->nr_reg; k++) { |
361 | if (d->reg[k] == address) | |
362 | return k; | |
51da6426 MD |
363 | } |
364 | ||
365 | BUG(); | |
73505b44 | 366 | return 0; |
51da6426 MD |
367 | } |
368 | ||
73505b44 MD |
369 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
370 | intc_enum enum_id) | |
680c4598 MD |
371 | { |
372 | struct intc_group *g = desc->groups; | |
373 | unsigned int i, j; | |
374 | ||
375 | for (i = 0; g && enum_id && i < desc->nr_groups; i++) { | |
376 | g = desc->groups + i; | |
377 | ||
378 | for (j = 0; g->enum_ids[j]; j++) { | |
379 | if (g->enum_ids[j] != enum_id) | |
380 | continue; | |
381 | ||
382 | return g->enum_id; | |
383 | } | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
02ab3f70 | 389 | static unsigned int __init intc_mask_data(struct intc_desc *desc, |
73505b44 | 390 | struct intc_desc_int *d, |
680c4598 | 391 | intc_enum enum_id, int do_grps) |
02ab3f70 | 392 | { |
680c4598 | 393 | struct intc_mask_reg *mr = desc->mask_regs; |
73505b44 MD |
394 | unsigned int i, j, fn, mode; |
395 | unsigned long reg_e, reg_d; | |
02ab3f70 | 396 | |
680c4598 MD |
397 | for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { |
398 | mr = desc->mask_regs + i; | |
02ab3f70 MD |
399 | |
400 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
401 | if (mr->enum_ids[j] != enum_id) | |
402 | continue; | |
403 | ||
73505b44 MD |
404 | if (mr->set_reg && mr->clr_reg) { |
405 | fn = REG_FN_WRITE_BASE; | |
406 | mode = MODE_DUAL_REG; | |
407 | reg_e = mr->clr_reg; | |
408 | reg_d = mr->set_reg; | |
409 | } else { | |
410 | fn = REG_FN_MODIFY_BASE; | |
411 | if (mr->set_reg) { | |
412 | mode = MODE_ENABLE_REG; | |
413 | reg_e = mr->set_reg; | |
414 | reg_d = mr->set_reg; | |
415 | } else { | |
416 | mode = MODE_MASK_REG; | |
417 | reg_e = mr->clr_reg; | |
418 | reg_d = mr->clr_reg; | |
419 | } | |
51da6426 MD |
420 | } |
421 | ||
73505b44 MD |
422 | fn += (mr->reg_width >> 3) - 1; |
423 | return _INTC_MK(fn, mode, | |
424 | intc_get_reg(d, reg_e), | |
425 | intc_get_reg(d, reg_d), | |
426 | 1, | |
427 | (mr->reg_width - 1) - j); | |
02ab3f70 MD |
428 | } |
429 | } | |
430 | ||
680c4598 | 431 | if (do_grps) |
73505b44 | 432 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
680c4598 | 433 | |
02ab3f70 MD |
434 | return 0; |
435 | } | |
436 | ||
437 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | |
73505b44 | 438 | struct intc_desc_int *d, |
680c4598 | 439 | intc_enum enum_id, int do_grps) |
02ab3f70 | 440 | { |
680c4598 | 441 | struct intc_prio_reg *pr = desc->prio_regs; |
73505b44 MD |
442 | unsigned int i, j, fn, mode, bit; |
443 | unsigned long reg_e, reg_d; | |
02ab3f70 | 444 | |
680c4598 MD |
445 | for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { |
446 | pr = desc->prio_regs + i; | |
02ab3f70 MD |
447 | |
448 | for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { | |
449 | if (pr->enum_ids[j] != enum_id) | |
450 | continue; | |
451 | ||
73505b44 MD |
452 | if (pr->set_reg && pr->clr_reg) { |
453 | fn = REG_FN_WRITE_BASE; | |
454 | mode = MODE_PCLR_REG; | |
455 | reg_e = pr->set_reg; | |
456 | reg_d = pr->clr_reg; | |
457 | } else { | |
458 | fn = REG_FN_MODIFY_BASE; | |
459 | mode = MODE_PRIO_REG; | |
460 | if (!pr->set_reg) | |
461 | BUG(); | |
462 | reg_e = pr->set_reg; | |
463 | reg_d = pr->set_reg; | |
464 | } | |
02ab3f70 | 465 | |
73505b44 | 466 | fn += (pr->reg_width >> 3) - 1; |
02ab3f70 | 467 | |
b21a9104 | 468 | BUG_ON((j + 1) * pr->field_width > pr->reg_width); |
469 | ||
470 | bit = pr->reg_width - ((j + 1) * pr->field_width); | |
02ab3f70 | 471 | |
73505b44 MD |
472 | return _INTC_MK(fn, mode, |
473 | intc_get_reg(d, reg_e), | |
474 | intc_get_reg(d, reg_d), | |
475 | pr->field_width, bit); | |
02ab3f70 MD |
476 | } |
477 | } | |
478 | ||
680c4598 | 479 | if (do_grps) |
73505b44 MD |
480 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
6bdfb22a | 485 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
486 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
487 | struct intc_desc_int *d, | |
488 | intc_enum enum_id) | |
489 | { | |
490 | struct intc_mask_reg *mr = desc->ack_regs; | |
491 | unsigned int i, j, fn, mode; | |
492 | unsigned long reg_e, reg_d; | |
493 | ||
494 | for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { | |
495 | mr = desc->ack_regs + i; | |
496 | ||
497 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
498 | if (mr->enum_ids[j] != enum_id) | |
499 | continue; | |
500 | ||
501 | fn = REG_FN_MODIFY_BASE; | |
502 | mode = MODE_ENABLE_REG; | |
503 | reg_e = mr->set_reg; | |
504 | reg_d = mr->set_reg; | |
505 | ||
506 | fn += (mr->reg_width >> 3) - 1; | |
507 | return _INTC_MK(fn, mode, | |
508 | intc_get_reg(d, reg_e), | |
509 | intc_get_reg(d, reg_d), | |
510 | 1, | |
511 | (mr->reg_width - 1) - j); | |
512 | } | |
513 | } | |
514 | ||
515 | return 0; | |
516 | } | |
517 | #endif | |
518 | ||
73505b44 MD |
519 | static unsigned int __init intc_sense_data(struct intc_desc *desc, |
520 | struct intc_desc_int *d, | |
521 | intc_enum enum_id) | |
522 | { | |
523 | struct intc_sense_reg *sr = desc->sense_regs; | |
524 | unsigned int i, j, fn, bit; | |
525 | ||
526 | for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { | |
527 | sr = desc->sense_regs + i; | |
528 | ||
529 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | |
530 | if (sr->enum_ids[j] != enum_id) | |
531 | continue; | |
532 | ||
533 | fn = REG_FN_MODIFY_BASE; | |
534 | fn += (sr->reg_width >> 3) - 1; | |
73505b44 | 535 | |
b21a9104 | 536 | BUG_ON((j + 1) * sr->field_width > sr->reg_width); |
537 | ||
538 | bit = sr->reg_width - ((j + 1) * sr->field_width); | |
73505b44 MD |
539 | |
540 | return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), | |
541 | 0, sr->field_width, bit); | |
542 | } | |
543 | } | |
680c4598 | 544 | |
02ab3f70 MD |
545 | return 0; |
546 | } | |
547 | ||
73505b44 MD |
548 | static void __init intc_register_irq(struct intc_desc *desc, |
549 | struct intc_desc_int *d, | |
550 | intc_enum enum_id, | |
02ab3f70 MD |
551 | unsigned int irq) |
552 | { | |
3d37d94e | 553 | struct intc_handle_int *hp; |
680c4598 MD |
554 | unsigned int data[2], primary; |
555 | ||
556 | /* Prefer single interrupt source bitmap over other combinations: | |
557 | * 1. bitmap, single interrupt source | |
558 | * 2. priority, single interrupt source | |
559 | * 3. bitmap, multiple interrupt sources (groups) | |
560 | * 4. priority, multiple interrupt sources (groups) | |
561 | */ | |
02ab3f70 | 562 | |
73505b44 MD |
563 | data[0] = intc_mask_data(desc, d, enum_id, 0); |
564 | data[1] = intc_prio_data(desc, d, enum_id, 0); | |
680c4598 MD |
565 | |
566 | primary = 0; | |
567 | if (!data[0] && data[1]) | |
568 | primary = 1; | |
569 | ||
73505b44 MD |
570 | data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); |
571 | data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); | |
680c4598 MD |
572 | |
573 | if (!data[primary]) | |
574 | primary ^= 1; | |
575 | ||
576 | BUG_ON(!data[primary]); /* must have primary masking method */ | |
02ab3f70 MD |
577 | |
578 | disable_irq_nosync(irq); | |
73505b44 | 579 | set_irq_chip_and_handler_name(irq, &d->chip, |
02ab3f70 | 580 | handle_level_irq, "level"); |
680c4598 | 581 | set_irq_chip_data(irq, (void *)data[primary]); |
02ab3f70 | 582 | |
7f3edee8 MD |
583 | /* set priority level |
584 | * - this needs to be at least 2 for 5-bit priorities on 7780 | |
585 | */ | |
586 | intc_prio_level[irq] = 2; | |
73505b44 | 587 | |
680c4598 MD |
588 | /* enable secondary masking method if present */ |
589 | if (data[!primary]) | |
73505b44 MD |
590 | _intc_enable(irq, data[!primary]); |
591 | ||
592 | /* add irq to d->prio list if priority is available */ | |
593 | if (data[1]) { | |
3d37d94e MD |
594 | hp = d->prio + d->nr_prio; |
595 | hp->irq = irq; | |
596 | hp->handle = data[1]; | |
597 | ||
598 | if (primary) { | |
599 | /* | |
600 | * only secondary priority should access registers, so | |
601 | * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() | |
602 | */ | |
603 | ||
604 | hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); | |
605 | hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); | |
606 | } | |
73505b44 MD |
607 | d->nr_prio++; |
608 | } | |
609 | ||
610 | /* add irq to d->sense list if sense is available */ | |
611 | data[0] = intc_sense_data(desc, d, enum_id); | |
612 | if (data[0]) { | |
613 | (d->sense + d->nr_sense)->irq = irq; | |
614 | (d->sense + d->nr_sense)->handle = data[0]; | |
615 | d->nr_sense++; | |
616 | } | |
02ab3f70 MD |
617 | |
618 | /* irq should be disabled by default */ | |
73505b44 | 619 | d->chip.mask(irq); |
d58876e2 | 620 | |
6bdfb22a | 621 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
622 | if (desc->ack_regs) |
623 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); | |
624 | #endif | |
02ab3f70 MD |
625 | } |
626 | ||
f18d533e MD |
627 | static unsigned int __init save_reg(struct intc_desc_int *d, |
628 | unsigned int cnt, | |
629 | unsigned long value, | |
630 | unsigned int smp) | |
631 | { | |
632 | if (value) { | |
633 | d->reg[cnt] = value; | |
634 | #ifdef CONFIG_SMP | |
635 | d->smp[cnt] = smp; | |
636 | #endif | |
637 | return 1; | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | ||
02ab3f70 MD |
644 | void __init register_intc_controller(struct intc_desc *desc) |
645 | { | |
f18d533e | 646 | unsigned int i, k, smp; |
73505b44 MD |
647 | struct intc_desc_int *d; |
648 | ||
649 | d = alloc_bootmem(sizeof(*d)); | |
650 | ||
651 | d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; | |
652 | d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; | |
653 | d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; | |
654 | ||
6bdfb22a | 655 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
656 | d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; |
657 | #endif | |
73505b44 | 658 | d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg)); |
f18d533e MD |
659 | #ifdef CONFIG_SMP |
660 | d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp)); | |
661 | #endif | |
73505b44 MD |
662 | k = 0; |
663 | ||
664 | if (desc->mask_regs) { | |
665 | for (i = 0; i < desc->nr_mask_regs; i++) { | |
f18d533e MD |
666 | smp = IS_SMP(desc->mask_regs[i]); |
667 | k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); | |
668 | k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); | |
73505b44 MD |
669 | } |
670 | } | |
671 | ||
672 | if (desc->prio_regs) { | |
673 | d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio)); | |
674 | ||
675 | for (i = 0; i < desc->nr_prio_regs; i++) { | |
f18d533e MD |
676 | smp = IS_SMP(desc->prio_regs[i]); |
677 | k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); | |
678 | k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); | |
73505b44 MD |
679 | } |
680 | } | |
681 | ||
682 | if (desc->sense_regs) { | |
683 | d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense)); | |
684 | ||
685 | for (i = 0; i < desc->nr_sense_regs; i++) { | |
f18d533e | 686 | k += save_reg(d, k, desc->sense_regs[i].reg, 0); |
73505b44 MD |
687 | } |
688 | } | |
689 | ||
73505b44 MD |
690 | d->chip.name = desc->name; |
691 | d->chip.mask = intc_disable; | |
692 | d->chip.unmask = intc_enable; | |
693 | d->chip.mask_ack = intc_disable; | |
694 | d->chip.set_type = intc_set_sense; | |
02ab3f70 | 695 | |
6bdfb22a | 696 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
d58876e2 MD |
697 | if (desc->ack_regs) { |
698 | for (i = 0; i < desc->nr_ack_regs; i++) | |
699 | k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); | |
700 | ||
701 | d->chip.mask_ack = intc_mask_ack; | |
702 | } | |
703 | #endif | |
704 | ||
705 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ | |
706 | ||
02ab3f70 MD |
707 | for (i = 0; i < desc->nr_vectors; i++) { |
708 | struct intc_vect *vect = desc->vectors + i; | |
709 | ||
73505b44 | 710 | intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); |
02ab3f70 MD |
711 | } |
712 | } |