Commit | Line | Data |
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02ab3f70 MD |
1 | /* |
2 | * Shared interrupt handling code for IPR and INTC2 types of IRQs. | |
3 | * | |
d58876e2 | 4 | * Copyright (C) 2007, 2008 Magnus Damm |
02ab3f70 MD |
5 | * |
6 | * Based on intc2.c and ipr.c | |
7 | * | |
8 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
9 | * Copyright (C) 2000 Kazumoto Kojima | |
10 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | |
11 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | |
12 | * Copyright (C) 2005, 2006 Paul Mundt | |
13 | * | |
14 | * This file is subject to the terms and conditions of the GNU General Public | |
15 | * License. See the file "COPYING" in the main directory of this archive | |
16 | * for more details. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/interrupt.h> | |
73505b44 MD |
23 | #include <linux/bootmem.h> |
24 | ||
25 | #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ | |
26 | ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ | |
27 | ((addr_e) << 16) | ((addr_d << 24))) | |
28 | ||
29 | #define _INTC_SHIFT(h) (h & 0x1f) | |
30 | #define _INTC_WIDTH(h) ((h >> 5) & 0xf) | |
31 | #define _INTC_FN(h) ((h >> 9) & 0xf) | |
32 | #define _INTC_MODE(h) ((h >> 13) & 0x7) | |
33 | #define _INTC_ADDR_E(h) ((h >> 16) & 0xff) | |
34 | #define _INTC_ADDR_D(h) ((h >> 24) & 0xff) | |
35 | ||
36 | struct intc_handle_int { | |
37 | unsigned int irq; | |
38 | unsigned long handle; | |
39 | }; | |
02ab3f70 | 40 | |
73505b44 MD |
41 | struct intc_desc_int { |
42 | unsigned long *reg; | |
f18d533e MD |
43 | #ifdef CONFIG_SMP |
44 | unsigned long *smp; | |
45 | #endif | |
73505b44 MD |
46 | unsigned int nr_reg; |
47 | struct intc_handle_int *prio; | |
48 | unsigned int nr_prio; | |
49 | struct intc_handle_int *sense; | |
50 | unsigned int nr_sense; | |
51 | struct irq_chip chip; | |
52 | }; | |
02ab3f70 | 53 | |
f18d533e MD |
54 | #ifdef CONFIG_SMP |
55 | #define IS_SMP(x) x.smp | |
56 | #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) | |
57 | #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) | |
58 | #else | |
59 | #define IS_SMP(x) 0 | |
60 | #define INTC_REG(d, x, c) (d->reg[(x)]) | |
61 | #define SMP_NR(d, x) 1 | |
62 | #endif | |
63 | ||
73505b44 | 64 | static unsigned int intc_prio_level[NR_IRQS]; /* for now */ |
d58876e2 MD |
65 | #ifdef CONFIG_CPU_SH3 |
66 | static unsigned long ack_handle[NR_IRQS]; | |
67 | #endif | |
02ab3f70 | 68 | |
73505b44 | 69 | static inline struct intc_desc_int *get_intc_desc(unsigned int irq) |
02ab3f70 MD |
70 | { |
71 | struct irq_chip *chip = get_irq_chip(irq); | |
73505b44 | 72 | return (void *)((char *)chip - offsetof(struct intc_desc_int, chip)); |
02ab3f70 MD |
73 | } |
74 | ||
75 | static inline unsigned int set_field(unsigned int value, | |
76 | unsigned int field_value, | |
73505b44 | 77 | unsigned int handle) |
02ab3f70 | 78 | { |
73505b44 MD |
79 | unsigned int width = _INTC_WIDTH(handle); |
80 | unsigned int shift = _INTC_SHIFT(handle); | |
81 | ||
02ab3f70 MD |
82 | value &= ~(((1 << width) - 1) << shift); |
83 | value |= field_value << shift; | |
84 | return value; | |
85 | } | |
86 | ||
73505b44 | 87 | static void write_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 88 | { |
73505b44 | 89 | ctrl_outb(set_field(0, data, h), addr); |
02ab3f70 MD |
90 | } |
91 | ||
73505b44 | 92 | static void write_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 93 | { |
73505b44 | 94 | ctrl_outw(set_field(0, data, h), addr); |
02ab3f70 MD |
95 | } |
96 | ||
73505b44 | 97 | static void write_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 98 | { |
73505b44 | 99 | ctrl_outl(set_field(0, data, h), addr); |
02ab3f70 MD |
100 | } |
101 | ||
73505b44 | 102 | static void modify_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 103 | { |
4370fe1c MD |
104 | unsigned long flags; |
105 | local_irq_save(flags); | |
73505b44 | 106 | ctrl_outb(set_field(ctrl_inb(addr), data, h), addr); |
4370fe1c | 107 | local_irq_restore(flags); |
02ab3f70 MD |
108 | } |
109 | ||
73505b44 | 110 | static void modify_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 111 | { |
4370fe1c MD |
112 | unsigned long flags; |
113 | local_irq_save(flags); | |
73505b44 | 114 | ctrl_outw(set_field(ctrl_inw(addr), data, h), addr); |
4370fe1c | 115 | local_irq_restore(flags); |
02ab3f70 MD |
116 | } |
117 | ||
73505b44 | 118 | static void modify_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 119 | { |
4370fe1c MD |
120 | unsigned long flags; |
121 | local_irq_save(flags); | |
73505b44 | 122 | ctrl_outl(set_field(ctrl_inl(addr), data, h), addr); |
4370fe1c | 123 | local_irq_restore(flags); |
02ab3f70 MD |
124 | } |
125 | ||
73505b44 MD |
126 | enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; |
127 | ||
128 | static void (*intc_reg_fns[])(unsigned long addr, | |
129 | unsigned long h, | |
130 | unsigned long data) = { | |
131 | [REG_FN_WRITE_BASE + 0] = write_8, | |
132 | [REG_FN_WRITE_BASE + 1] = write_16, | |
133 | [REG_FN_WRITE_BASE + 3] = write_32, | |
134 | [REG_FN_MODIFY_BASE + 0] = modify_8, | |
135 | [REG_FN_MODIFY_BASE + 1] = modify_16, | |
136 | [REG_FN_MODIFY_BASE + 3] = modify_32, | |
137 | }; | |
02ab3f70 | 138 | |
73505b44 MD |
139 | enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ |
140 | MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ | |
141 | MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ | |
142 | MODE_PRIO_REG, /* Priority value written to enable interrupt */ | |
143 | MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ | |
144 | }; | |
02ab3f70 | 145 | |
73505b44 MD |
146 | static void intc_mode_field(unsigned long addr, |
147 | unsigned long handle, | |
148 | void (*fn)(unsigned long, | |
149 | unsigned long, | |
150 | unsigned long), | |
151 | unsigned int irq) | |
02ab3f70 | 152 | { |
73505b44 | 153 | fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); |
02ab3f70 MD |
154 | } |
155 | ||
73505b44 MD |
156 | static void intc_mode_zero(unsigned long addr, |
157 | unsigned long handle, | |
158 | void (*fn)(unsigned long, | |
159 | unsigned long, | |
160 | unsigned long), | |
161 | unsigned int irq) | |
51da6426 | 162 | { |
73505b44 | 163 | fn(addr, handle, 0); |
51da6426 MD |
164 | } |
165 | ||
73505b44 MD |
166 | static void intc_mode_prio(unsigned long addr, |
167 | unsigned long handle, | |
168 | void (*fn)(unsigned long, | |
169 | unsigned long, | |
170 | unsigned long), | |
171 | unsigned int irq) | |
51da6426 | 172 | { |
73505b44 | 173 | fn(addr, handle, intc_prio_level[irq]); |
51da6426 MD |
174 | } |
175 | ||
73505b44 MD |
176 | static void (*intc_enable_fns[])(unsigned long addr, |
177 | unsigned long handle, | |
178 | void (*fn)(unsigned long, | |
179 | unsigned long, | |
180 | unsigned long), | |
181 | unsigned int irq) = { | |
182 | [MODE_ENABLE_REG] = intc_mode_field, | |
183 | [MODE_MASK_REG] = intc_mode_zero, | |
184 | [MODE_DUAL_REG] = intc_mode_field, | |
185 | [MODE_PRIO_REG] = intc_mode_prio, | |
186 | [MODE_PCLR_REG] = intc_mode_prio, | |
187 | }; | |
51da6426 | 188 | |
73505b44 MD |
189 | static void (*intc_disable_fns[])(unsigned long addr, |
190 | unsigned long handle, | |
191 | void (*fn)(unsigned long, | |
192 | unsigned long, | |
193 | unsigned long), | |
194 | unsigned int irq) = { | |
195 | [MODE_ENABLE_REG] = intc_mode_zero, | |
196 | [MODE_MASK_REG] = intc_mode_field, | |
197 | [MODE_DUAL_REG] = intc_mode_field, | |
198 | [MODE_PRIO_REG] = intc_mode_zero, | |
199 | [MODE_PCLR_REG] = intc_mode_field, | |
200 | }; | |
51da6426 | 201 | |
73505b44 | 202 | static inline void _intc_enable(unsigned int irq, unsigned long handle) |
51da6426 | 203 | { |
73505b44 | 204 | struct intc_desc_int *d = get_intc_desc(irq); |
f18d533e MD |
205 | unsigned long addr; |
206 | unsigned int cpu; | |
51da6426 | 207 | |
f18d533e MD |
208 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { |
209 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | |
210 | intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ | |
211 | [_INTC_FN(handle)], irq); | |
212 | } | |
51da6426 MD |
213 | } |
214 | ||
02ab3f70 MD |
215 | static void intc_enable(unsigned int irq) |
216 | { | |
73505b44 | 217 | _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); |
02ab3f70 MD |
218 | } |
219 | ||
220 | static void intc_disable(unsigned int irq) | |
221 | { | |
f18d533e | 222 | struct intc_desc_int *d = get_intc_desc(irq); |
73505b44 | 223 | unsigned long handle = (unsigned long) get_irq_chip_data(irq); |
f18d533e MD |
224 | unsigned long addr; |
225 | unsigned int cpu; | |
02ab3f70 | 226 | |
f18d533e MD |
227 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { |
228 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | |
229 | intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ | |
230 | [_INTC_FN(handle)], irq); | |
231 | } | |
02ab3f70 MD |
232 | } |
233 | ||
d58876e2 MD |
234 | #ifdef CONFIG_CPU_SH3 |
235 | static void intc_mask_ack(unsigned int irq) | |
236 | { | |
237 | struct intc_desc_int *d = get_intc_desc(irq); | |
238 | unsigned long handle = ack_handle[irq]; | |
239 | unsigned long addr; | |
240 | ||
241 | intc_disable(irq); | |
242 | ||
243 | /* read register and write zero only to the assocaited bit */ | |
244 | ||
245 | if (handle) { | |
246 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
247 | ctrl_inb(addr); | |
248 | ctrl_outb(0x3f ^ set_field(0, 1, handle), addr); | |
249 | } | |
250 | } | |
251 | #endif | |
252 | ||
73505b44 MD |
253 | static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, |
254 | unsigned int nr_hp, | |
255 | unsigned int irq) | |
02ab3f70 | 256 | { |
73505b44 MD |
257 | int i; |
258 | ||
3d37d94e MD |
259 | /* this doesn't scale well, but... |
260 | * | |
261 | * this function should only be used for cerain uncommon | |
262 | * operations such as intc_set_priority() and intc_set_sense() | |
263 | * and in those rare cases performance doesn't matter that much. | |
264 | * keeping the memory footprint low is more important. | |
265 | * | |
266 | * one rather simple way to speed this up and still keep the | |
267 | * memory footprint down is to make sure the array is sorted | |
268 | * and then perform a bisect to lookup the irq. | |
269 | */ | |
270 | ||
73505b44 MD |
271 | for (i = 0; i < nr_hp; i++) { |
272 | if ((hp + i)->irq != irq) | |
273 | continue; | |
274 | ||
275 | return hp + i; | |
276 | } | |
02ab3f70 | 277 | |
73505b44 | 278 | return NULL; |
02ab3f70 MD |
279 | } |
280 | ||
73505b44 | 281 | int intc_set_priority(unsigned int irq, unsigned int prio) |
02ab3f70 | 282 | { |
73505b44 MD |
283 | struct intc_desc_int *d = get_intc_desc(irq); |
284 | struct intc_handle_int *ihp; | |
285 | ||
286 | if (!intc_prio_level[irq] || prio <= 1) | |
287 | return -EINVAL; | |
288 | ||
289 | ihp = intc_find_irq(d->prio, d->nr_prio, irq); | |
290 | if (ihp) { | |
3d37d94e | 291 | if (prio >= (1 << _INTC_WIDTH(ihp->handle))) |
73505b44 | 292 | return -EINVAL; |
02ab3f70 | 293 | |
73505b44 MD |
294 | intc_prio_level[irq] = prio; |
295 | ||
296 | /* | |
297 | * only set secondary masking method directly | |
298 | * primary masking method is using intc_prio_level[irq] | |
299 | * priority level will be set during next enable() | |
300 | */ | |
301 | ||
3d37d94e | 302 | if (_INTC_FN(ihp->handle) != REG_FN_ERR) |
73505b44 MD |
303 | _intc_enable(irq, ihp->handle); |
304 | } | |
305 | return 0; | |
02ab3f70 MD |
306 | } |
307 | ||
308 | #define VALID(x) (x | 0x80) | |
309 | ||
310 | static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { | |
311 | [IRQ_TYPE_EDGE_FALLING] = VALID(0), | |
312 | [IRQ_TYPE_EDGE_RISING] = VALID(1), | |
313 | [IRQ_TYPE_LEVEL_LOW] = VALID(2), | |
720be990 MD |
314 | /* SH7706, SH7707 and SH7709 do not support high level triggered */ |
315 | #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ | |
316 | !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ | |
317 | !defined(CONFIG_CPU_SUBTYPE_SH7709) | |
02ab3f70 | 318 | [IRQ_TYPE_LEVEL_HIGH] = VALID(3), |
720be990 | 319 | #endif |
02ab3f70 MD |
320 | }; |
321 | ||
322 | static int intc_set_sense(unsigned int irq, unsigned int type) | |
323 | { | |
73505b44 | 324 | struct intc_desc_int *d = get_intc_desc(irq); |
02ab3f70 | 325 | unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; |
73505b44 MD |
326 | struct intc_handle_int *ihp; |
327 | unsigned long addr; | |
02ab3f70 | 328 | |
73505b44 | 329 | if (!value) |
02ab3f70 MD |
330 | return -EINVAL; |
331 | ||
73505b44 MD |
332 | ihp = intc_find_irq(d->sense, d->nr_sense, irq); |
333 | if (ihp) { | |
f18d533e | 334 | addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); |
73505b44 | 335 | intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); |
02ab3f70 | 336 | } |
73505b44 | 337 | return 0; |
02ab3f70 MD |
338 | } |
339 | ||
73505b44 MD |
340 | static unsigned int __init intc_get_reg(struct intc_desc_int *d, |
341 | unsigned long address) | |
02ab3f70 | 342 | { |
73505b44 | 343 | unsigned int k; |
02ab3f70 | 344 | |
73505b44 MD |
345 | for (k = 0; k < d->nr_reg; k++) { |
346 | if (d->reg[k] == address) | |
347 | return k; | |
51da6426 MD |
348 | } |
349 | ||
350 | BUG(); | |
73505b44 | 351 | return 0; |
51da6426 MD |
352 | } |
353 | ||
73505b44 MD |
354 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
355 | intc_enum enum_id) | |
680c4598 MD |
356 | { |
357 | struct intc_group *g = desc->groups; | |
358 | unsigned int i, j; | |
359 | ||
360 | for (i = 0; g && enum_id && i < desc->nr_groups; i++) { | |
361 | g = desc->groups + i; | |
362 | ||
363 | for (j = 0; g->enum_ids[j]; j++) { | |
364 | if (g->enum_ids[j] != enum_id) | |
365 | continue; | |
366 | ||
367 | return g->enum_id; | |
368 | } | |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
02ab3f70 | 374 | static unsigned int __init intc_mask_data(struct intc_desc *desc, |
73505b44 | 375 | struct intc_desc_int *d, |
680c4598 | 376 | intc_enum enum_id, int do_grps) |
02ab3f70 | 377 | { |
680c4598 | 378 | struct intc_mask_reg *mr = desc->mask_regs; |
73505b44 MD |
379 | unsigned int i, j, fn, mode; |
380 | unsigned long reg_e, reg_d; | |
02ab3f70 | 381 | |
680c4598 MD |
382 | for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { |
383 | mr = desc->mask_regs + i; | |
02ab3f70 MD |
384 | |
385 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
386 | if (mr->enum_ids[j] != enum_id) | |
387 | continue; | |
388 | ||
73505b44 MD |
389 | if (mr->set_reg && mr->clr_reg) { |
390 | fn = REG_FN_WRITE_BASE; | |
391 | mode = MODE_DUAL_REG; | |
392 | reg_e = mr->clr_reg; | |
393 | reg_d = mr->set_reg; | |
394 | } else { | |
395 | fn = REG_FN_MODIFY_BASE; | |
396 | if (mr->set_reg) { | |
397 | mode = MODE_ENABLE_REG; | |
398 | reg_e = mr->set_reg; | |
399 | reg_d = mr->set_reg; | |
400 | } else { | |
401 | mode = MODE_MASK_REG; | |
402 | reg_e = mr->clr_reg; | |
403 | reg_d = mr->clr_reg; | |
404 | } | |
51da6426 MD |
405 | } |
406 | ||
73505b44 MD |
407 | fn += (mr->reg_width >> 3) - 1; |
408 | return _INTC_MK(fn, mode, | |
409 | intc_get_reg(d, reg_e), | |
410 | intc_get_reg(d, reg_d), | |
411 | 1, | |
412 | (mr->reg_width - 1) - j); | |
02ab3f70 MD |
413 | } |
414 | } | |
415 | ||
680c4598 | 416 | if (do_grps) |
73505b44 | 417 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
680c4598 | 418 | |
02ab3f70 MD |
419 | return 0; |
420 | } | |
421 | ||
422 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | |
73505b44 | 423 | struct intc_desc_int *d, |
680c4598 | 424 | intc_enum enum_id, int do_grps) |
02ab3f70 | 425 | { |
680c4598 | 426 | struct intc_prio_reg *pr = desc->prio_regs; |
73505b44 MD |
427 | unsigned int i, j, fn, mode, bit; |
428 | unsigned long reg_e, reg_d; | |
02ab3f70 | 429 | |
680c4598 MD |
430 | for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { |
431 | pr = desc->prio_regs + i; | |
02ab3f70 MD |
432 | |
433 | for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { | |
434 | if (pr->enum_ids[j] != enum_id) | |
435 | continue; | |
436 | ||
73505b44 MD |
437 | if (pr->set_reg && pr->clr_reg) { |
438 | fn = REG_FN_WRITE_BASE; | |
439 | mode = MODE_PCLR_REG; | |
440 | reg_e = pr->set_reg; | |
441 | reg_d = pr->clr_reg; | |
442 | } else { | |
443 | fn = REG_FN_MODIFY_BASE; | |
444 | mode = MODE_PRIO_REG; | |
445 | if (!pr->set_reg) | |
446 | BUG(); | |
447 | reg_e = pr->set_reg; | |
448 | reg_d = pr->set_reg; | |
449 | } | |
02ab3f70 | 450 | |
73505b44 | 451 | fn += (pr->reg_width >> 3) - 1; |
02ab3f70 MD |
452 | bit = pr->reg_width - ((j + 1) * pr->field_width); |
453 | ||
454 | BUG_ON(bit < 0); | |
455 | ||
73505b44 MD |
456 | return _INTC_MK(fn, mode, |
457 | intc_get_reg(d, reg_e), | |
458 | intc_get_reg(d, reg_d), | |
459 | pr->field_width, bit); | |
02ab3f70 MD |
460 | } |
461 | } | |
462 | ||
680c4598 | 463 | if (do_grps) |
73505b44 MD |
464 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
d58876e2 MD |
469 | #ifdef CONFIG_CPU_SH3 |
470 | static unsigned int __init intc_ack_data(struct intc_desc *desc, | |
471 | struct intc_desc_int *d, | |
472 | intc_enum enum_id) | |
473 | { | |
474 | struct intc_mask_reg *mr = desc->ack_regs; | |
475 | unsigned int i, j, fn, mode; | |
476 | unsigned long reg_e, reg_d; | |
477 | ||
478 | for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { | |
479 | mr = desc->ack_regs + i; | |
480 | ||
481 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
482 | if (mr->enum_ids[j] != enum_id) | |
483 | continue; | |
484 | ||
485 | fn = REG_FN_MODIFY_BASE; | |
486 | mode = MODE_ENABLE_REG; | |
487 | reg_e = mr->set_reg; | |
488 | reg_d = mr->set_reg; | |
489 | ||
490 | fn += (mr->reg_width >> 3) - 1; | |
491 | return _INTC_MK(fn, mode, | |
492 | intc_get_reg(d, reg_e), | |
493 | intc_get_reg(d, reg_d), | |
494 | 1, | |
495 | (mr->reg_width - 1) - j); | |
496 | } | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | #endif | |
502 | ||
73505b44 MD |
503 | static unsigned int __init intc_sense_data(struct intc_desc *desc, |
504 | struct intc_desc_int *d, | |
505 | intc_enum enum_id) | |
506 | { | |
507 | struct intc_sense_reg *sr = desc->sense_regs; | |
508 | unsigned int i, j, fn, bit; | |
509 | ||
510 | for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { | |
511 | sr = desc->sense_regs + i; | |
512 | ||
513 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | |
514 | if (sr->enum_ids[j] != enum_id) | |
515 | continue; | |
516 | ||
517 | fn = REG_FN_MODIFY_BASE; | |
518 | fn += (sr->reg_width >> 3) - 1; | |
519 | bit = sr->reg_width - ((j + 1) * sr->field_width); | |
520 | ||
521 | BUG_ON(bit < 0); | |
522 | ||
523 | return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), | |
524 | 0, sr->field_width, bit); | |
525 | } | |
526 | } | |
680c4598 | 527 | |
02ab3f70 MD |
528 | return 0; |
529 | } | |
530 | ||
73505b44 MD |
531 | static void __init intc_register_irq(struct intc_desc *desc, |
532 | struct intc_desc_int *d, | |
533 | intc_enum enum_id, | |
02ab3f70 MD |
534 | unsigned int irq) |
535 | { | |
3d37d94e | 536 | struct intc_handle_int *hp; |
680c4598 MD |
537 | unsigned int data[2], primary; |
538 | ||
539 | /* Prefer single interrupt source bitmap over other combinations: | |
540 | * 1. bitmap, single interrupt source | |
541 | * 2. priority, single interrupt source | |
542 | * 3. bitmap, multiple interrupt sources (groups) | |
543 | * 4. priority, multiple interrupt sources (groups) | |
544 | */ | |
02ab3f70 | 545 | |
73505b44 MD |
546 | data[0] = intc_mask_data(desc, d, enum_id, 0); |
547 | data[1] = intc_prio_data(desc, d, enum_id, 0); | |
680c4598 MD |
548 | |
549 | primary = 0; | |
550 | if (!data[0] && data[1]) | |
551 | primary = 1; | |
552 | ||
73505b44 MD |
553 | data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); |
554 | data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); | |
680c4598 MD |
555 | |
556 | if (!data[primary]) | |
557 | primary ^= 1; | |
558 | ||
559 | BUG_ON(!data[primary]); /* must have primary masking method */ | |
02ab3f70 MD |
560 | |
561 | disable_irq_nosync(irq); | |
73505b44 | 562 | set_irq_chip_and_handler_name(irq, &d->chip, |
02ab3f70 | 563 | handle_level_irq, "level"); |
680c4598 | 564 | set_irq_chip_data(irq, (void *)data[primary]); |
02ab3f70 | 565 | |
7f3edee8 MD |
566 | /* set priority level |
567 | * - this needs to be at least 2 for 5-bit priorities on 7780 | |
568 | */ | |
569 | intc_prio_level[irq] = 2; | |
73505b44 | 570 | |
680c4598 MD |
571 | /* enable secondary masking method if present */ |
572 | if (data[!primary]) | |
73505b44 MD |
573 | _intc_enable(irq, data[!primary]); |
574 | ||
575 | /* add irq to d->prio list if priority is available */ | |
576 | if (data[1]) { | |
3d37d94e MD |
577 | hp = d->prio + d->nr_prio; |
578 | hp->irq = irq; | |
579 | hp->handle = data[1]; | |
580 | ||
581 | if (primary) { | |
582 | /* | |
583 | * only secondary priority should access registers, so | |
584 | * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() | |
585 | */ | |
586 | ||
587 | hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); | |
588 | hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); | |
589 | } | |
73505b44 MD |
590 | d->nr_prio++; |
591 | } | |
592 | ||
593 | /* add irq to d->sense list if sense is available */ | |
594 | data[0] = intc_sense_data(desc, d, enum_id); | |
595 | if (data[0]) { | |
596 | (d->sense + d->nr_sense)->irq = irq; | |
597 | (d->sense + d->nr_sense)->handle = data[0]; | |
598 | d->nr_sense++; | |
599 | } | |
02ab3f70 MD |
600 | |
601 | /* irq should be disabled by default */ | |
73505b44 | 602 | d->chip.mask(irq); |
d58876e2 MD |
603 | |
604 | #ifdef CONFIG_CPU_SH3 | |
605 | if (desc->ack_regs) | |
606 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); | |
607 | #endif | |
02ab3f70 MD |
608 | } |
609 | ||
f18d533e MD |
610 | static unsigned int __init save_reg(struct intc_desc_int *d, |
611 | unsigned int cnt, | |
612 | unsigned long value, | |
613 | unsigned int smp) | |
614 | { | |
615 | if (value) { | |
616 | d->reg[cnt] = value; | |
617 | #ifdef CONFIG_SMP | |
618 | d->smp[cnt] = smp; | |
619 | #endif | |
620 | return 1; | |
621 | } | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | ||
02ab3f70 MD |
627 | void __init register_intc_controller(struct intc_desc *desc) |
628 | { | |
f18d533e | 629 | unsigned int i, k, smp; |
73505b44 MD |
630 | struct intc_desc_int *d; |
631 | ||
632 | d = alloc_bootmem(sizeof(*d)); | |
633 | ||
634 | d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; | |
635 | d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; | |
636 | d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; | |
637 | ||
d58876e2 MD |
638 | #ifdef CONFIG_CPU_SH3 |
639 | d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; | |
640 | #endif | |
73505b44 | 641 | d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg)); |
f18d533e MD |
642 | #ifdef CONFIG_SMP |
643 | d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp)); | |
644 | #endif | |
73505b44 MD |
645 | k = 0; |
646 | ||
647 | if (desc->mask_regs) { | |
648 | for (i = 0; i < desc->nr_mask_regs; i++) { | |
f18d533e MD |
649 | smp = IS_SMP(desc->mask_regs[i]); |
650 | k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); | |
651 | k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); | |
73505b44 MD |
652 | } |
653 | } | |
654 | ||
655 | if (desc->prio_regs) { | |
656 | d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio)); | |
657 | ||
658 | for (i = 0; i < desc->nr_prio_regs; i++) { | |
f18d533e MD |
659 | smp = IS_SMP(desc->prio_regs[i]); |
660 | k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); | |
661 | k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); | |
73505b44 MD |
662 | } |
663 | } | |
664 | ||
665 | if (desc->sense_regs) { | |
666 | d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense)); | |
667 | ||
668 | for (i = 0; i < desc->nr_sense_regs; i++) { | |
f18d533e | 669 | k += save_reg(d, k, desc->sense_regs[i].reg, 0); |
73505b44 MD |
670 | } |
671 | } | |
672 | ||
73505b44 MD |
673 | d->chip.name = desc->name; |
674 | d->chip.mask = intc_disable; | |
675 | d->chip.unmask = intc_enable; | |
676 | d->chip.mask_ack = intc_disable; | |
677 | d->chip.set_type = intc_set_sense; | |
02ab3f70 | 678 | |
d58876e2 MD |
679 | #ifdef CONFIG_CPU_SH3 |
680 | if (desc->ack_regs) { | |
681 | for (i = 0; i < desc->nr_ack_regs; i++) | |
682 | k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); | |
683 | ||
684 | d->chip.mask_ack = intc_mask_ack; | |
685 | } | |
686 | #endif | |
687 | ||
688 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ | |
689 | ||
02ab3f70 MD |
690 | for (i = 0; i < desc->nr_vectors; i++) { |
691 | struct intc_vect *vect = desc->vectors + i; | |
692 | ||
73505b44 | 693 | intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); |
02ab3f70 MD |
694 | } |
695 | } |