[deliverable/linux.git] / arch / sh / kernel / cpu / sh2 / entry.S

/*
 * arch/sh/kernel/cpu/sh2/entry.S
 *
 * The SH-2 exception entry
 *
 * Copyright (C) 2005,2006 Yoshinori Sato
 * Copyright (C) 2005  AXE,Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
#include <asm/cpu/mmu_context.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/page.h>
	
/* Offsets to the stack */
OFF_R0  =  0		/* Return value. New ABI also arg4 */
OFF_R1  =  4     	/* New ABI: arg5 */
OFF_R2  =  8     	/* New ABI: arg6 */
OFF_R3  =  12     	/* New ABI: syscall_nr */
OFF_R4  =  16     	/* New ABI: arg0 */
OFF_R5  =  20     	/* New ABI: arg1 */
OFF_R6  =  24     	/* New ABI: arg2 */
OFF_R7  =  28     	/* New ABI: arg3 */
OFF_SP	=  (15*4)
OFF_PC  =  (16*4)
OFF_SR	=  (16*4+2*4)
OFF_TRA	=  (16*4+6*4)

#include <asm/entry-macros.S>

ENTRY(exception_handler)
	! already saved r0/r1
	mov.l	r2,@-sp
	mov.l	r3,@-sp
	mov	r0,r1
	cli
	mov.l	$cpu_mode,r2
	mov.l	@r2,r0
	mov.l	@(5*4,r15),r3	! previous SR
	shll2	r3		! set "S" flag
	rotl	r0		! T <- "S" flag
	rotl	r0		! "S" flag is LSB
	rotcr	r3		! T -> r3:b30
	shlr	r3
	shlr	r0
	bt/s	1f
	 mov.l	r3,@(5*4,r15)	! copy cpu mode to SR
	! switch to kernel mode
	mov	#1,r0
	rotr	r0
	rotr	r0
	mov.l	r0,@r2		! enter kernel mode
	mov.l	$current_thread_info,r2
	mov.l	@r2,r2
	mov	#0x20,r0
	shll8	r0
	add	r2,r0
	mov	r15,r2		! r2 = user stack top
	mov	r0,r15		! switch kernel stack
	add	#-4,r15		! dummy
	mov.l	r1,@-r15	! TRA
	sts.l	macl, @-r15
	sts.l	mach, @-r15
	stc.l	gbr, @-r15
	mov.l	@(4*4,r2),r0
	mov.l	@(5*4,r2),r1
	mov.l	r1,@-r15	! original SR
	sts.l	pr,@-r15
	mov.l	r0,@-r15	! original PC
	mov	r2,r3
	add	#(4+2)*4,r3	! rewind r0 - r3 + exception frame
	mov.l	r3,@-r15	! original SP
	mov.l	r14,@-r15
	mov.l	r13,@-r15
	mov.l	r12,@-r15
	mov.l	r11,@-r15
	mov.l	r10,@-r15
	mov.l	r9,@-r15
	mov.l	r8,@-r15
	mov.l	r7,@-r15
	mov.l	r6,@-r15
	mov.l	r5,@-r15
	mov.l	r4,@-r15
	mov	r2,r8		! copy user -> kernel stack
	mov.l	@r8+,r3
	mov.l	r3,@-r15
	mov.l	@r8+,r2
	mov.l	r2,@-r15
	mov.l	@r8+,r1
	mov.l	r1,@-r15
	mov.l	@r8+,r0
	bra	2f
	 mov.l	r0,@-r15
1:
	! in kernel exception
	mov	#(22-4-4-1)*4+4,r0
	mov	r15,r2
	sub	r0,r15
	mov.l	@r2+,r0		! old R3
	mov.l	r0,@-r15	
	mov.l	@r2+,r0		! old R2
	mov.l	r0,@-r15	
	mov.l	@r2+,r0		! old R1
	mov.l	r0,@-r15	
	mov.l	@r2+,r0		! old R0
	mov.l	r0,@-r15	
	mov.l	@r2+,r3		! old PC
	mov.l	@r2+,r0		! old SR
	add	#-4,r2		! exception frame stub (sr)
	mov.l	r1,@-r2		! TRA
	sts.l	macl, @-r2
	sts.l	mach, @-r2
	stc.l	gbr, @-r2
	mov.l	r0,@-r2		! save old SR
	sts.l	pr,@-r2
	mov.l	r3,@-r2		! save old PC
	mov	r2,r0
	add	#8*4,r0
	mov.l	r0,@-r2		! save old SP
	mov.l	r14,@-r2
	mov.l	r13,@-r2
	mov.l	r12,@-r2
	mov.l	r11,@-r2
	mov.l	r10,@-r2
	mov.l	r9,@-r2
	mov.l	r8,@-r2
	mov.l	r7,@-r2
	mov.l	r6,@-r2
	mov.l	r5,@-r2
	mov.l	r4,@-r2
	mov.l	@(OFF_R0,r15),r0
	mov.l	@(OFF_R1,r15),r1
	mov.l	@(OFF_R2,r15),r2
	mov.l	@(OFF_R3,r15),r3
2:
	mov	#OFF_TRA,r8
	add	r15,r8
	mov.l	@r8,r9	
	mov	#64,r8
	cmp/hs	r8,r9
	bt	interrupt_entry	! vec >= 64 is interrupt
	mov	#32,r8
	cmp/hs	r8,r9
	bt	trap_entry	! 64 > vec >= 32  is trap

#if defined(CONFIG_SH_FPU)
	mov     #13,r8
	cmp/eq  r8,r9
	bt      10f             ! fpu
	nop
#endif

	mov.l	4f,r8
	mov	r9,r4
	shll2	r9
	add	r9,r8
	mov.l	@r8,r8
	mov	#0,r9
	cmp/eq	r9,r8
	bf	3f
	mov.l	8f,r8		! unhandled exception
#if defined(CONFIG_SH_FPU)
10:
	mov.l	9f, r8		! unhandled exception
#endif
3:
	mov.l	5f,r10
	jmp	@r8
	 lds	r10,pr

interrupt_entry:
	mov	r9,r4
	mov	r15,r5
	mov.l	6f,r9
	mov.l	7f,r8
	jmp	@r8
	 lds	r9,pr

	.align	2
4:	.long	exception_handling_table
5:	.long	ret_from_exception
6:	.long	ret_from_irq
7:	.long	do_IRQ
8:	.long	do_exception_error
#ifdef CONFIG_SH_FPU
9:	.long	fpu_error_trap_handler
#endif

trap_entry:
	mov	#0x30,r8
	cmp/ge	r8,r9		! vector 0x20-0x2f is systemcall
	bt	1f
	add	#-0x10,r9	! convert SH2 to SH3/4 ABI
1:	
	shll2	r9			! TRA
	mov	#OFF_TRA,r8
	add	r15,r8
	mov.l	r9,@r8
	mov	r9,r8
#ifdef CONFIG_TRACE_IRQFLAGS
	mov.l	2f, r9
	jsr	@r9
	 nop
#endif
	sti
	bra	system_call
	 nop
	
	.align	2
#ifdef CONFIG_TRACE_IRQFLAGS
2:	.long	trace_hardirqs_on
#endif

#if defined(CONFIG_SH_STANDARD_BIOS)
	/* Unwind the stack and jmp to the debug entry */
ENTRY(sh_bios_handler)
	mov	r15,r0
	add	#(22-4)*4-4,r0
	ldc.l	@r0+,gbr
	lds.l	@r0+,mach
	lds.l	@r0+,macl
	mov	r15,r0
	mov.l	@(OFF_SP,r0),r1
	mov	#OFF_SR,r2
	mov.l	@(r0,r2),r3
	mov.l	r3,@-r1
	mov	#OFF_SP,r2
	mov.l	@(r0,r2),r3
	mov.l	r3,@-r1
	mov	r15,r0
	add	#(22-4)*4-8,r0
	mov.l	1f,r2
	mov.l	@r2,r2
	stc	sr,r3
	mov.l	r2,@r0
	mov.l	r3,@r0
	mov.l	r1,@(8,r0)	
	mov.l	@r15+, r0
	mov.l	@r15+, r1
	mov.l	@r15+, r2
	mov.l	@r15+, r3
	mov.l	@r15+, r4
	mov.l	@r15+, r5
	mov.l	@r15+, r6
	mov.l	@r15+, r7
	mov.l	@r15+, r8
	mov.l	@r15+, r9
	mov.l	@r15+, r10
	mov.l	@r15+, r11
	mov.l	@r15+, r12
	mov.l	@r15+, r13
	mov.l	@r15+, r14
	add	#8,r15
	lds.l	@r15+, pr
	rte
	 mov.l	@r15+,r15
	.align	2
1:	.long	gdb_vbr_vector
#endif /* CONFIG_SH_STANDARD_BIOS */

ENTRY(address_error_trap_handler)
	mov	r15,r4				! regs
	add	#4,r4
	mov	#OFF_PC,r0
	mov.l	@(r0,r15),r6			! pc
	mov.l	1f,r0
	jmp	@r0
	 mov	#0,r5				! writeaccess is unknown
	.align	2

1:	.long	do_address_error

restore_all:
	cli
#ifdef CONFIG_TRACE_IRQFLAGS
	mov.l	1f, r0
	jsr	@r0
	 nop
#endif
	mov	r15,r0
	mov.l	$cpu_mode,r2
	mov	#OFF_SR,r3
	mov.l	@(r0,r3),r1
	mov.l	r1,@r2
	shll2	r1				! clear MD bit
	shlr2	r1
	mov.l	@(OFF_SP,r0),r2
	add	#-8,r2
	mov.l	r2,@(OFF_SP,r0)			! point exception frame top
	mov.l	r1,@(4,r2)			! set sr
	mov	#OFF_PC,r3
	mov.l	@(r0,r3),r1
	mov.l	r1,@r2				! set pc
	add	#4*16+4,r0
	lds.l	@r0+,pr
	add	#4,r0				! skip sr
	ldc.l	@r0+,gbr
	lds.l	@r0+,mach
	lds.l	@r0+,macl
	get_current_thread_info r0, r1
	mov.l	$current_thread_info,r1
	mov.l	r0,@r1
	mov.l	@r15+,r0
	mov.l	@r15+,r1
	mov.l	@r15+,r2
	mov.l	@r15+,r3
	mov.l	@r15+,r4
	mov.l	@r15+,r5
	mov.l	@r15+,r6
	mov.l	@r15+,r7
	mov.l	@r15+,r8
	mov.l	@r15+,r9
	mov.l	@r15+,r10
	mov.l	@r15+,r11
	mov.l	@r15+,r12
	mov.l	@r15+,r13
	mov.l	@r15+,r14
	mov.l	@r15,r15
	rte
	 nop

	.align 2
#ifdef CONFIG_TRACE_IRQFLAGS
1:     .long   trace_hardirqs_off
#endif
$current_thread_info:
	.long	__current_thread_info
$cpu_mode:	
	.long	__cpu_mode
		
! common exception handler
#include "../../entry-common.S"
	
	.data
! cpu operation mode 
! bit30 = MD (compatible SH3/4)
__cpu_mode:
	.long	0x40000000
		
	.section	.bss
__current_thread_info:
	.long	0

ENTRY(exception_handling_table)
	.space	4*32
Commit	Line	Data
de398406 YS	1	/*
	2	* arch/sh/kernel/cpu/sh2/entry.S
	3	*
	4	* The SH-2 exception entry
	5	*
	6	* Copyright (C) 2005,2006 Yoshinori Sato
	7	* Copyright (C) 2005 AXE,Inc.
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13
	14	#include <linux/linkage.h>
	15	#include <asm/asm-offsets.h>
	16	#include <asm/thread_info.h>
	17	#include <asm/cpu/mmu_context.h>
	18	#include <asm/unistd.h>
	19	#include <asm/errno.h>
	20	#include <asm/page.h>
	21
	22	/* Offsets to the stack */
	23	OFF_R0 = 0 /* Return value. New ABI also arg4 */
	24	OFF_R1 = 4 /* New ABI: arg5 */
	25	OFF_R2 = 8 /* New ABI: arg6 */
	26	OFF_R3 = 12 /* New ABI: syscall_nr */
	27	OFF_R4 = 16 /* New ABI: arg0 */
	28	OFF_R5 = 20 /* New ABI: arg1 */
	29	OFF_R6 = 24 /* New ABI: arg2 */
	30	OFF_R7 = 28 /* New ABI: arg3 */
	31	OFF_SP = (15*4)
	32	OFF_PC = (16*4)
	33	OFF_SR = (164+24)
	34	OFF_TRA = (164+64)
	35
	36	#include <asm/entry-macros.S>
	37
	38	ENTRY(exception_handler)
	39	! already saved r0/r1
	40	mov.l r2,@-sp
	41	mov.l r3,@-sp
	42	mov r0,r1
	43	cli
	44	mov.l $cpu_mode,r2
	45	mov.l @r2,r0
	46	mov.l @(5*4,r15),r3 ! previous SR
	47	shll2 r3 ! set "S" flag
	48	rotl r0 ! T <- "S" flag
	49	rotl r0 ! "S" flag is LSB
	50	rotcr r3 ! T -> r3:b30
	51	shlr r3
	52	shlr r0
	53	bt/s 1f
	54	mov.l r3,@(5*4,r15) ! copy cpu mode to SR
	55	! switch to kernel mode
	56	mov #1,r0
	57	rotr r0
	58	rotr r0
	59	mov.l r0,@r2 ! enter kernel mode
	60	mov.l $current_thread_info,r2
	61	mov.l @r2,r2
	62	mov #0x20,r0
	63	shll8 r0
	64	add r2,r0
65	mov r15,r2 ! r2 = user stack top
66	mov r0,r15 ! switch kernel stack
67	add #-4,r15 ! dummy
68	mov.l r1,@-r15 ! TRA
69	sts.l macl, @-r15
70	sts.l mach, @-r15
71	stc.l gbr, @-r15
72	mov.l @(4*4,r2),r0
73	mov.l @(5*4,r2),r1
74	mov.l r1,@-r15 ! original SR
75	sts.l pr,@-r15
76	mov.l r0,@-r15 ! original PC
77	mov r2,r3
78	add #(4+2)*4,r3 ! rewind r0 - r3 + exception frame
79	mov.l r3,@-r15 ! original SP
80	mov.l r14,@-r15
81	mov.l r13,@-r15
82	mov.l r12,@-r15
83	mov.l r11,@-r15
84	mov.l r10,@-r15
85	mov.l r9,@-r15
86	mov.l r8,@-r15
87	mov.l r7,@-r15
88	mov.l r6,@-r15
89	mov.l r5,@-r15
90	mov.l r4,@-r15
91	mov r2,r8 ! copy user -> kernel stack
92	mov.l @r8+,r3
93	mov.l r3,@-r15
94	mov.l @r8+,r2
95	mov.l r2,@-r15
96	mov.l @r8+,r1
97	mov.l r1,@-r15
98	mov.l @r8+,r0
99	bra 2f
100	mov.l r0,@-r15
101	1:
102	! in kernel exception
103	mov #(22-4-4-1)*4+4,r0
104	mov r15,r2
105	sub r0,r15
106	mov.l @r2+,r0 ! old R3
107	mov.l r0,@-r15
108	mov.l @r2+,r0 ! old R2
109	mov.l r0,@-r15
110	mov.l @r2+,r0 ! old R1
111	mov.l r0,@-r15
112	mov.l @r2+,r0 ! old R0
113	mov.l r0,@-r15
114	mov.l @r2+,r3 ! old PC
115	mov.l @r2+,r0 ! old SR
116	add #-4,r2 ! exception frame stub (sr)
117	mov.l r1,@-r2 ! TRA
118	sts.l macl, @-r2
119	sts.l mach, @-r2
120	stc.l gbr, @-r2
121	mov.l r0,@-r2 ! save old SR
122	sts.l pr,@-r2
123	mov.l r3,@-r2 ! save old PC
124	mov r2,r0
125	add #8*4,r0
126	mov.l r0,@-r2 ! save old SP
127	mov.l r14,@-r2
128	mov.l r13,@-r2
129	mov.l r12,@-r2
130	mov.l r11,@-r2
131	mov.l r10,@-r2
132	mov.l r9,@-r2
133	mov.l r8,@-r2
134	mov.l r7,@-r2
135	mov.l r6,@-r2
136	mov.l r5,@-r2
137	mov.l r4,@-r2
138	mov.l @(OFF_R0,r15),r0
139	mov.l @(OFF_R1,r15),r1
140	mov.l @(OFF_R2,r15),r2
141	mov.l @(OFF_R3,r15),r3
142	2:
143	mov #OFF_TRA,r8
144	add r15,r8
145	mov.l @r8,r9
146	mov #64,r8
147	cmp/hs r8,r9
148	bt interrupt_entry ! vec >= 64 is interrupt
149	mov #32,r8
150	cmp/hs r8,r9
151	bt trap_entry ! 64 > vec >= 32 is trap
74d99a5e PM	152
	153	#if defined(CONFIG_SH_FPU)
	154	mov #13,r8
	155	cmp/eq r8,r9
	156	bt 10f ! fpu
	157	nop
	158	#endif
	159
de398406 YS	160	mov.l 4f,r8
	161	mov r9,r4
	162	shll2 r9
	163	add r9,r8
	164	mov.l @r8,r8
	165	mov #0,r9
	166	cmp/eq r9,r8
	167	bf 3f
	168	mov.l 8f,r8 ! unhandled exception
74d99a5e PM	169	#if defined(CONFIG_SH_FPU)
	170	10:
	171	mov.l 9f, r8 ! unhandled exception
	172	#endif
de398406 YS	173	3:
	174	mov.l 5f,r10
	175	jmp @r8
	176	lds r10,pr
	177
	178	interrupt_entry:
	179	mov r9,r4
3afb209a	180	mov r15,r5
de398406 YS	181	mov.l 6f,r9
	182	mov.l 7f,r8
	183	jmp @r8
	184	lds r9,pr
	185
	186	.align 2
	187	4: .long exception_handling_table
	188	5: .long ret_from_exception
	189	6: .long ret_from_irq
	190	7: .long do_IRQ
	191	8: .long do_exception_error
74d99a5e PM	192	#ifdef CONFIG_SH_FPU
	193	9: .long fpu_error_trap_handler
	194	#endif
	195
e9cfc147	196	trap_entry:
4aa362bb YS	197	mov #0x30,r8
	198	cmp/ge r8,r9 ! vector 0x20-0x2f is systemcall
	199	bt 1f
	200	add #-0x10,r9 ! convert SH2 to SH3/4 ABI
e9cfc147	201	1:
de398406 YS	202	shll2 r9 ! TRA
	203	mov #OFF_TRA,r8
	204	add r15,r8
	205	mov.l r9,@r8
	206	mov r9,r8
afbfb52e	207	#ifdef CONFIG_TRACE_IRQFLAGS
e9cfc147	208	mov.l 2f, r9
afbfb52e PM	209	jsr @r9
	210	nop
	211	#endif
de398406 YS	212	sti
	213	bra system_call
	214	nop
	215
	216	.align 2
afbfb52e	217	#ifdef CONFIG_TRACE_IRQFLAGS
e9cfc147	218	2: .long trace_hardirqs_on
afbfb52e	219	#endif
de398406 YS	220
	221	#if defined(CONFIG_SH_STANDARD_BIOS)
	222	/* Unwind the stack and jmp to the debug entry */
f413d0d9	223	ENTRY(sh_bios_handler)
de398406 YS	224	mov r15,r0
	225	add #(22-4)*4-4,r0
	226	ldc.l @r0+,gbr
	227	lds.l @r0+,mach
	228	lds.l @r0+,macl
	229	mov r15,r0
	230	mov.l @(OFF_SP,r0),r1
	231	mov #OFF_SR,r2
	232	mov.l @(r0,r2),r3
	233	mov.l r3,@-r1
	234	mov #OFF_SP,r2
	235	mov.l @(r0,r2),r3
	236	mov.l r3,@-r1
	237	mov r15,r0
	238	add #(22-4)*4-8,r0
	239	mov.l 1f,r2
	240	mov.l @r2,r2
	241	stc sr,r3
	242	mov.l r2,@r0
	243	mov.l r3,@r0
	244	mov.l r1,@(8,r0)
	245	mov.l @r15+, r0
	246	mov.l @r15+, r1
	247	mov.l @r15+, r2
	248	mov.l @r15+, r3
	249	mov.l @r15+, r4
	250	mov.l @r15+, r5
	251	mov.l @r15+, r6
	252	mov.l @r15+, r7
	253	mov.l @r15+, r8
	254	mov.l @r15+, r9
	255	mov.l @r15+, r10
	256	mov.l @r15+, r11
	257	mov.l @r15+, r12
	258	mov.l @r15+, r13
	259	mov.l @r15+, r14
	260	add #8,r15
	261	lds.l @r15+, pr
	262	rte
	263	mov.l @r15+,r15
	264	.align 2
	265	1: .long gdb_vbr_vector
	266	#endif /* CONFIG_SH_STANDARD_BIOS */
	267
5a4f7c66	268	ENTRY(address_error_trap_handler)
de398406 YS	269	mov r15,r4 ! regs
	270	add #4,r4
	271	mov #OFF_PC,r0
	272	mov.l @(r0,r15),r6 ! pc
	273	mov.l 1f,r0
	274	jmp @r0
	275	mov #0,r5 ! writeaccess is unknown
	276	.align 2
	277
	278	1: .long do_address_error
	279
	280	restore_all:
	281	cli
afbfb52e	282	#ifdef CONFIG_TRACE_IRQFLAGS
e9cfc147	283	mov.l 1f, r0
afbfb52e PM	284	jsr @r0
	285	nop
	286	#endif
de398406 YS	287	mov r15,r0
	288	mov.l $cpu_mode,r2
	289	mov #OFF_SR,r3
	290	mov.l @(r0,r3),r1
	291	mov.l r1,@r2
	292	shll2 r1 ! clear MD bit
	293	shlr2 r1
	294	mov.l @(OFF_SP,r0),r2
	295	add #-8,r2
	296	mov.l r2,@(OFF_SP,r0) ! point exception frame top
	297	mov.l r1,@(4,r2) ! set sr
	298	mov #OFF_PC,r3
	299	mov.l @(r0,r3),r1
	300	mov.l r1,@r2 ! set pc
	301	add #4*16+4,r0
	302	lds.l @r0+,pr
	303	add #4,r0 ! skip sr
	304	ldc.l @r0+,gbr
	305	lds.l @r0+,mach
	306	lds.l @r0+,macl
	307	get_current_thread_info r0, r1
	308	mov.l $current_thread_info,r1
	309	mov.l r0,@r1
	310	mov.l @r15+,r0
	311	mov.l @r15+,r1
	312	mov.l @r15+,r2
	313	mov.l @r15+,r3
	314	mov.l @r15+,r4
	315	mov.l @r15+,r5
	316	mov.l @r15+,r6
	317	mov.l @r15+,r7
	318	mov.l @r15+,r8
	319	mov.l @r15+,r9
	320	mov.l @r15+,r10
	321	mov.l @r15+,r11
	322	mov.l @r15+,r12
	323	mov.l @r15+,r13
	324	mov.l @r15+,r14
	325	mov.l @r15,r15
	326	rte
	327	nop
de398406	328
9f9a5de4	329	.align 2
e9cfc147 YS	330	#ifdef CONFIG_TRACE_IRQFLAGS
	331	1: .long trace_hardirqs_off
	332	#endif
de398406 YS	333	$current_thread_info:
	334	.long __current_thread_info
	335	$cpu_mode:
	336	.long __cpu_mode
	337
	338	! common exception handler
	339	#include "../../entry-common.S"
	340
	341	.data
	342	! cpu operation mode
	343	! bit30 = MD (compatible SH3/4)
	344	__cpu_mode:
	345	.long 0x40000000
	346
	347	.section .bss
	348	__current_thread_info:
	349	.long 0
	350
	351	ENTRY(exception_handling_table)
	352	.space 4*32