[deliverable/linux.git] / arch / sh / kernel / cpu / sh2a / clock-sh7201.c

/*
 * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
 *
 * SH7201 support for the clock framework
 *
 *  Copyright (C) 2008 Peter Griffin  <pgriffin@mpc-data.co.uk>
 *
 * Based on clock-sh4.c
 *  Copyright (C) 2005  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>

static const int pll1rate[]={1,2,3,4,6,8};
static const int pfc_divisors[]={1,2,3,4,6,8,12};
#define ifc_divisors pfc_divisors

#if (CONFIG_SH_CLK_MD == 0)
#define PLL2 (4)
#elif (CONFIG_SH_CLK_MD == 2)
#define PLL2 (2)
#elif (CONFIG_SH_CLK_MD == 3)
#define PLL2 (1)
#else
#error "Illegal Clock Mode!"
#endif

static void master_clk_init(struct clk *clk)
{
	clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
}

static struct clk_ops sh7201_master_clk_ops = {
	.init		= master_clk_init,
};

static void module_clk_recalc(struct clk *clk)
{
	int idx = (ctrl_inw(FREQCR) & 0x0007);
	clk->rate = clk->parent->rate / pfc_divisors[idx];
}

static struct clk_ops sh7201_module_clk_ops = {
	.recalc		= module_clk_recalc,
};

static void bus_clk_recalc(struct clk *clk)
{
	int idx = (ctrl_inw(FREQCR) & 0x0007);
	clk->rate = clk->parent->rate / pfc_divisors[idx];
}

static struct clk_ops sh7201_bus_clk_ops = {
	.recalc		= bus_clk_recalc,
};

static void cpu_clk_recalc(struct clk *clk)
{
	int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
	clk->rate = clk->parent->rate / ifc_divisors[idx];
}

static struct clk_ops sh7201_cpu_clk_ops = {
	.recalc		= cpu_clk_recalc,
};

static struct clk_ops *sh7201_clk_ops[] = {
	&sh7201_master_clk_ops,
	&sh7201_module_clk_ops,
	&sh7201_bus_clk_ops,
	&sh7201_cpu_clk_ops,
};

void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
	if (idx < ARRAY_SIZE(sh7201_clk_ops))
		*ops = sh7201_clk_ops[idx];
}
Commit	Line	Data
2825999e PG	1	/*
	2	* arch/sh/kernel/cpu/sh2a/clock-sh7201.c
	3	*
	4	* SH7201 support for the clock framework
	5	*
	6	* Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
	7	*
	8	* Based on clock-sh4.c
	9	* Copyright (C) 2005 Paul Mundt
	10	*
	11	* This file is subject to the terms and conditions of the GNU General Public
	12	* License. See the file "COPYING" in the main directory of this archive
	13	* for more details.
	14	*/
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
	17	#include <asm/clock.h>
	18	#include <asm/freq.h>
	19	#include <asm/io.h>
	20
270c5609 TK	21	static const int pll1rate[]={1,2,3,4,6,8};
270c5609 TK	22	static const int pfc_divisors[]={1,2,3,4,6,8,12};
2825999e PG	23	#define ifc_divisors pfc_divisors
	24
	25	#if (CONFIG_SH_CLK_MD == 0)
	26	#define PLL2 (4)
	27	#elif (CONFIG_SH_CLK_MD == 2)
	28	#define PLL2 (2)
	29	#elif (CONFIG_SH_CLK_MD == 3)
	30	#define PLL2 (1)
	31	#else
	32	#error "Illegal Clock Mode!"
	33	#endif
	34
	35	static void master_clk_init(struct clk *clk)
	36	{
	37	clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
	38	}
	39
	40	static struct clk_ops sh7201_master_clk_ops = {
	41	.init = master_clk_init,
	42	};
	43
	44	static void module_clk_recalc(struct clk *clk)
	45	{
	46	int idx = (ctrl_inw(FREQCR) & 0x0007);
	47	clk->rate = clk->parent->rate / pfc_divisors[idx];
	48	}
	49
	50	static struct clk_ops sh7201_module_clk_ops = {
	51	.recalc = module_clk_recalc,
	52	};
	53
	54	static void bus_clk_recalc(struct clk *clk)
	55	{
	56	int idx = (ctrl_inw(FREQCR) & 0x0007);
	57	clk->rate = clk->parent->rate / pfc_divisors[idx];
	58	}
	59
	60	static struct clk_ops sh7201_bus_clk_ops = {
	61	.recalc = bus_clk_recalc,
	62	};
	63
	64	static void cpu_clk_recalc(struct clk *clk)
	65	{
	66	int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
	67	clk->rate = clk->parent->rate / ifc_divisors[idx];
	68	}
	69
	70	static struct clk_ops sh7201_cpu_clk_ops = {
	71	.recalc = cpu_clk_recalc,
	72	};
	73
	74	static struct clk_ops *sh7201_clk_ops[] = {
	75	&sh7201_master_clk_ops,
	76	&sh7201_module_clk_ops,
	77	&sh7201_bus_clk_ops,
	78	&sh7201_cpu_clk_ops,
	79	};
	80
	81	void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
	82	{
	83	if (idx < ARRAY_SIZE(sh7201_clk_ops))
	84	*ops = sh7201_clk_ops[idx];
	85	}