Commit | Line | Data |
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9d4436a6 YS |
1 | /* |
2 | * SH7206 Setup | |
3 | * | |
4 | * Copyright (C) 2006 Yoshinori Sato | |
f858abbe | 5 | * Copyright (C) 2009 Paul Mundt |
9d4436a6 YS |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/serial.h> | |
96de1a8f | 14 | #include <linux/serial_sci.h> |
46a12f74 | 15 | #include <linux/sh_timer.h> |
698aa99d | 16 | #include <linux/io.h> |
9d4436a6 | 17 | |
2eb0303c MD |
18 | enum { |
19 | UNUSED = 0, | |
20 | ||
21 | /* interrupt sources */ | |
22 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
23 | PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, | |
24 | ADC_ADI0, ADC_ADI1, | |
f858abbe PM |
25 | |
26 | DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, | |
27 | ||
28 | MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, | |
29 | MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, | |
30 | IIC3, | |
31 | ||
2eb0303c | 32 | CMT0, CMT1, BSC, WDT, |
f858abbe PM |
33 | |
34 | MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V, | |
35 | ||
2eb0303c | 36 | POE2_OEI3, |
f858abbe PM |
37 | |
38 | SCIF0, SCIF1, SCIF2, SCIF3, | |
2eb0303c MD |
39 | |
40 | /* interrupt groups */ | |
f858abbe | 41 | PINT, |
2eb0303c MD |
42 | }; |
43 | ||
44 | static struct intc_vect vectors[] __initdata = { | |
45 | INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), | |
46 | INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), | |
47 | INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), | |
48 | INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), | |
49 | INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), | |
50 | INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), | |
51 | INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), | |
52 | INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), | |
53 | INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), | |
f858abbe PM |
54 | INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), |
55 | INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), | |
56 | INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), | |
57 | INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), | |
58 | INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), | |
59 | INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), | |
60 | INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), | |
61 | INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), | |
2eb0303c MD |
62 | INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), |
63 | INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), | |
f858abbe PM |
64 | INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157), |
65 | INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159), | |
66 | INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161), | |
67 | INTC_IRQ(MTU0_VEF, 162), | |
68 | INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165), | |
69 | INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169), | |
70 | INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173), | |
71 | INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177), | |
72 | INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181), | |
73 | INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183), | |
2eb0303c | 74 | INTC_IRQ(MTU2_TCI3V, 184), |
f858abbe PM |
75 | INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189), |
76 | INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191), | |
2eb0303c | 77 | INTC_IRQ(MTU2_TCI4V, 192), |
f858abbe PM |
78 | INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197), |
79 | INTC_IRQ(MTU5, 198), | |
80 | INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201), | |
81 | INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205), | |
82 | INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207), | |
2eb0303c | 83 | INTC_IRQ(MTU2S_TCI3V, 208), |
f858abbe PM |
84 | INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213), |
85 | INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215), | |
2eb0303c | 86 | INTC_IRQ(MTU2S_TCI4V, 216), |
f858abbe PM |
87 | INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221), |
88 | INTC_IRQ(MTU5S, 222), | |
2eb0303c | 89 | INTC_IRQ(POE2_OEI3, 224), |
f858abbe PM |
90 | INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229), |
91 | INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231), | |
92 | INTC_IRQ(IIC3, 232), | |
93 | INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241), | |
94 | INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243), | |
95 | INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245), | |
96 | INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247), | |
97 | INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249), | |
98 | INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251), | |
99 | INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253), | |
100 | INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255), | |
2eb0303c MD |
101 | }; |
102 | ||
103 | static struct intc_group groups[] __initdata = { | |
104 | INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, | |
105 | PINT4, PINT5, PINT6, PINT7), | |
2eb0303c MD |
106 | }; |
107 | ||
108 | static struct intc_prio_reg prio_registers[] __initdata = { | |
109 | { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | |
110 | { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
111 | { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } }, | |
112 | { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, | |
113 | { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, | |
114 | { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } }, | |
115 | { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF, | |
116 | MTU1_AB, MTU1_VU } }, | |
117 | { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU, | |
118 | MTU3_ABCD, MTU2_TCI3V } }, | |
119 | { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V, | |
120 | MTU5, POE2_12 } }, | |
121 | { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V, | |
122 | MTU4S_ABCD, MTU2S_TCI4V } }, | |
123 | { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } }, | |
124 | { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, | |
125 | }; | |
126 | ||
127 | static struct intc_mask_reg mask_registers[] __initdata = { | |
128 | { 0xfffe0808, 0, 16, /* PINTER */ | |
129 | { 0, 0, 0, 0, 0, 0, 0, 0, | |
130 | PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, | |
131 | }; | |
132 | ||
133 | static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, | |
7f3edee8 | 134 | mask_registers, prio_registers, NULL); |
2eb0303c | 135 | |
9d4436a6 YS |
136 | static struct plat_sci_port sci_platform_data[] = { |
137 | { | |
138 | .mapbase = 0xfffe8000, | |
139 | .flags = UPF_BOOT_AUTOCONF, | |
140 | .type = PORT_SCIF, | |
f858abbe | 141 | .irqs = { 240, 240, 240, 240 }, |
9d4436a6 YS |
142 | }, { |
143 | .mapbase = 0xfffe8800, | |
144 | .flags = UPF_BOOT_AUTOCONF, | |
145 | .type = PORT_SCIF, | |
f858abbe | 146 | .irqs = { 244, 244, 244, 244 }, |
9d4436a6 YS |
147 | }, { |
148 | .mapbase = 0xfffe9000, | |
149 | .flags = UPF_BOOT_AUTOCONF, | |
150 | .type = PORT_SCIF, | |
f858abbe | 151 | .irqs = { 248, 248, 248, 248 }, |
9d4436a6 YS |
152 | }, { |
153 | .mapbase = 0xfffe9800, | |
154 | .flags = UPF_BOOT_AUTOCONF, | |
155 | .type = PORT_SCIF, | |
f858abbe | 156 | .irqs = { 252, 252, 252, 252 }, |
9d4436a6 YS |
157 | }, { |
158 | .flags = 0, | |
159 | } | |
160 | }; | |
161 | ||
162 | static struct platform_device sci_device = { | |
163 | .name = "sh-sci", | |
164 | .id = -1, | |
165 | .dev = { | |
166 | .platform_data = sci_platform_data, | |
167 | }, | |
168 | }; | |
169 | ||
46a12f74 | 170 | static struct sh_timer_config cmt0_platform_data = { |
698aa99d MD |
171 | .name = "CMT0", |
172 | .channel_offset = 0x02, | |
173 | .timer_bit = 0, | |
af777ce4 | 174 | .clk = "peripheral_clk", |
698aa99d MD |
175 | .clockevent_rating = 125, |
176 | .clocksource_rating = 0, /* disabled due to code generation issues */ | |
177 | }; | |
178 | ||
179 | static struct resource cmt0_resources[] = { | |
180 | [0] = { | |
181 | .name = "CMT0", | |
182 | .start = 0xfffec002, | |
183 | .end = 0xfffec007, | |
184 | .flags = IORESOURCE_MEM, | |
185 | }, | |
186 | [1] = { | |
187 | .start = 140, | |
188 | .flags = IORESOURCE_IRQ, | |
189 | }, | |
190 | }; | |
191 | ||
192 | static struct platform_device cmt0_device = { | |
193 | .name = "sh_cmt", | |
194 | .id = 0, | |
195 | .dev = { | |
196 | .platform_data = &cmt0_platform_data, | |
197 | }, | |
198 | .resource = cmt0_resources, | |
199 | .num_resources = ARRAY_SIZE(cmt0_resources), | |
200 | }; | |
201 | ||
46a12f74 | 202 | static struct sh_timer_config cmt1_platform_data = { |
698aa99d MD |
203 | .name = "CMT1", |
204 | .channel_offset = 0x08, | |
205 | .timer_bit = 1, | |
af777ce4 | 206 | .clk = "peripheral_clk", |
698aa99d MD |
207 | .clockevent_rating = 125, |
208 | .clocksource_rating = 0, /* disabled due to code generation issues */ | |
209 | }; | |
210 | ||
211 | static struct resource cmt1_resources[] = { | |
212 | [0] = { | |
213 | .name = "CMT1", | |
214 | .start = 0xfffec008, | |
215 | .end = 0xfffec00d, | |
216 | .flags = IORESOURCE_MEM, | |
217 | }, | |
218 | [1] = { | |
219 | .start = 144, | |
220 | .flags = IORESOURCE_IRQ, | |
221 | }, | |
222 | }; | |
223 | ||
224 | static struct platform_device cmt1_device = { | |
225 | .name = "sh_cmt", | |
226 | .id = 1, | |
227 | .dev = { | |
228 | .platform_data = &cmt1_platform_data, | |
229 | }, | |
230 | .resource = cmt1_resources, | |
231 | .num_resources = ARRAY_SIZE(cmt1_resources), | |
232 | }; | |
233 | ||
46a12f74 | 234 | static struct sh_timer_config mtu2_0_platform_data = { |
da107c6e MD |
235 | .name = "MTU2_0", |
236 | .channel_offset = -0x80, | |
237 | .timer_bit = 0, | |
af777ce4 | 238 | .clk = "peripheral_clk", |
da107c6e MD |
239 | .clockevent_rating = 200, |
240 | }; | |
241 | ||
242 | static struct resource mtu2_0_resources[] = { | |
243 | [0] = { | |
244 | .name = "MTU2_0", | |
245 | .start = 0xfffe4300, | |
246 | .end = 0xfffe4326, | |
247 | .flags = IORESOURCE_MEM, | |
248 | }, | |
249 | [1] = { | |
250 | .start = 156, | |
251 | .flags = IORESOURCE_IRQ, | |
252 | }, | |
253 | }; | |
254 | ||
255 | static struct platform_device mtu2_0_device = { | |
256 | .name = "sh_mtu2", | |
257 | .id = 0, | |
258 | .dev = { | |
259 | .platform_data = &mtu2_0_platform_data, | |
260 | }, | |
261 | .resource = mtu2_0_resources, | |
262 | .num_resources = ARRAY_SIZE(mtu2_0_resources), | |
263 | }; | |
264 | ||
46a12f74 | 265 | static struct sh_timer_config mtu2_1_platform_data = { |
da107c6e MD |
266 | .name = "MTU2_1", |
267 | .channel_offset = -0x100, | |
268 | .timer_bit = 1, | |
af777ce4 | 269 | .clk = "peripheral_clk", |
da107c6e MD |
270 | .clockevent_rating = 200, |
271 | }; | |
272 | ||
273 | static struct resource mtu2_1_resources[] = { | |
274 | [0] = { | |
275 | .name = "MTU2_1", | |
276 | .start = 0xfffe4380, | |
277 | .end = 0xfffe4390, | |
278 | .flags = IORESOURCE_MEM, | |
279 | }, | |
280 | [1] = { | |
281 | .start = 164, | |
282 | .flags = IORESOURCE_IRQ, | |
283 | }, | |
284 | }; | |
285 | ||
286 | static struct platform_device mtu2_1_device = { | |
287 | .name = "sh_mtu2", | |
288 | .id = 1, | |
289 | .dev = { | |
290 | .platform_data = &mtu2_1_platform_data, | |
291 | }, | |
292 | .resource = mtu2_1_resources, | |
293 | .num_resources = ARRAY_SIZE(mtu2_1_resources), | |
294 | }; | |
295 | ||
46a12f74 | 296 | static struct sh_timer_config mtu2_2_platform_data = { |
da107c6e MD |
297 | .name = "MTU2_2", |
298 | .channel_offset = 0x80, | |
299 | .timer_bit = 2, | |
af777ce4 | 300 | .clk = "peripheral_clk", |
da107c6e MD |
301 | .clockevent_rating = 200, |
302 | }; | |
303 | ||
304 | static struct resource mtu2_2_resources[] = { | |
305 | [0] = { | |
306 | .name = "MTU2_2", | |
307 | .start = 0xfffe4000, | |
308 | .end = 0xfffe400a, | |
309 | .flags = IORESOURCE_MEM, | |
310 | }, | |
311 | [1] = { | |
312 | .start = 180, | |
313 | .flags = IORESOURCE_IRQ, | |
314 | }, | |
315 | }; | |
316 | ||
317 | static struct platform_device mtu2_2_device = { | |
318 | .name = "sh_mtu2", | |
319 | .id = 2, | |
320 | .dev = { | |
321 | .platform_data = &mtu2_2_platform_data, | |
322 | }, | |
323 | .resource = mtu2_2_resources, | |
324 | .num_resources = ARRAY_SIZE(mtu2_2_resources), | |
325 | }; | |
326 | ||
9d4436a6 YS |
327 | static struct platform_device *sh7206_devices[] __initdata = { |
328 | &sci_device, | |
698aa99d MD |
329 | &cmt0_device, |
330 | &cmt1_device, | |
da107c6e MD |
331 | &mtu2_0_device, |
332 | &mtu2_1_device, | |
333 | &mtu2_2_device, | |
9d4436a6 YS |
334 | }; |
335 | ||
336 | static int __init sh7206_devices_setup(void) | |
337 | { | |
338 | return platform_add_devices(sh7206_devices, | |
339 | ARRAY_SIZE(sh7206_devices)); | |
340 | } | |
ba9a6337 | 341 | arch_initcall(sh7206_devices_setup); |
780a1568 | 342 | |
90015c89 | 343 | void __init plat_irq_setup(void) |
780a1568 | 344 | { |
2eb0303c | 345 | register_intc_controller(&intc_desc); |
780a1568 | 346 | } |
698aa99d MD |
347 | |
348 | static struct platform_device *sh7206_early_devices[] __initdata = { | |
349 | &cmt0_device, | |
350 | &cmt1_device, | |
da107c6e MD |
351 | &mtu2_0_device, |
352 | &mtu2_1_device, | |
353 | &mtu2_2_device, | |
698aa99d MD |
354 | }; |
355 | ||
da107c6e | 356 | #define STBCR3 0xfffe0408 |
698aa99d MD |
357 | #define STBCR4 0xfffe040c |
358 | ||
359 | void __init plat_early_device_setup(void) | |
360 | { | |
361 | /* enable CMT clock */ | |
362 | __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); | |
363 | ||
da107c6e MD |
364 | /* enable MTU2 clock */ |
365 | __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); | |
366 | ||
698aa99d MD |
367 | early_platform_add_devices(sh7206_early_devices, |
368 | ARRAY_SIZE(sh7206_early_devices)); | |
369 | } |