projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * arch/sh/kernel/cpu/sh3/probe.c | |
| 3 | * | |
| 4 | * CPU Subtype Probing for SH-3. | |
| 5 | * | |
| 6 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
| 7 | * Copyright (C) 2002 Paul Mundt | |
| 8 | * | |
| 9 | * This file is subject to the terms and conditions of the GNU General Public | |
| 10 | * License. See the file "COPYING" in the main directory of this archive | |
| 11 | * for more details. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/init.h> | |
| 15 | #include <asm/processor.h> | |
| 16 | #include <asm/cache.h> | |
| 17 | #include <asm/io.h> | |
| 18 | ||
| 4603f53a | 19 | void cpu_probe(void) |
| 1da177e4 LT |
20 | { |
| 21 | unsigned long addr0, addr1, data0, data1, data2, data3; | |
| 22 | ||
| cbaa118e | 23 | jump_to_uncached(); |
| 1da177e4 LT |
24 | /* |
| 25 | * Check if the entry shadows or not. | |
| 26 | * When shadowed, it's 128-entry system. | |
| 27 | * Otherwise, it's 256-entry system. | |
| 28 | */ | |
| 29 | addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12); | |
| 30 | addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12); | |
| 31 | ||
| 32 | /* First, write back & invalidate */ | |
| 9d56dd3b PM |
33 | data0 = __raw_readl(addr0); |
| 34 | __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); | |
| 35 | data1 = __raw_readl(addr1); | |
| 36 | __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); | |
| 1da177e4 LT |
37 | |
| 38 | /* Next, check if there's shadow or not */ | |
| 9d56dd3b | 39 | data0 = __raw_readl(addr0); |
| 1da177e4 | 40 | data0 ^= SH_CACHE_VALID; |
| 9d56dd3b PM |
41 | __raw_writel(data0, addr0); |
| 42 | data1 = __raw_readl(addr1); | |
| 1da177e4 | 43 | data2 = data1 ^ SH_CACHE_VALID; |
| 9d56dd3b PM |
44 | __raw_writel(data2, addr1); |
| 45 | data3 = __raw_readl(addr0); | |
| 1da177e4 LT |
46 | |
| 47 | /* Lastly, invaliate them. */ | |
| 9d56dd3b PM |
48 | __raw_writel(data0&~SH_CACHE_VALID, addr0); |
| 49 | __raw_writel(data2&~SH_CACHE_VALID, addr1); | |
| 1da177e4 | 50 | |
| cbaa118e | 51 | back_to_cached(); |
| 1da177e4 | 52 | |
| cb7af21f PM |
53 | boot_cpu_data.dcache.ways = 4; |
| 54 | boot_cpu_data.dcache.entry_shift = 4; | |
| 55 | boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; | |
| 56 | boot_cpu_data.dcache.flags = 0; | |
| 1da177e4 LT |
57 | |
| 58 | /* | |
| 59 | * 7709A/7729 has 16K cache (256-entry), while 7702 has only | |
| 60 | * 2K(direct) 7702 is not supported (yet) | |
| 61 | */ | |
| 62 | if (data0 == data1 && data2 == data3) { /* Shadow */ | |
| cb7af21f PM |
63 | boot_cpu_data.dcache.way_incr = (1 << 11); |
| 64 | boot_cpu_data.dcache.entry_mask = 0x7f0; | |
| 65 | boot_cpu_data.dcache.sets = 128; | |
| 66 | boot_cpu_data.type = CPU_SH7708; | |
| 1da177e4 | 67 | |
| cb7af21f | 68 | boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC; |
| 1da177e4 | 69 | } else { /* 7709A or 7729 */ |
| cb7af21f PM |
70 | boot_cpu_data.dcache.way_incr = (1 << 12); |
| 71 | boot_cpu_data.dcache.entry_mask = 0xff0; | |
| 72 | boot_cpu_data.dcache.sets = 256; | |
| 73 | boot_cpu_data.type = CPU_SH7729; | |
| 1da177e4 | 74 | |
| e5723e0e | 75 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) |
| cb7af21f | 76 | boot_cpu_data.type = CPU_SH7706; |
| e5723e0e PM |
77 | #endif |
| 78 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) | |
| cb7af21f | 79 | boot_cpu_data.type = CPU_SH7710; |
| e5723e0e | 80 | #endif |
| 9465a54f | 81 | #if defined(CONFIG_CPU_SUBTYPE_SH7712) |
| cb7af21f | 82 | boot_cpu_data.type = CPU_SH7712; |
| 9465a54f | 83 | #endif |
| 3ea6bc3d | 84 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) |
| cb7af21f | 85 | boot_cpu_data.type = CPU_SH7720; |
| 3ea6bc3d | 86 | #endif |
| 31a49c4b YS |
87 | #if defined(CONFIG_CPU_SUBTYPE_SH7721) |
| 88 | boot_cpu_data.type = CPU_SH7721; | |
| 89 | #endif | |
| 1da177e4 | 90 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
| cb7af21f | 91 | boot_cpu_data.type = CPU_SH7705; |
| 1da177e4 LT |
92 | |
| 93 | #if defined(CONFIG_SH7705_CACHE_32KB) | |
| cb7af21f PM |
94 | boot_cpu_data.dcache.way_incr = (1 << 13); |
| 95 | boot_cpu_data.dcache.entry_mask = 0x1ff0; | |
| 96 | boot_cpu_data.dcache.sets = 512; | |
| 9d56dd3b | 97 | __raw_writel(CCR_CACHE_32KB, CCR3_REG); |
| 1da177e4 | 98 | #else |
| 9d56dd3b | 99 | __raw_writel(CCR_CACHE_16KB, CCR3_REG); |
| 1da177e4 LT |
100 | #endif |
| 101 | #endif | |
| 102 | } | |
| 103 | ||
| 104 | /* | |
| 105 | * SH-3 doesn't have separate caches | |
| 106 | */ | |
| cb7af21f PM |
107 | boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; |
| 108 | boot_cpu_data.icache = boot_cpu_data.dcache; | |
| 1da177e4 | 109 | |
| e82da214 | 110 | boot_cpu_data.family = CPU_FAMILY_SH3; |
| 1da177e4 | 111 | } |