Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[deliverable/linux.git] / arch / sh / kernel / cpu / sh3 / setup-sh7710.c
CommitLineData
e5723e0e 1/*
ac919986 2 * SH3 Setup code for SH7710, SH7712
e5723e0e 3 *
ad89f87a 4 * Copyright (C) 2006, 2007 Paul Mundt
9465a54f 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
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6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
28b146c8 13#include <linux/irq.h>
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14#include <linux/serial.h>
15#include <asm/sci.h>
ad89f87a 16#include <asm/rtc.h>
e5723e0e 17
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18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
26 DMAC_DEI4, DMAC_DEI5,
27 IPSEC,
28 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 TMU0, TMU1, TMU2,
32 RTC_ATI, RTC_PRI, RTC_CUI,
33 WDT,
34 REF,
35
36 /* interrupt groups */
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
38};
39
5c37e025 40static struct intc_vect vectors[] __initdata = {
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41 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
ac919986 49#ifdef CONFIG_CPU_SUBTYPE_SH7710
28b146c8 50 INTC_VECT(IPSEC, 0xbe0),
ac919986 51#endif
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52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0),
62 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580),
64};
65
5c37e025 66static struct intc_group groups[] __initdata = {
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67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
74};
75
5c37e025 76static struct intc_prio priorities[] __initdata = {
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77 INTC_PRIO(DMAC1, 7),
78 INTC_PRIO(DMAC2, 7),
79 INTC_PRIO(SCIF0, 3),
80 INTC_PRIO(SCIF1, 3),
81 INTC_PRIO(SIOF0, 3),
82 INTC_PRIO(SIOF1, 3),
83 INTC_PRIO(EDMAC0, 5),
84 INTC_PRIO(EDMAC1, 5),
85 INTC_PRIO(EDMAC2, 5),
86};
87
5c37e025 88static struct intc_prio_reg prio_registers[] __initdata = {
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89 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
90 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
91 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
92 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
93 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
94 { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
ac919986 95#ifdef CONFIG_CPU_SUBTYPE_SH7710
6ef5fb2c 96 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
ac919986 97#endif
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98 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
99 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
100 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
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101};
102
103static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
104 priorities, NULL, prio_registers, NULL);
105
5c37e025 106static struct intc_vect vectors_irq[] __initdata = {
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107 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
108 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
109};
110
111static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
112 priorities, NULL, prio_registers, NULL);
113
114static struct resource rtc_resources[] = {
115 [0] = {
116 .start = 0xa413fec0,
117 .end = 0xa413fec0 + 0x1e,
118 .flags = IORESOURCE_IO,
119 },
120 [1] = {
121 .start = 20,
122 .flags = IORESOURCE_IRQ,
123 },
124 [2] = {
125 .start = 21,
126 .flags = IORESOURCE_IRQ,
127 },
128 [3] = {
129 .start = 22,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
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134static struct sh_rtc_platform_info rtc_info = {
135 .capabilities = RTC_CAP_4_DIGIT_YEAR,
136};
137
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138static struct platform_device rtc_device = {
139 .name = "sh-rtc",
140 .id = -1,
141 .num_resources = ARRAY_SIZE(rtc_resources),
142 .resource = rtc_resources,
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143 .dev = {
144 .platform_data = &rtc_info,
145 },
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146};
147
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148static struct plat_sci_port sci_platform_data[] = {
149 {
150 .mapbase = 0xa4400000,
151 .flags = UPF_BOOT_AUTOCONF,
152 .type = PORT_SCIF,
153 .irqs = { 52, 53, 55, 54 },
154 }, {
28b146c8 155 .mapbase = 0xa4410000,
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156 .flags = UPF_BOOT_AUTOCONF,
157 .type = PORT_SCIF,
158 .irqs = { 56, 57, 59, 58 },
159 }, {
160
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161 .flags = 0,
162 }
163};
164
165static struct platform_device sci_device = {
166 .name = "sh-sci",
167 .id = -1,
168 .dev = {
169 .platform_data = sci_platform_data,
170 },
171};
172
173static struct platform_device *sh7710_devices[] __initdata = {
174 &sci_device,
28b146c8 175 &rtc_device,
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176};
177
178static int __init sh7710_devices_setup(void)
179{
180 return platform_add_devices(sh7710_devices,
181 ARRAY_SIZE(sh7710_devices));
182}
183__initcall(sh7710_devices_setup);
9465a54f 184
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185void __init plat_irq_setup_pins(int mode)
186{
187 if (mode == IRQ_MODE_IRQ) {
188 register_intc_controller(&intc_desc_irq);
189 return;
190 }
191 BUG();
192}
9465a54f 193
90015c89 194void __init plat_irq_setup(void)
9465a54f 195{
28b146c8 196 register_intc_controller(&intc_desc);
9465a54f 197}
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