[deliverable/linux.git] / arch / sh / kernel / cpu / sh4 / probe.c

/*
 * arch/sh/kernel/cpu/sh4/probe.c
 *
 * CPU Subtype Probing for SH-4.
 *
 * Copyright (C) 2001 - 2007  Paul Mundt
 * Copyright (C) 2003  Richard Curnow
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/cache.h>

int __init detect_cpu_and_cache_system(void)
{
	unsigned long pvr, prr, cvr;
	unsigned long size;

	static unsigned long sizes[16] = {
		[1] = (1 << 12),
		[2] = (1 << 13),
		[4] = (1 << 14),
		[8] = (1 << 15),
		[9] = (1 << 16)
	};

	pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
	prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
	cvr = (ctrl_inl(CCN_CVR));

	/*
	 * Setup some sane SH-4 defaults for the icache
	 */
	boot_cpu_data.icache.way_incr		= (1 << 13);
	boot_cpu_data.icache.entry_shift	= 5;
	boot_cpu_data.icache.sets		= 256;
	boot_cpu_data.icache.ways		= 1;
	boot_cpu_data.icache.linesz		= L1_CACHE_BYTES;

	/*
	 * And again for the dcache ..
	 */
	boot_cpu_data.dcache.way_incr		= (1 << 14);
	boot_cpu_data.dcache.entry_shift	= 5;
	boot_cpu_data.dcache.sets		= 512;
	boot_cpu_data.dcache.ways		= 1;
	boot_cpu_data.dcache.linesz		= L1_CACHE_BYTES;

	/*
	 * Setup some generic flags we can probe on SH-4A parts
	 */
	if (((pvr >> 16) & 0xff) == 0x10) {
		if ((cvr & 0x10000000) == 0)
			boot_cpu_data.flags |= CPU_HAS_DSP;

		boot_cpu_data.flags |= CPU_HAS_LLSC;
	}

	/* FPU detection works for everyone */
	if ((cvr & 0x20000000) == 1)
		boot_cpu_data.flags |= CPU_HAS_FPU;

	/* Mask off the upper chip ID */
	pvr &= 0xffff;

	/*
	 * Probe the underlying processor version/revision and
	 * adjust cpu_data setup accordingly.
	 */
	switch (pvr) {
	case 0x205:
		boot_cpu_data.type = CPU_SH7750;
		boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
				   CPU_HAS_PERF_COUNTER;
		break;
	case 0x206:
		boot_cpu_data.type = CPU_SH7750S;
		boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
				   CPU_HAS_PERF_COUNTER;
		break;
	case 0x1100:
		boot_cpu_data.type = CPU_SH7751;
		boot_cpu_data.flags |= CPU_HAS_FPU;
		break;
	case 0x2001:
	case 0x2004:
		boot_cpu_data.type = CPU_SH7770;
		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;

		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
		break;
	case 0x2006:
	case 0x200A:
		if (prr == 0x61)
			boot_cpu_data.type = CPU_SH7781;
		else
			boot_cpu_data.type = CPU_SH7780;

		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;

		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
				   CPU_HAS_LLSC;
		break;
	case 0x3000:
	case 0x3003:
	case 0x3009:
		boot_cpu_data.type = CPU_SH7343;
		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;
		boot_cpu_data.flags |= CPU_HAS_LLSC;
		break;
	case 0x3004:
	case 0x3007:
		boot_cpu_data.type = CPU_SH7785;
		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;
		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
					  CPU_HAS_LLSC;
		break;
	case 0x3008:
		if (prr == 0xa0) {
			boot_cpu_data.type = CPU_SH7722;
			boot_cpu_data.icache.ways = 4;
			boot_cpu_data.dcache.ways = 4;
			boot_cpu_data.flags |= CPU_HAS_LLSC;
		}
		break;
	case 0x4000:	/* 1st cut */
	case 0x4001:	/* 2nd cut */
		boot_cpu_data.type = CPU_SHX3;
		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;
		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
					  CPU_HAS_LLSC;
		break;
	case 0x8000:
		boot_cpu_data.type = CPU_ST40RA;
		boot_cpu_data.flags |= CPU_HAS_FPU;
		break;
	case 0x8100:
		boot_cpu_data.type = CPU_ST40GX1;
		boot_cpu_data.flags |= CPU_HAS_FPU;
		break;
	case 0x700:
		boot_cpu_data.type = CPU_SH4_501;
		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;
		break;
	case 0x600:
		boot_cpu_data.type = CPU_SH4_202;
		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;
		boot_cpu_data.flags |= CPU_HAS_FPU;
		break;
	case 0x500 ... 0x501:
		switch (prr) {
		case 0x10:
			boot_cpu_data.type = CPU_SH7750R;
			break;
		case 0x11:
			boot_cpu_data.type = CPU_SH7751R;
			break;
		case 0x50 ... 0x5f:
			boot_cpu_data.type = CPU_SH7760;
			break;
		}

		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;

		boot_cpu_data.flags |= CPU_HAS_FPU;

		break;
	default:
		boot_cpu_data.type = CPU_SH_NONE;
		break;
	}

#ifdef CONFIG_SH_DIRECT_MAPPED
	boot_cpu_data.icache.ways = 1;
	boot_cpu_data.dcache.ways = 1;
#endif

#ifdef CONFIG_CPU_HAS_PTEA
	boot_cpu_data.flags |= CPU_HAS_PTEA;
#endif

	/*
	 * On anything that's not a direct-mapped cache, look to the CVR
	 * for I/D-cache specifics.
	 */
	if (boot_cpu_data.icache.ways > 1) {
		size = sizes[(cvr >> 20) & 0xf];
		boot_cpu_data.icache.way_incr	= (size >> 1);
		boot_cpu_data.icache.sets	= (size >> 6);

	}

	/* And the rest of the D-cache */
	if (boot_cpu_data.dcache.ways > 1) {
		size = sizes[(cvr >> 16) & 0xf];
		boot_cpu_data.dcache.way_incr	= (size >> 1);
		boot_cpu_data.dcache.sets	= (size >> 6);
	}

	/*
	 * Setup the L2 cache desc
	 *
	 * SH-4A's have an optional PIPT L2.
	 */
	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
		/*
		 * Size calculation is much more sensible
		 * than it is for the L1.
		 *
		 * Sizes are 128KB, 258KB, 512KB, and 1MB.
		 */
		size = (cvr & 0xf) << 17;

		BUG_ON(!size);

		boot_cpu_data.scache.way_incr		= (1 << 16);
		boot_cpu_data.scache.entry_shift	= 5;
		boot_cpu_data.scache.ways		= 4;
		boot_cpu_data.scache.linesz		= L1_CACHE_BYTES;

		boot_cpu_data.scache.entry_mask	=
			(boot_cpu_data.scache.way_incr -
			 boot_cpu_data.scache.linesz);

		boot_cpu_data.scache.sets	= size /
			(boot_cpu_data.scache.linesz *
			 boot_cpu_data.scache.ways);

		boot_cpu_data.scache.way_size	=
			(boot_cpu_data.scache.sets *
			 boot_cpu_data.scache.linesz);
	}

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/kernel/cpu/sh4/probe.c
	3	*
	4	* CPU Subtype Probing for SH-4.
	5	*
26fad19d	6	* Copyright (C) 2001 - 2007 Paul Mundt
1da177e4 LT	7	* Copyright (C) 2003 Richard Curnow
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
1da177e4	13	#include <linux/init.h>
11c19656	14	#include <linux/io.h>
1da177e4 LT	15	#include <asm/processor.h>
1da177e4 LT	16	#include <asm/cache.h>
1da177e4 LT	17
	18	int __init detect_cpu_and_cache_system(void)
	19	{
	20	unsigned long pvr, prr, cvr;
	21	unsigned long size;
	22
	23	static unsigned long sizes[16] = {
	24	[1] = (1 << 12),
	25	[2] = (1 << 13),
	26	[4] = (1 << 14),
	27	[8] = (1 << 15),
	28	[9] = (1 << 16)
	29	};
	30
72c35543	31	pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
1da177e4 LT	32	prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
	33	cvr = (ctrl_inl(CCN_CVR));
	34
	35	/*
	36	* Setup some sane SH-4 defaults for the icache
	37	*/
cb7af21f PM	38	boot_cpu_data.icache.way_incr = (1 << 13);
	39	boot_cpu_data.icache.entry_shift = 5;
	40	boot_cpu_data.icache.sets = 256;
	41	boot_cpu_data.icache.ways = 1;
	42	boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
1da177e4 LT	43
	44	/*
	45	* And again for the dcache ..
	46	*/
cb7af21f PM	47	boot_cpu_data.dcache.way_incr = (1 << 14);
	48	boot_cpu_data.dcache.entry_shift = 5;
	49	boot_cpu_data.dcache.sets = 512;
	50	boot_cpu_data.dcache.ways = 1;
	51	boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
1da177e4	52
72c35543	53	/*
26fad19d	54	* Setup some generic flags we can probe on SH-4A parts
72c35543 PM	55	*/
72c35543 PM	56	if (((pvr >> 16) & 0xff) == 0x10) {
72c35543	57	if ((cvr & 0x10000000) == 0)
cb7af21f	58	boot_cpu_data.flags \|= CPU_HAS_DSP;
72c35543	59
cb7af21f	60	boot_cpu_data.flags \|= CPU_HAS_LLSC;
72c35543 PM	61	}
	62
	63	/* FPU detection works for everyone */
	64	if ((cvr & 0x20000000) == 1)
cb7af21f	65	boot_cpu_data.flags \|= CPU_HAS_FPU;
72c35543 PM	66
	67	/* Mask off the upper chip ID */
	68	pvr &= 0xffff;
	69
1da177e4 LT	70	/*
	71	* Probe the underlying processor version/revision and
	72	* adjust cpu_data setup accordingly.
	73	*/
	74	switch (pvr) {
	75	case 0x205:
cb7af21f PM	76	boot_cpu_data.type = CPU_SH7750;
cb7af21f PM	77	boot_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|
9b3a53ab	78	CPU_HAS_PERF_COUNTER;
1da177e4 LT	79	break;
1da177e4 LT	80	case 0x206:
cb7af21f PM	81	boot_cpu_data.type = CPU_SH7750S;
cb7af21f PM	82	boot_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|
9b3a53ab	83	CPU_HAS_PERF_COUNTER;
1da177e4 LT	84	break;
1da177e4 LT	85	case 0x1100:
cb7af21f PM	86	boot_cpu_data.type = CPU_SH7751;
cb7af21f PM	87	boot_cpu_data.flags \|= CPU_HAS_FPU;
1da177e4	88	break;
5b19c908 PM	89	case 0x2001:
5b19c908 PM	90	case 0x2004:
cb7af21f PM	91	boot_cpu_data.type = CPU_SH7770;
	92	boot_cpu_data.icache.ways = 4;
	93	boot_cpu_data.dcache.ways = 4;
749cf486	94
cb7af21f	95	boot_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_LLSC;
5b19c908 PM	96	break;
	97	case 0x2006:
	98	case 0x200A:
	99	if (prr == 0x61)
cb7af21f	100	boot_cpu_data.type = CPU_SH7781;
5b19c908	101	else
cb7af21f	102	boot_cpu_data.type = CPU_SH7780;
749cf486	103
cb7af21f PM	104	boot_cpu_data.icache.ways = 4;
cb7af21f PM	105	boot_cpu_data.dcache.ways = 4;
749cf486	106
cb7af21f	107	boot_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_PERF_COUNTER \|
315bb968	108	CPU_HAS_LLSC;
5b19c908	109	break;
e5723e0e PM	110	case 0x3000:
e5723e0e PM	111	case 0x3003:
41504c39	112	case 0x3009:
cb7af21f PM	113	boot_cpu_data.type = CPU_SH7343;
	114	boot_cpu_data.icache.ways = 4;
	115	boot_cpu_data.dcache.ways = 4;
	116	boot_cpu_data.flags \|= CPU_HAS_LLSC;
e5723e0e	117	break;
32351a28 PM	118	case 0x3004:
32351a28 PM	119	case 0x3007:
cb7af21f PM	120	boot_cpu_data.type = CPU_SH7785;
	121	boot_cpu_data.icache.ways = 4;
	122	boot_cpu_data.dcache.ways = 4;
	123	boot_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_PERF_COUNTER \|
32351a28 PM	124	CPU_HAS_LLSC;
32351a28 PM	125	break;
41504c39 PM	126	case 0x3008:
41504c39 PM	127	if (prr == 0xa0) {
cb7af21f PM	128	boot_cpu_data.type = CPU_SH7722;
	129	boot_cpu_data.icache.ways = 4;
	130	boot_cpu_data.dcache.ways = 4;
	131	boot_cpu_data.flags \|= CPU_HAS_LLSC;
41504c39 PM	132	}
41504c39 PM	133	break;
2b1bd1ac PM	134	case 0x4000: /* 1st cut */
2b1bd1ac PM	135	case 0x4001: /* 2nd cut */
cb7af21f PM	136	boot_cpu_data.type = CPU_SHX3;
	137	boot_cpu_data.icache.ways = 4;
	138	boot_cpu_data.dcache.ways = 4;
	139	boot_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_PERF_COUNTER \|
2b1bd1ac PM	140	CPU_HAS_LLSC;
2b1bd1ac PM	141	break;
1da177e4	142	case 0x8000:
cb7af21f PM	143	boot_cpu_data.type = CPU_ST40RA;
cb7af21f PM	144	boot_cpu_data.flags \|= CPU_HAS_FPU;
1da177e4 LT	145	break;
1da177e4 LT	146	case 0x8100:
cb7af21f PM	147	boot_cpu_data.type = CPU_ST40GX1;
cb7af21f PM	148	boot_cpu_data.flags \|= CPU_HAS_FPU;
1da177e4 LT	149	break;
1da177e4 LT	150	case 0x700:
cb7af21f PM	151	boot_cpu_data.type = CPU_SH4_501;
	152	boot_cpu_data.icache.ways = 2;
	153	boot_cpu_data.dcache.ways = 2;
1da177e4 LT	154	break;
1da177e4 LT	155	case 0x600:
cb7af21f PM	156	boot_cpu_data.type = CPU_SH4_202;
	157	boot_cpu_data.icache.ways = 2;
	158	boot_cpu_data.dcache.ways = 2;
	159	boot_cpu_data.flags \|= CPU_HAS_FPU;
1da177e4 LT	160	break;
	161	case 0x500 ... 0x501:
	162	switch (prr) {
73388cc7	163	case 0x10:
cb7af21f	164	boot_cpu_data.type = CPU_SH7750R;
73388cc7 PM	165	break;
73388cc7 PM	166	case 0x11:
cb7af21f	167	boot_cpu_data.type = CPU_SH7751R;
73388cc7 PM	168	break;
73388cc7 PM	169	case 0x50 ... 0x5f:
cb7af21f	170	boot_cpu_data.type = CPU_SH7760;
73388cc7	171	break;
1da177e4 LT	172	}
1da177e4 LT	173
cb7af21f PM	174	boot_cpu_data.icache.ways = 2;
cb7af21f PM	175	boot_cpu_data.dcache.ways = 2;
1da177e4	176
cb7af21f	177	boot_cpu_data.flags \|= CPU_HAS_FPU;
749cf486	178
1da177e4 LT	179	break;
1da177e4 LT	180	default:
cb7af21f	181	boot_cpu_data.type = CPU_SH_NONE;
1da177e4 LT	182	break;
	183	}
	184
b638d0b9	185	#ifdef CONFIG_SH_DIRECT_MAPPED
cb7af21f PM	186	boot_cpu_data.icache.ways = 1;
cb7af21f PM	187	boot_cpu_data.dcache.ways = 1;
11c19656 PM	188	#endif
	189
	190	#ifdef CONFIG_CPU_HAS_PTEA
cb7af21f	191	boot_cpu_data.flags \|= CPU_HAS_PTEA;
b638d0b9 RC	192	#endif
b638d0b9 RC	193
1da177e4 LT	194	/*
	195	* On anything that's not a direct-mapped cache, look to the CVR
	196	* for I/D-cache specifics.
	197	*/
cb7af21f	198	if (boot_cpu_data.icache.ways > 1) {
1da177e4	199	size = sizes[(cvr >> 20) & 0xf];
cb7af21f PM	200	boot_cpu_data.icache.way_incr = (size >> 1);
cb7af21f PM	201	boot_cpu_data.icache.sets = (size >> 6);
d15f4560	202
1da177e4 LT	203	}
1da177e4 LT	204
d15f4560	205	/* And the rest of the D-cache */
cb7af21f	206	if (boot_cpu_data.dcache.ways > 1) {
1da177e4	207	size = sizes[(cvr >> 16) & 0xf];
cb7af21f PM	208	boot_cpu_data.dcache.way_incr = (size >> 1);
cb7af21f PM	209	boot_cpu_data.dcache.sets = (size >> 6);
1da177e4 LT	210	}
1da177e4 LT	211
72c35543 PM	212	/*
	213	* Setup the L2 cache desc
	214	*
	215	* SH-4A's have an optional PIPT L2.
	216	*/
cb7af21f	217	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
72c35543 PM	218	/*
	219	* Size calculation is much more sensible
	220	* than it is for the L1.
	221	*
	222	* Sizes are 128KB, 258KB, 512KB, and 1MB.
	223	*/
	224	size = (cvr & 0xf) << 17;
	225
	226	BUG_ON(!size);
	227
cb7af21f PM	228	boot_cpu_data.scache.way_incr = (1 << 16);
	229	boot_cpu_data.scache.entry_shift = 5;
	230	boot_cpu_data.scache.ways = 4;
	231	boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
11c19656	232
cb7af21f PM	233	boot_cpu_data.scache.entry_mask =
	234	(boot_cpu_data.scache.way_incr -
	235	boot_cpu_data.scache.linesz);
11c19656	236
cb7af21f PM	237	boot_cpu_data.scache.sets = size /
	238	(boot_cpu_data.scache.linesz *
	239	boot_cpu_data.scache.ways);
11c19656	240
cb7af21f PM	241	boot_cpu_data.scache.way_size =
	242	(boot_cpu_data.scache.sets *
	243	boot_cpu_data.scache.linesz);
72c35543 PM	244	}
72c35543 PM	245
1da177e4 LT	246	return 0;
1da177e4 LT	247	}