[deliverable/linux.git] / arch / sh / kernel / cpu / sh4 / probe.c

/*
 * arch/sh/kernel/cpu/sh4/probe.c
 *
 * CPU Subtype Probing for SH-4.
 *
 * Copyright (C) 2001, 2002, 2003, 2004  Paul Mundt
 * Copyright (C) 2003  Richard Curnow
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/io.h>

int __init detect_cpu_and_cache_system(void)
{
	unsigned long pvr, prr, cvr;
	unsigned long size;

	static unsigned long sizes[16] = {
		[1] = (1 << 12),
		[2] = (1 << 13),
		[4] = (1 << 14),
		[8] = (1 << 15),
		[9] = (1 << 16)
	};

	pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
	prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
	cvr = (ctrl_inl(CCN_CVR));

	/*
	 * Setup some sane SH-4 defaults for the icache
	 */
	cpu_data->icache.way_incr	= (1 << 13);
	cpu_data->icache.entry_shift	= 5;
	cpu_data->icache.entry_mask	= 0x1fe0;
	cpu_data->icache.sets		= 256;
	cpu_data->icache.ways		= 1;
	cpu_data->icache.linesz		= L1_CACHE_BYTES;

	/*
	 * And again for the dcache ..
	 */
	cpu_data->dcache.way_incr	= (1 << 14);
	cpu_data->dcache.entry_shift	= 5;
	cpu_data->dcache.entry_mask	= 0x3fe0;
	cpu_data->dcache.sets		= 512;
	cpu_data->dcache.ways		= 1;
	cpu_data->dcache.linesz		= L1_CACHE_BYTES;

	/* Set the FPU flag, virtually all SH-4's have one */
	cpu_data->flags |= CPU_HAS_FPU;

	/*
	 * Probe the underlying processor version/revision and
	 * adjust cpu_data setup accordingly.
	 */
	switch (pvr) {
	case 0x205:
		cpu_data->type = CPU_SH7750;
		cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
		break;
	case 0x206:
		cpu_data->type = CPU_SH7750S;
		cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
		break;
	case 0x1100:
		cpu_data->type = CPU_SH7751;
		break;
	case 0x2000:
		cpu_data->type = CPU_SH73180;
		cpu_data->icache.ways = 4;
		cpu_data->dcache.ways = 4;
		cpu_data->flags &= ~CPU_HAS_FPU;
		break;
	case 0x8000:
		cpu_data->type = CPU_ST40RA;
		break;
	case 0x8100:
		cpu_data->type = CPU_ST40GX1;
		break;
	case 0x700:
		cpu_data->type = CPU_SH4_501;
		cpu_data->icache.ways = 2;
		cpu_data->dcache.ways = 2;

		/* No FPU on the SH4-500 series.. */
		cpu_data->flags &= ~CPU_HAS_FPU;
		break;
	case 0x600:
		cpu_data->type = CPU_SH4_202;
		cpu_data->icache.ways = 2;
		cpu_data->dcache.ways = 2;
		break;
	case 0x500 ... 0x501:
		switch (prr) {
		case 0x10:
			cpu_data->type = CPU_SH7750R;
			break;
		case 0x11:
			cpu_data->type = CPU_SH7751R;
			break;
		case 0x50 ... 0x5f:
			cpu_data->type = CPU_SH7760;
			break;
		}

		cpu_data->icache.ways = 2;
		cpu_data->dcache.ways = 2;

		break;
	default:
		cpu_data->type = CPU_SH_NONE;
		break;
	}

#ifdef CONFIG_SH_DIRECT_MAPPED
	cpu_data->icache.ways = 1;
	cpu_data->dcache.ways = 1;
#endif

	/*
	 * On anything that's not a direct-mapped cache, look to the CVR
	 * for I/D-cache specifics.
	 */
	if (cpu_data->icache.ways > 1) {
		size = sizes[(cvr >> 20) & 0xf];
		cpu_data->icache.way_incr	= (size >> 1);
		cpu_data->icache.sets		= (size >> 6);
		cpu_data->icache.entry_mask	=
			(cpu_data->icache.way_incr - (1 << 5));
	}

	cpu_data->icache.way_size = cpu_data->icache.sets *
				    cpu_data->icache.linesz;

	if (cpu_data->dcache.ways > 1) {
		size = sizes[(cvr >> 16) & 0xf];
		cpu_data->dcache.way_incr	= (size >> 1);
		cpu_data->dcache.sets		= (size >> 6);
		cpu_data->dcache.entry_mask	=
			(cpu_data->dcache.way_incr - (1 << 5));
	}

	cpu_data->dcache.way_size = cpu_data->dcache.sets *
				    cpu_data->dcache.linesz;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/kernel/cpu/sh4/probe.c
	3	*
	4	* CPU Subtype Probing for SH-4.
	5	*
	6	* Copyright (C) 2001, 2002, 2003, 2004 Paul Mundt
	7	* Copyright (C) 2003 Richard Curnow
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <asm/processor.h>
	16	#include <asm/cache.h>
	17	#include <asm/io.h>
	18
	19	int __init detect_cpu_and_cache_system(void)
	20	{
	21	unsigned long pvr, prr, cvr;
	22	unsigned long size;
	23
	24	static unsigned long sizes[16] = {
	25	[1] = (1 << 12),
	26	[2] = (1 << 13),
	27	[4] = (1 << 14),
	28	[8] = (1 << 15),
	29	[9] = (1 << 16)
	30	};
	31
	32	pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
	33	prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
	34	cvr = (ctrl_inl(CCN_CVR));
	35
	36	/*
	37	* Setup some sane SH-4 defaults for the icache
	38	*/
	39	cpu_data->icache.way_incr = (1 << 13);
	40	cpu_data->icache.entry_shift = 5;
	41	cpu_data->icache.entry_mask = 0x1fe0;
	42	cpu_data->icache.sets = 256;
	43	cpu_data->icache.ways = 1;
	44	cpu_data->icache.linesz = L1_CACHE_BYTES;
	45
	46	/*
	47	* And again for the dcache ..
	48	*/
	49	cpu_data->dcache.way_incr = (1 << 14);
	50	cpu_data->dcache.entry_shift = 5;
	51	cpu_data->dcache.entry_mask = 0x3fe0;
	52	cpu_data->dcache.sets = 512;
	53	cpu_data->dcache.ways = 1;
	54	cpu_data->dcache.linesz = L1_CACHE_BYTES;
	55
	56	/* Set the FPU flag, virtually all SH-4's have one */
	57	cpu_data->flags \|= CPU_HAS_FPU;
	58
	59	/*
	60	* Probe the underlying processor version/revision and
	61	* adjust cpu_data setup accordingly.
	62	*/
	63	switch (pvr) {
	64	case 0x205:
65	cpu_data->type = CPU_SH7750;
66	cpu_data->flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_PERF_COUNTER;
67	break;
68	case 0x206:
69	cpu_data->type = CPU_SH7750S;
70	cpu_data->flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_PERF_COUNTER;
71	break;
72	case 0x1100:
73	cpu_data->type = CPU_SH7751;
74	break;
75	case 0x2000:
76	cpu_data->type = CPU_SH73180;
77	cpu_data->icache.ways = 4;
78	cpu_data->dcache.ways = 4;
79	cpu_data->flags &= ~CPU_HAS_FPU;
80	break;
81	case 0x8000:
82	cpu_data->type = CPU_ST40RA;
83	break;
84	case 0x8100:
85	cpu_data->type = CPU_ST40GX1;
86	break;
87	case 0x700:
88	cpu_data->type = CPU_SH4_501;
89	cpu_data->icache.ways = 2;
90	cpu_data->dcache.ways = 2;
91
92	/* No FPU on the SH4-500 series.. */
93	cpu_data->flags &= ~CPU_HAS_FPU;
94	break;
95	case 0x600:
96	cpu_data->type = CPU_SH4_202;
97	cpu_data->icache.ways = 2;
98	cpu_data->dcache.ways = 2;
99	break;
100	case 0x500 ... 0x501:
101	switch (prr) {
73388cc7 PM	102	case 0x10:
	103	cpu_data->type = CPU_SH7750R;
	104	break;
	105	case 0x11:
	106	cpu_data->type = CPU_SH7751R;
	107	break;
	108	case 0x50 ... 0x5f:
	109	cpu_data->type = CPU_SH7760;
	110	break;
1da177e4 LT	111	}
	112
	113	cpu_data->icache.ways = 2;
	114	cpu_data->dcache.ways = 2;
	115
	116	break;
	117	default:
	118	cpu_data->type = CPU_SH_NONE;
	119	break;
	120	}
	121
b638d0b9 RC	122	#ifdef CONFIG_SH_DIRECT_MAPPED
	123	cpu_data->icache.ways = 1;
	124	cpu_data->dcache.ways = 1;
	125	#endif
	126
1da177e4 LT	127	/*
	128	* On anything that's not a direct-mapped cache, look to the CVR
	129	* for I/D-cache specifics.
	130	*/
	131	if (cpu_data->icache.ways > 1) {
	132	size = sizes[(cvr >> 20) & 0xf];
	133	cpu_data->icache.way_incr = (size >> 1);
	134	cpu_data->icache.sets = (size >> 6);
	135	cpu_data->icache.entry_mask =
	136	(cpu_data->icache.way_incr - (1 << 5));
	137	}
	138
b638d0b9 RC	139	cpu_data->icache.way_size = cpu_data->icache.sets *
	140	cpu_data->icache.linesz;
	141
1da177e4 LT	142	if (cpu_data->dcache.ways > 1) {
	143	size = sizes[(cvr >> 16) & 0xf];
	144	cpu_data->dcache.way_incr = (size >> 1);
	145	cpu_data->dcache.sets = (size >> 6);
	146	cpu_data->dcache.entry_mask =
	147	(cpu_data->dcache.way_incr - (1 << 5));
	148	}
	149
b638d0b9 RC	150	cpu_data->dcache.way_size = cpu_data->dcache.sets *
	151	cpu_data->dcache.linesz;
	152
1da177e4 LT	153	return 0;
	154	}
	155