[deliverable/linux.git] / arch / sh / kernel / cpu / sh4 / probe.c

/*
 * arch/sh/kernel/cpu/sh4/probe.c
 *
 * CPU Subtype Probing for SH-4.
 *
 * Copyright (C) 2001 - 2007  Paul Mundt
 * Copyright (C) 2003  Richard Curnow
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/cache.h>

void cpu_probe(void)
{
	unsigned long pvr, prr, cvr;
	unsigned long size;

	static unsigned long sizes[16] = {
		[1] = (1 << 12),
		[2] = (1 << 13),
		[4] = (1 << 14),
		[8] = (1 << 15),
		[9] = (1 << 16)
	};

	pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
	prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
	cvr = (__raw_readl(CCN_CVR));

	/*
	 * Setup some sane SH-4 defaults for the icache
	 */
	boot_cpu_data.icache.way_incr		= (1 << 13);
	boot_cpu_data.icache.entry_shift	= 5;
	boot_cpu_data.icache.sets		= 256;
	boot_cpu_data.icache.ways		= 1;
	boot_cpu_data.icache.linesz		= L1_CACHE_BYTES;

	/*
	 * And again for the dcache ..
	 */
	boot_cpu_data.dcache.way_incr		= (1 << 14);
	boot_cpu_data.dcache.entry_shift	= 5;
	boot_cpu_data.dcache.sets		= 512;
	boot_cpu_data.dcache.ways		= 1;
	boot_cpu_data.dcache.linesz		= L1_CACHE_BYTES;

	/* We don't know the chip cut */
	boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;

	/*
	 * Setup some generic flags we can probe on SH-4A parts
	 */
	if (((pvr >> 16) & 0xff) == 0x10) {
		boot_cpu_data.family = CPU_FAMILY_SH4A;

		if ((cvr & 0x10000000) == 0) {
			boot_cpu_data.flags |= CPU_HAS_DSP;
			boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
		}

		boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
		boot_cpu_data.cut_major = pvr & 0x7f;

		boot_cpu_data.icache.ways = 4;
		boot_cpu_data.dcache.ways = 4;
	} else {
		/* And some SH-4 defaults.. */
		boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU;
		boot_cpu_data.family = CPU_FAMILY_SH4;
	}

	/* FPU detection works for almost everyone */
	if ((cvr & 0x20000000))
		boot_cpu_data.flags |= CPU_HAS_FPU;

	/* Mask off the upper chip ID */
	pvr &= 0xffff;

	/*
	 * Probe the underlying processor version/revision and
	 * adjust cpu_data setup accordingly.
	 */
	switch (pvr) {
	case 0x205:
		boot_cpu_data.type = CPU_SH7750;
		boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
				       CPU_HAS_PERF_COUNTER;
		break;
	case 0x206:
		boot_cpu_data.type = CPU_SH7750S;
		boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
				       CPU_HAS_PERF_COUNTER;
		break;
	case 0x1100:
		boot_cpu_data.type = CPU_SH7751;
		break;
	case 0x2001:
	case 0x2004:
		boot_cpu_data.type = CPU_SH7770;
		break;
	case 0x2006:
	case 0x200A:
		if (prr == 0x61)
			boot_cpu_data.type = CPU_SH7781;
		else if (prr == 0xa1)
			boot_cpu_data.type = CPU_SH7763;
		else
			boot_cpu_data.type = CPU_SH7780;

		break;
	case 0x3000:
	case 0x3003:
	case 0x3009:
		boot_cpu_data.type = CPU_SH7343;
		break;
	case 0x3004:
	case 0x3007:
		boot_cpu_data.type = CPU_SH7785;
		break;
	case 0x4004:
	case 0x4005:
		boot_cpu_data.type = CPU_SH7786;
		boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
		break;
	case 0x3008:
		switch (prr) {
		case 0x50:
		case 0x51:
			boot_cpu_data.type = CPU_SH7723;
			boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
			break;
		case 0x70:
			boot_cpu_data.type = CPU_SH7366;
			break;
		case 0xa0:
		case 0xa1:
			boot_cpu_data.type = CPU_SH7722;
			break;
		}
		break;
	case 0x300b:
		switch (prr) {
		case 0x20:
			boot_cpu_data.type = CPU_SH7724;
			boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
			break;
		case 0x10:
		case 0x11:
			boot_cpu_data.type = CPU_SH7757;
			break;
		case 0xd0:
		case 0x40: /* yon-ten-go */
			boot_cpu_data.type = CPU_SH7372;
			break;
		case 0xE0: /* 0x4E0 */
			boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
			break;

		}
		break;
	case 0x4000:	/* 1st cut */
	case 0x4001:	/* 2nd cut */
		boot_cpu_data.type = CPU_SHX3;
		break;
	case 0x700:
		boot_cpu_data.type = CPU_SH4_501;
		boot_cpu_data.flags &= ~CPU_HAS_FPU;
		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;
		break;
	case 0x600:
		boot_cpu_data.type = CPU_SH4_202;
		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;
		break;
	case 0x500 ... 0x501:
		switch (prr) {
		case 0x10:
			boot_cpu_data.type = CPU_SH7750R;
			break;
		case 0x11:
			boot_cpu_data.type = CPU_SH7751R;
			break;
		case 0x50 ... 0x5f:
			boot_cpu_data.type = CPU_SH7760;
			break;
		}

		boot_cpu_data.icache.ways = 2;
		boot_cpu_data.dcache.ways = 2;

		break;
	}

	/*
	 * On anything that's not a direct-mapped cache, look to the CVR
	 * for I/D-cache specifics.
	 */
	if (boot_cpu_data.icache.ways > 1) {
		size = sizes[(cvr >> 20) & 0xf];
		boot_cpu_data.icache.way_incr	= (size >> 1);
		boot_cpu_data.icache.sets	= (size >> 6);

	}

	/* And the rest of the D-cache */
	if (boot_cpu_data.dcache.ways > 1) {
		size = sizes[(cvr >> 16) & 0xf];
		boot_cpu_data.dcache.way_incr	= (size >> 1);
		boot_cpu_data.dcache.sets	= (size >> 6);
	}

	/*
	 * SH-4A's have an optional PIPT L2.
	 */
	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
		/*
		 * Verify that it really has something hooked up, this
		 * is the safety net for CPUs that have optional L2
		 * support yet do not implement it.
		 */
		if ((cvr & 0xf) == 0)
			boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
		else {
			/*
			 * Silicon and specifications have clearly never
			 * met..
			 */
			cvr ^= 0xf;

			/*
			 * Size calculation is much more sensible
			 * than it is for the L1.
			 *
			 * Sizes are 128KB, 256KB, 512KB, and 1MB.
			 */
			size = (cvr & 0xf) << 17;

			boot_cpu_data.scache.way_incr		= (1 << 16);
			boot_cpu_data.scache.entry_shift	= 5;
			boot_cpu_data.scache.ways		= 4;
			boot_cpu_data.scache.linesz		= L1_CACHE_BYTES;

			boot_cpu_data.scache.entry_mask	=
				(boot_cpu_data.scache.way_incr -
				 boot_cpu_data.scache.linesz);

			boot_cpu_data.scache.sets	= size /
				(boot_cpu_data.scache.linesz *
				 boot_cpu_data.scache.ways);

			boot_cpu_data.scache.way_size	=
				(boot_cpu_data.scache.sets *
				 boot_cpu_data.scache.linesz);
		}
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/kernel/cpu/sh4/probe.c
	3	*
	4	* CPU Subtype Probing for SH-4.
	5	*
26fad19d	6	* Copyright (C) 2001 - 2007 Paul Mundt
1da177e4 LT	7	* Copyright (C) 2003 Richard Curnow
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
1da177e4	13	#include <linux/init.h>
11c19656	14	#include <linux/io.h>
1da177e4 LT	15	#include <asm/processor.h>
1da177e4 LT	16	#include <asm/cache.h>
1da177e4	17
4603f53a	18	void cpu_probe(void)
1da177e4 LT	19	{
	20	unsigned long pvr, prr, cvr;
	21	unsigned long size;
	22
	23	static unsigned long sizes[16] = {
	24	[1] = (1 << 12),
	25	[2] = (1 << 13),
	26	[4] = (1 << 14),
	27	[8] = (1 << 15),
	28	[9] = (1 << 16)
	29	};
	30
9d56dd3b PM	31	pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
	32	prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
	33	cvr = (__raw_readl(CCN_CVR));
1da177e4 LT	34
	35	/*
	36	* Setup some sane SH-4 defaults for the icache
	37	*/
cb7af21f PM	38	boot_cpu_data.icache.way_incr = (1 << 13);
	39	boot_cpu_data.icache.entry_shift = 5;
	40	boot_cpu_data.icache.sets = 256;
	41	boot_cpu_data.icache.ways = 1;
	42	boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
1da177e4 LT	43
	44	/*
	45	* And again for the dcache ..
	46	*/
cb7af21f PM	47	boot_cpu_data.dcache.way_incr = (1 << 14);
	48	boot_cpu_data.dcache.entry_shift = 5;
	49	boot_cpu_data.dcache.sets = 512;
	50	boot_cpu_data.dcache.ways = 1;
	51	boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
1da177e4	52
068f5914 PM	53	/* We don't know the chip cut */
	54	boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
	55
72c35543	56	/*
26fad19d	57	* Setup some generic flags we can probe on SH-4A parts
72c35543	58	*/
068f5914	59	if (((pvr >> 16) & 0xff) == 0x10) {
e82da214 PM	60	boot_cpu_data.family = CPU_FAMILY_SH4A;
	61
	62	if ((cvr & 0x10000000) == 0) {
cb7af21f	63	boot_cpu_data.flags \|= CPU_HAS_DSP;
e82da214 PM	64	boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
e82da214 PM	65	}
72c35543	66
0bf8513e	67	boot_cpu_data.flags \|= CPU_HAS_LLSC \| CPU_HAS_PERF_COUNTER;
068f5914	68	boot_cpu_data.cut_major = pvr & 0x7f;
0bf8513e PM	69
	70	boot_cpu_data.icache.ways = 4;
	71	boot_cpu_data.dcache.ways = 4;
	72	} else {
	73	/* And some SH-4 defaults.. */
bdc27300	74	boot_cpu_data.flags \|= CPU_HAS_PTEA \| CPU_HAS_FPU;
e82da214	75	boot_cpu_data.family = CPU_FAMILY_SH4;
72c35543 PM	76	}
72c35543 PM	77
bdc27300	78	/* FPU detection works for almost everyone */
0bf8513e	79	if ((cvr & 0x20000000))
cb7af21f	80	boot_cpu_data.flags \|= CPU_HAS_FPU;
72c35543 PM	81
	82	/* Mask off the upper chip ID */
	83	pvr &= 0xffff;
	84
1da177e4 LT	85	/*
	86	* Probe the underlying processor version/revision and
	87	* adjust cpu_data setup accordingly.
	88	*/
	89	switch (pvr) {
	90	case 0x205:
cb7af21f	91	boot_cpu_data.type = CPU_SH7750;
0bf8513e PM	92	boot_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \|
0bf8513e PM	93	CPU_HAS_PERF_COUNTER;
1da177e4 LT	94	break;
1da177e4 LT	95	case 0x206:
cb7af21f	96	boot_cpu_data.type = CPU_SH7750S;
0bf8513e PM	97	boot_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \|
0bf8513e PM	98	CPU_HAS_PERF_COUNTER;
1da177e4 LT	99	break;
1da177e4 LT	100	case 0x1100:
cb7af21f	101	boot_cpu_data.type = CPU_SH7751;
1da177e4	102	break;
5b19c908 PM	103	case 0x2001:
5b19c908 PM	104	case 0x2004:
cb7af21f	105	boot_cpu_data.type = CPU_SH7770;
5b19c908 PM	106	break;
	107	case 0x2006:
	108	case 0x200A:
	109	if (prr == 0x61)
cb7af21f	110	boot_cpu_data.type = CPU_SH7781;
7d740a06 YS	111	else if (prr == 0xa1)
7d740a06 YS	112	boot_cpu_data.type = CPU_SH7763;
5b19c908	113	else
cb7af21f	114	boot_cpu_data.type = CPU_SH7780;
749cf486	115
5b19c908	116	break;
e5723e0e PM	117	case 0x3000:
e5723e0e PM	118	case 0x3003:
41504c39	119	case 0x3009:
cb7af21f	120	boot_cpu_data.type = CPU_SH7343;
e5723e0e	121	break;
32351a28 PM	122	case 0x3004:
32351a28 PM	123	case 0x3007:
cb7af21f	124	boot_cpu_data.type = CPU_SH7785;
32351a28	125	break;
55ba99eb	126	case 0x4004:
7f33306e	127	case 0x4005:
55ba99eb	128	boot_cpu_data.type = CPU_SH7786;
0bf8513e	129	boot_cpu_data.flags \|= CPU_HAS_PTEAEX \| CPU_HAS_L2_CACHE;
55ba99eb	130	break;
41504c39	131	case 0x3008:
178dd0cd PM	132	switch (prr) {
178dd0cd PM	133	case 0x50:
b76baf4c	134	case 0x51:
178dd0cd	135	boot_cpu_data.type = CPU_SH7723;
0bf8513e	136	boot_cpu_data.flags \|= CPU_HAS_L2_CACHE;
178dd0cd PM	137	break;
178dd0cd PM	138	case 0x70:
9109a30e	139	boot_cpu_data.type = CPU_SH7366;
178dd0cd PM	140	break;
	141	case 0xa0:
	142	case 0xa1:
	143	boot_cpu_data.type = CPU_SH7722;
	144	break;
9109a30e	145	}
41504c39	146	break;
0207a2ef	147	case 0x300b:
c01f0f1a YS	148	switch (prr) {
c01f0f1a YS	149	case 0x20:
b37c7c66	150	boot_cpu_data.type = CPU_SH7724;
c01f0f1a YS	151	boot_cpu_data.flags \|= CPU_HAS_L2_CACHE;
c01f0f1a YS	152	break;
e81e5ce2	153	case 0x10:
538e7906	154	case 0x11:
c01f0f1a YS	155	boot_cpu_data.type = CPU_SH7757;
c01f0f1a YS	156	break;
fac6c2a8 MD	157	case 0xd0:
	158	case 0x40: /* yon-ten-go */
	159	boot_cpu_data.type = CPU_SH7372;
	160	break;
fea88a0c NI	161	case 0xE0: /* 0x4E0 */
	162	boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
	163	break;
fac6c2a8	164
c01f0f1a	165	}
0207a2ef	166	break;
2b1bd1ac PM	167	case 0x4000: /* 1st cut */
2b1bd1ac PM	168	case 0x4001: /* 2nd cut */
cb7af21f	169	boot_cpu_data.type = CPU_SHX3;
2b1bd1ac	170	break;
1da177e4	171	case 0x700:
cb7af21f	172	boot_cpu_data.type = CPU_SH4_501;
bdc27300	173	boot_cpu_data.flags &= ~CPU_HAS_FPU;
cb7af21f PM	174	boot_cpu_data.icache.ways = 2;
cb7af21f PM	175	boot_cpu_data.dcache.ways = 2;
1da177e4 LT	176	break;
1da177e4 LT	177	case 0x600:
cb7af21f PM	178	boot_cpu_data.type = CPU_SH4_202;
	179	boot_cpu_data.icache.ways = 2;
	180	boot_cpu_data.dcache.ways = 2;
1da177e4 LT	181	break;
	182	case 0x500 ... 0x501:
	183	switch (prr) {
73388cc7	184	case 0x10:
cb7af21f	185	boot_cpu_data.type = CPU_SH7750R;
73388cc7 PM	186	break;
73388cc7 PM	187	case 0x11:
cb7af21f	188	boot_cpu_data.type = CPU_SH7751R;
73388cc7 PM	189	break;
73388cc7 PM	190	case 0x50 ... 0x5f:
cb7af21f	191	boot_cpu_data.type = CPU_SH7760;
73388cc7	192	break;
1da177e4 LT	193	}
1da177e4 LT	194
cb7af21f PM	195	boot_cpu_data.icache.ways = 2;
cb7af21f PM	196	boot_cpu_data.dcache.ways = 2;
1da177e4	197
1da177e4 LT	198	break;
	199	}
	200
	201	/*
	202	* On anything that's not a direct-mapped cache, look to the CVR
	203	* for I/D-cache specifics.
	204	*/
cb7af21f	205	if (boot_cpu_data.icache.ways > 1) {
1da177e4	206	size = sizes[(cvr >> 20) & 0xf];
cb7af21f PM	207	boot_cpu_data.icache.way_incr = (size >> 1);
cb7af21f PM	208	boot_cpu_data.icache.sets = (size >> 6);
d15f4560	209
1da177e4 LT	210	}
1da177e4 LT	211
d15f4560	212	/* And the rest of the D-cache */
cb7af21f	213	if (boot_cpu_data.dcache.ways > 1) {
1da177e4	214	size = sizes[(cvr >> 16) & 0xf];
cb7af21f PM	215	boot_cpu_data.dcache.way_incr = (size >> 1);
cb7af21f PM	216	boot_cpu_data.dcache.sets = (size >> 6);
1da177e4 LT	217	}
1da177e4 LT	218
72c35543	219	/*
72c35543 PM	220	* SH-4A's have an optional PIPT L2.
72c35543 PM	221	*/
cb7af21f	222	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
72c35543	223	/*
7863d3f7 PM	224	* Verify that it really has something hooked up, this
	225	* is the safety net for CPUs that have optional L2
	226	* support yet do not implement it.
72c35543	227	*/
7863d3f7 PM	228	if ((cvr & 0xf) == 0)
	229	boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
	230	else {
	231	/*
	232	* Silicon and specifications have clearly never
	233	* met..
	234	*/
	235	cvr ^= 0xf;
72c35543	236
7863d3f7 PM	237	/*
	238	* Size calculation is much more sensible
	239	* than it is for the L1.
	240	*
88f73d22	241	* Sizes are 128KB, 256KB, 512KB, and 1MB.
7863d3f7 PM	242	*/
7863d3f7 PM	243	size = (cvr & 0xf) << 17;
72c35543	244
7863d3f7 PM	245	boot_cpu_data.scache.way_incr = (1 << 16);
	246	boot_cpu_data.scache.entry_shift = 5;
	247	boot_cpu_data.scache.ways = 4;
	248	boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
11c19656	249
7863d3f7 PM	250	boot_cpu_data.scache.entry_mask =
	251	(boot_cpu_data.scache.way_incr -
	252	boot_cpu_data.scache.linesz);
11c19656	253
7863d3f7 PM	254	boot_cpu_data.scache.sets = size /
	255	(boot_cpu_data.scache.linesz *
	256	boot_cpu_data.scache.ways);
11c19656	257
7863d3f7 PM	258	boot_cpu_data.scache.way_size =
	259	(boot_cpu_data.scache.sets *
	260	boot_cpu_data.scache.linesz);
	261	}
72c35543	262	}
1da177e4	263	}