[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7343.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
 *
 * SH7343 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>

/* SH7343 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

	return clk->parent->rate * mult;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
       DIV4_SIUA, DIV4_SIUB, DIV4_NR };

#define DIV4(_reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

#define MSTP(_parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)

enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
       MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
       MSTP109, MSTP108, MSTP100,
       MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
       MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
	[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),

	[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
	[MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
	[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
	[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
	[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("rclk", &r_clk),
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("dll_clk", &dll_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
	CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),

	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP32 clocks */
	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
	CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
	{
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP007],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP006],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP005],
	}, {
		/* SCIF3 */
		.dev_id		= "sh-sci.3",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP004],
	},
	CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
	CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
	CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
	CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
	CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
	CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
	CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
	CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
	CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
	CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
bc49b6ea MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7343.c
	3	*
	4	* SH7343 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
098ec49b	24	#include <asm/clkdev.h>
bc49b6ea MD	25	#include <asm/clock.h>
	26
	27	/* SH7343 registers */
	28	#define FRQCR 0xa4150000
	29	#define VCLKCR 0xa4150004
	30	#define SCLKACR 0xa4150008
	31	#define SCLKBCR 0xa415000c
	32	#define PLLCR 0xa4150024
	33	#define MSTPCR0 0xa4150030
	34	#define MSTPCR1 0xa4150034
	35	#define MSTPCR2 0xa4150038
	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
bc49b6ea MD	40	.rate = 32768,
	41	};
	42
	43	/*
	44	* Default rate for the root input clock, reset this with clk_set_rate()
	45	* from the platform code.
	46	*/
	47	struct clk extal_clk = {
bc49b6ea MD	48	.rate = 33333333,
	49	};
	50
	51	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
	52	static unsigned long dll_recalc(struct clk *clk)
	53	{
	54	unsigned long mult;
	55
	56	if (__raw_readl(PLLCR) & 0x1000)
	57	mult = __raw_readl(DLLFRQ);
	58	else
	59	mult = 0;
	60
	61	return clk->parent->rate * mult;
	62	}
	63
	64	static struct clk_ops dll_clk_ops = {
	65	.recalc = dll_recalc,
	66	};
	67
	68	static struct clk dll_clk = {
bc49b6ea MD	69	.ops = &dll_clk_ops,
	70	.parent = &r_clk,
	71	.flags = CLK_ENABLE_ON_INIT,
	72	};
	73
	74	static unsigned long pll_recalc(struct clk *clk)
	75	{
	76	unsigned long mult = 1;
	77
	78	if (__raw_readl(PLLCR) & 0x4000)
	79	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	80
	81	return clk->parent->rate * mult;
	82	}
	83
	84	static struct clk_ops pll_clk_ops = {
	85	.recalc = pll_recalc,
	86	};
	87
	88	static struct clk pll_clk = {
bc49b6ea MD	89	.ops = &pll_clk_ops,
	90	.flags = CLK_ENABLE_ON_INIT,
	91	};
	92
	93	struct clk *main_clks[] = {
	94	&r_clk,
	95	&extal_clk,
	96	&dll_clk,
	97	&pll_clk,
	98	};
	99
	100	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
	101	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
	102
0a5f337e	103	static struct clk_div_mult_table div4_div_mult_table = {
bc49b6ea MD	104	.divisors = divisors,
	105	.nr_divisors = ARRAY_SIZE(divisors),
	106	.multipliers = multipliers,
	107	.nr_multipliers = ARRAY_SIZE(multipliers),
	108	};
	109
0a5f337e MD	110	static struct clk_div4_table div4_table = {
	111	.div_mult_table = &div4_div_mult_table,
	112	};
	113
bc49b6ea MD	114	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
	115	DIV4_SIUA, DIV4_SIUB, DIV4_NR };
	116
914ebf0b MD	117	#define DIV4(_reg, _bit, _mask, _flags) \
914ebf0b MD	118	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
bc49b6ea MD	119
bc49b6ea MD	120	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	121	[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
	122	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	123	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	124	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	125	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	126	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
	127	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	128	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
bc49b6ea MD	129	};
bc49b6ea MD	130
098ec49b MD	131	enum { DIV6_V, DIV6_NR };
	132
	133	struct clk div6_clks[DIV6_NR] = {
9e1985e1	134	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
bc49b6ea MD	135	};
bc49b6ea MD	136
c77a9c3e MD	137	#define MSTP(_parent, _reg, _bit, _flags) \
c77a9c3e MD	138	SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
bc49b6ea	139
e8b96918 MD	140	enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
	141	MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
	142	MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
	143	MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
	144	MSTP109, MSTP108, MSTP100,
	145	MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
	146	MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
	147	MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
	148	MSTP_NR };
	149
	150	static struct clk mstp_clks[MSTP_NR] = {
c77a9c3e MD	151	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	152	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	153	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	154	[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	155	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	156	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	157	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	158	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	159	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	160	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	161	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	162	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	163	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	164	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	165	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	166	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	167	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	168	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	169	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	170	[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
	171	[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
	172	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	173	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
	174
	175	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	176	[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
	177
	178	[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
	179	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	180	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	181	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	182	[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
	183	[MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
	184	[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
	185	[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
	186	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	187	[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
	188	[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
	189	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	190	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	191	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	192	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	193	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	194	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
bc49b6ea MD	195	};
bc49b6ea MD	196
098ec49b MD	197	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	198
	199	static struct clk_lookup lookups[] = {
8249a311 MD	200	/* main clocks */
	201	CLKDEV_CON_ID("rclk", &r_clk),
	202	CLKDEV_CON_ID("extal", &extal_clk),
	203	CLKDEV_CON_ID("dll_clk", &dll_clk),
	204	CLKDEV_CON_ID("pll_clk", &pll_clk),
	205
f8ef178c MD	206	/* DIV4 clocks */
	207	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	208	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	209	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	210	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	211	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	212	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	213	CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
	214	CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
	215
098ec49b MD	216	/* DIV6 clocks */
098ec49b MD	217	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
25637f7a MD	218
	219	/* MSTP32 clocks */
	220	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	221	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	222	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	223	CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
	224	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	225	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	226	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
25637f7a MD	227	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	228	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	229	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	230	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	231	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
	232	CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
	233	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	234	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	235	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
	236	{
	237	/* SCIF0 */
	238	.dev_id = "sh-sci.0",
	239	.con_id = "sci_fck",
	240	.clk = &mstp_clks[MSTP007],
	241	}, {
	242	/* SCIF1 */
	243	.dev_id = "sh-sci.1",
	244	.con_id = "sci_fck",
	245	.clk = &mstp_clks[MSTP006],
	246	}, {
	247	/* SCIF2 */
	248	.dev_id = "sh-sci.2",
	249	.con_id = "sci_fck",
	250	.clk = &mstp_clks[MSTP005],
	251	}, {
	252	/* SCIF3 */
	253	.dev_id = "sh-sci.3",
	254	.con_id = "sci_fck",
	255	.clk = &mstp_clks[MSTP004],
	256	},
	257	CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
	258	CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
	259	CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
	260	CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
	261	CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
	262	CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
	263	CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
	264	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	265	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	266	CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
	267	CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
	268	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
	269	CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
	270	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	271	CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
	272	CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
	273	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	274	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	275	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	276	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	277	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	278	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
098ec49b MD	279	};
098ec49b MD	280
bc49b6ea MD	281	int __init arch_clk_init(void)
	282	{
	283	int k, ret = 0;
	284
	285	/* autodetect extal or dll configuration */
	286	if (__raw_readl(PLLCR) & 0x1000)
	287	pll_clk.parent = &dll_clk;
	288	else
	289	pll_clk.parent = &extal_clk;
	290
	291	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	292	ret = clk_register(main_clks[k]);
	293
098ec49b MD	294	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
098ec49b MD	295
bc49b6ea MD	296	if (!ret)
	297	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	298
	299	if (!ret)
098ec49b	300	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
bc49b6ea MD	301
bc49b6ea MD	302	if (!ret)
e8b96918	303	ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
bc49b6ea MD	304
	305	return ret;
	306	}