[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7343.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
 *
 * SH7343 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>

/* SH7343 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.name           = "rclk",
	.id             = -1,
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.name           = "dll_clk",
	.id             = -1,
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);

	return clk->parent->rate * mult;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
       DIV4_SIUA, DIV4_SIUB, DIV4_NR };

#define DIV4(_str, _reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

#define MSTP(_str, _parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)

enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
       MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
       MSTP109, MSTP108, MSTP100,
       MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
       MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP031] = MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	[MSTP030] = MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	[MSTP029] = MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	[MSTP028] = MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	[MSTP026] = MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	[MSTP023] = MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
	[MSTP022] = MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
	[MSTP021] = MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP019] = MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
	[MSTP017] = MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP015] = MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[MSTP014] = MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
	[MSTP013] = MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
	[MSTP011] = MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
	[MSTP010] = MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[MSTP007] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
	[MSTP006] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
	[MSTP005] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
	[MSTP004] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
	[MSTP003] = MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
	[MSTP002] = MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
	[MSTP001] = MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),

	[MSTP109] = MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
	[MSTP108] = MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),

	[MSTP225] = MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
	[MSTP224] = MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
	[MSTP218] = MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
	[MSTP217] = MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
	[MSTP216] = MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
	[MSTP214] = MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
	[MSTP213] = MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
	[MSTP212] = MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
	[MSTP211] = MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
	[MSTP208] = MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
	[MSTP206] = MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
	[MSTP205] = MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
	[MSTP204] = MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
	[MSTP203] = MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
	[MSTP202] = MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	[MSTP201] = MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	[MSTP200] = MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
bc49b6ea MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7343.c
	3	*
	4	* SH7343 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
098ec49b	24	#include <asm/clkdev.h>
bc49b6ea MD	25	#include <asm/clock.h>
	26
	27	/* SH7343 registers */
	28	#define FRQCR 0xa4150000
	29	#define VCLKCR 0xa4150004
	30	#define SCLKACR 0xa4150008
	31	#define SCLKBCR 0xa415000c
	32	#define PLLCR 0xa4150024
	33	#define MSTPCR0 0xa4150030
	34	#define MSTPCR1 0xa4150034
	35	#define MSTPCR2 0xa4150038
	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
	40	.name = "rclk",
	41	.id = -1,
	42	.rate = 32768,
	43	};
	44
	45	/*
	46	* Default rate for the root input clock, reset this with clk_set_rate()
	47	* from the platform code.
	48	*/
	49	struct clk extal_clk = {
	50	.name = "extal",
	51	.id = -1,
	52	.rate = 33333333,
	53	};
	54
	55	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
	56	static unsigned long dll_recalc(struct clk *clk)
	57	{
	58	unsigned long mult;
	59
	60	if (__raw_readl(PLLCR) & 0x1000)
	61	mult = __raw_readl(DLLFRQ);
	62	else
	63	mult = 0;
	64
	65	return clk->parent->rate * mult;
	66	}
	67
	68	static struct clk_ops dll_clk_ops = {
	69	.recalc = dll_recalc,
	70	};
	71
	72	static struct clk dll_clk = {
	73	.name = "dll_clk",
	74	.id = -1,
	75	.ops = &dll_clk_ops,
	76	.parent = &r_clk,
	77	.flags = CLK_ENABLE_ON_INIT,
	78	};
	79
	80	static unsigned long pll_recalc(struct clk *clk)
	81	{
	82	unsigned long mult = 1;
	83
	84	if (__raw_readl(PLLCR) & 0x4000)
	85	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	86
	87	return clk->parent->rate * mult;
	88	}
89
90	static struct clk_ops pll_clk_ops = {
91	.recalc = pll_recalc,
92	};
93
94	static struct clk pll_clk = {
95	.name = "pll_clk",
96	.id = -1,
97	.ops = &pll_clk_ops,
98	.flags = CLK_ENABLE_ON_INIT,
99	};
100
101	struct clk *main_clks[] = {
102	&r_clk,
103	&extal_clk,
104	&dll_clk,
105	&pll_clk,
106	};
107
108	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
109	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
110
0a5f337e	111	static struct clk_div_mult_table div4_div_mult_table = {
bc49b6ea MD	112	.divisors = divisors,
	113	.nr_divisors = ARRAY_SIZE(divisors),
	114	.multipliers = multipliers,
	115	.nr_multipliers = ARRAY_SIZE(multipliers),
	116	};
	117
0a5f337e MD	118	static struct clk_div4_table div4_table = {
	119	.div_mult_table = &div4_div_mult_table,
	120	};
	121
bc49b6ea MD	122	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
	123	DIV4_SIUA, DIV4_SIUB, DIV4_NR };
	124
	125	#define DIV4(_str, _reg, _bit, _mask, _flags) \
	126	SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
	127
	128	struct clk div4_clks[DIV4_NR] = {
	129	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
	130	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	131	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	132	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	133	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	134	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	135	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	136	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
	137	};
	138
098ec49b MD	139	enum { DIV6_V, DIV6_NR };
	140
	141	struct clk div6_clks[DIV6_NR] = {
9e1985e1	142	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
bc49b6ea MD	143	};
	144
	145	#define MSTP(_str, _parent, _reg, _bit, _flags) \
	146	SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
	147
e8b96918 MD	148	enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
	149	MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
	150	MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
	151	MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
	152	MSTP109, MSTP108, MSTP100,
	153	MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
	154	MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
	155	MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
	156	MSTP_NR };
	157
	158	static struct clk mstp_clks[MSTP_NR] = {
	159	[MSTP031] = MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	160	[MSTP030] = MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	161	[MSTP029] = MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	162	[MSTP028] = MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	163	[MSTP026] = MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	164	[MSTP023] = MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
	165	[MSTP022] = MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
	166	[MSTP021] = MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
	167	[MSTP020] = MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
	168	[MSTP019] = MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
	169	[MSTP017] = MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
	170	[MSTP015] = MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
	171	[MSTP014] = MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
	172	[MSTP013] = MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
	173	[MSTP011] = MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
	174	[MSTP010] = MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
	175	[MSTP007] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
	176	[MSTP006] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
	177	[MSTP005] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
	178	[MSTP004] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
	179	[MSTP003] = MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
	180	[MSTP002] = MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
	181	[MSTP001] = MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
	182
	183	[MSTP109] = MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
	184	[MSTP108] = MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
	185
	186	[MSTP225] = MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
	187	[MSTP224] = MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
	188	[MSTP218] = MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
	189	[MSTP217] = MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
	190	[MSTP216] = MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
	191	[MSTP214] = MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
	192	[MSTP213] = MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
	193	[MSTP212] = MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
	194	[MSTP211] = MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
	195	[MSTP208] = MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
	196	[MSTP206] = MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
	197	[MSTP205] = MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
	198	[MSTP204] = MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
	199	[MSTP203] = MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
	200	[MSTP202] = MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	201	[MSTP201] = MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	202	[MSTP200] = MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
bc49b6ea MD	203	};
bc49b6ea MD	204
098ec49b MD	205	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	206
	207	static struct clk_lookup lookups[] = {
	208	/* DIV6 clocks */
	209	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
	210	};
	211
bc49b6ea MD	212	int __init arch_clk_init(void)
	213	{
	214	int k, ret = 0;
	215
	216	/* autodetect extal or dll configuration */
	217	if (__raw_readl(PLLCR) & 0x1000)
	218	pll_clk.parent = &dll_clk;
	219	else
	220	pll_clk.parent = &extal_clk;
	221
	222	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	223	ret = clk_register(main_clks[k]);
	224
098ec49b MD	225	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
098ec49b MD	226
bc49b6ea MD	227	if (!ret)
	228	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	229
	230	if (!ret)
098ec49b	231	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
bc49b6ea MD	232
bc49b6ea MD	233	if (!ret)
e8b96918	234	ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
bc49b6ea MD	235
	236	return ret;
	237	}