[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7722.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
 *
 * SH7722 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7722.h>

/* SH7722 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define IRDACLKCR	0xa4150018
#define PLLCR		0xa4150024
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

#define DIV4(_reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
};

enum { DIV4_IRDA, DIV4_ENABLE_NR };

struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
};

enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };

struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

static struct clk mstp_clks[HWBLK_NR] = {
	SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),

	SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),

	SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
	SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
	SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
	SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("rclk", &r_clk),
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("dll_clk", &dll_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),

	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP clocks */
	CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
	CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
	{
		/* TMU0 */
		.dev_id		= "sh_tmu.0",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	}, {
		/* TMU1 */
		.dev_id		= "sh_tmu.1",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	}, {
		/* TMU2 */
		.dev_id		= "sh_tmu.2",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	},
	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
	CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
	{
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF0],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF1],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF2],
	},
	CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
	CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
	CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
	CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
	CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
	CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
	CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
	CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
	CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_enable_register(div4_enable_clks,
					DIV4_ENABLE_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_reparent_register(div4_reparent_clks,
					DIV4_REPARENT_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);

	return ret;
}
Commit	Line	Data
1929cb34	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
	3	*
46e9371c	4	* SH7722 clock framework support
1929cb34	5	*
46e9371c	6	* Copyright (C) 2009 Magnus Damm
1929cb34	7	*
46e9371c MD	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1929cb34	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
e4e06697	24	#include <asm/clkdev.h>
1929cb34	25	#include <asm/clock.h>
a61c1a63 MD	26	#include <asm/hwblk.h>
a61c1a63 MD	27	#include <cpu/sh7722.h>
1929cb34	28
46e9371c MD	29	/* SH7722 registers */
	30	#define FRQCR 0xa4150000
	31	#define VCLKCR 0xa4150004
	32	#define SCLKACR 0xa4150008
	33	#define SCLKBCR 0xa415000c
	34	#define IRDACLKCR 0xa4150018
	35	#define PLLCR 0xa4150024
46e9371c MD	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
46e9371c	40	.rate = 32768,
1929cb34	41	};
1929cb34	42
1929cb34	43	/*
46e9371c MD	44	* Default rate for the root input clock, reset this with clk_set_rate()
46e9371c MD	45	* from the platform code.
1929cb34	46	*/
46e9371c	47	struct clk extal_clk = {
46e9371c	48	.rate = 33333333,
1929cb34	49	};
1929cb34	50
46e9371c MD	51	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
46e9371c MD	52	static unsigned long dll_recalc(struct clk *clk)
1929cb34	53	{
46e9371c	54	unsigned long mult;
1929cb34	55
46e9371c MD	56	if (__raw_readl(PLLCR) & 0x1000)
46e9371c MD	57	mult = __raw_readl(DLLFRQ);
1929cb34	58	else
46e9371c	59	mult = 0;
1929cb34	60
46e9371c	61	return clk->parent->rate * mult;
1929cb34	62	}
1929cb34	63
46e9371c MD	64	static struct clk_ops dll_clk_ops = {
46e9371c MD	65	.recalc = dll_recalc,
1312994c MD	66	};
1312994c MD	67
46e9371c	68	static struct clk dll_clk = {
46e9371c MD	69	.ops = &dll_clk_ops,
	70	.parent = &r_clk,
	71	.flags = CLK_ENABLE_ON_INIT,
	72	};
1929cb34	73
46e9371c	74	static unsigned long pll_recalc(struct clk *clk)
1929cb34	75	{
46e9371c MD	76	unsigned long mult = 1;
46e9371c MD	77	unsigned long div = 1;
1929cb34	78
46e9371c MD	79	if (__raw_readl(PLLCR) & 0x4000)
	80	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	81	else
	82	div = 2;
1929cb34	83
46e9371c	84	return (clk->parent->rate * mult) / div;
1929cb34	85	}
1929cb34	86
46e9371c MD	87	static struct clk_ops pll_clk_ops = {
46e9371c MD	88	.recalc = pll_recalc,
1929cb34	89	};
1929cb34	90
46e9371c	91	static struct clk pll_clk = {
46e9371c MD	92	.ops = &pll_clk_ops,
46e9371c MD	93	.flags = CLK_ENABLE_ON_INIT,
1929cb34	94	};
1929cb34	95
46e9371c MD	96	struct clk *main_clks[] = {
	97	&r_clk,
	98	&extal_clk,
	99	&dll_clk,
	100	&pll_clk,
1929cb34	101	};
1929cb34	102
46e9371c MD	103	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
46e9371c MD	104	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
1929cb34	105
0a5f337e	106	static struct clk_div_mult_table div4_div_mult_table = {
46e9371c MD	107	.divisors = divisors,
	108	.nr_divisors = ARRAY_SIZE(divisors),
	109	.multipliers = multipliers,
	110	.nr_multipliers = ARRAY_SIZE(multipliers),
7c7e02a2	111	};
1312994c	112
0a5f337e MD	113	static struct clk_div4_table div4_table = {
	114	.div_mult_table = &div4_div_mult_table,
	115	};
	116
914ebf0b MD	117	#define DIV4(_reg, _bit, _mask, _flags) \
914ebf0b MD	118	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
1929cb34	119
31c3af50 GL	120	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
31c3af50 GL	121
46e9371c	122	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	123	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	124	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	125	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	126	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	127	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	128	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
31c3af50 GL	129	};
	130
	131	enum { DIV4_IRDA, DIV4_ENABLE_NR };
	132
	133	struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
914ebf0b	134	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
31c3af50 GL	135	};
	136
	137	enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
	138
	139	struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
914ebf0b MD	140	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
914ebf0b MD	141	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
1929cb34	142	};
1929cb34	143
098ec49b MD	144	enum { DIV6_V, DIV6_NR };
	145
	146	struct clk div6_clks[DIV6_NR] = {
9e1985e1	147	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
1929cb34	148	};
1929cb34	149
f3d51e13	150	static struct clk mstp_clks[HWBLK_NR] = {
08134c3c MD	151	SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
	152	SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
	153	SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
	154	SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
	155	SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
	156	SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
	157	SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
	158	SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
	159	SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
	160
	161	SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
	162	SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
	163
	164	SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
	165	SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
	166	SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
	167	SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
	168	SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
	169	SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
	170	SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
	171	SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
	172	SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
	173	SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
	174	SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
	175	SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
1929cb34	176	};
1929cb34	177
fd30401b MD	178	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
fd30401b MD	179
e4e06697	180	static struct clk_lookup lookups[] = {
925bb17b MD	181	/* main clocks */
	182	CLKDEV_CON_ID("rclk", &r_clk),
	183	CLKDEV_CON_ID("extal", &extal_clk),
	184	CLKDEV_CON_ID("dll_clk", &dll_clk),
	185	CLKDEV_CON_ID("pll_clk", &pll_clk),
	186
a3e9f2b7 MD	187	/* DIV4 clocks */
	188	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	189	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	190	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	191	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	192	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	193	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	194	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
	195	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
	196	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
	197
098ec49b MD	198	/* DIV6 clocks */
	199	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
	200
fd30401b MD	201	/* MSTP clocks */
	202	CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
	203	CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
e4e06697 MD	204	{
	205	/* TMU0 */
	206	.dev_id = "sh_tmu.0",
	207	.con_id = "tmu_fck",
	208	.clk = &mstp_clks[HWBLK_TMU],
	209	}, {
	210	/* TMU1 */
	211	.dev_id = "sh_tmu.1",
	212	.con_id = "tmu_fck",
	213	.clk = &mstp_clks[HWBLK_TMU],
	214	}, {
	215	/* TMU2 */
	216	.dev_id = "sh_tmu.2",
	217	.con_id = "tmu_fck",
	218	.clk = &mstp_clks[HWBLK_TMU],
fd30401b MD	219	},
	220	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
	221	CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
	222	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
	223	{
e4e06697 MD	224	/* SCIF0 */
	225	.dev_id = "sh-sci.0",
	226	.con_id = "sci_fck",
	227	.clk = &mstp_clks[HWBLK_SCIF0],
	228	}, {
	229	/* SCIF1 */
	230	.dev_id = "sh-sci.1",
	231	.con_id = "sci_fck",
	232	.clk = &mstp_clks[HWBLK_SCIF1],
	233	}, {
	234	/* SCIF2 */
	235	.dev_id = "sh-sci.2",
	236	.con_id = "sci_fck",
	237	.clk = &mstp_clks[HWBLK_SCIF2],
	238	},
fd30401b MD	239	CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
	240	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
	241	CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
	242	CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
	243	CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
	244	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
	245	CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
	246	CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
	247	CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
	248	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
	249	CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
	250	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
	251	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
	252	CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
e4e06697 MD	253	};
e4e06697 MD	254
dfbbbe92	255	int __init arch_clk_init(void)
1929cb34	256	{
46e9371c	257	int k, ret = 0;
1929cb34	258
46e9371c MD	259	/* autodetect extal or dll configuration */
	260	if (__raw_readl(PLLCR) & 0x1000)
	261	pll_clk.parent = &dll_clk;
	262	else
	263	pll_clk.parent = &extal_clk;
253b0887	264
46e9371c MD	265	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
46e9371c MD	266	ret = clk_register(main_clks[k]);
7c7e02a2	267
e4e06697 MD	268	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
e4e06697 MD	269
46e9371c MD	270	if (!ret)
46e9371c MD	271	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
7c7e02a2	272
31c3af50 GL	273	if (!ret)
	274	ret = sh_clk_div4_enable_register(div4_enable_clks,
	275	DIV4_ENABLE_NR, &div4_table);
	276
	277	if (!ret)
	278	ret = sh_clk_div4_reparent_register(div4_reparent_clks,
	279	DIV4_REPARENT_NR, &div4_table);
	280
46e9371c	281	if (!ret)
098ec49b	282	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
aea167cb	283
46e9371c	284	if (!ret)
f3d51e13	285	ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
0c0daec7	286
46e9371c	287	return ret;
1929cb34	288	}