[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7722.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
 *
 * SH7722 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/sh_clk.h>
#include <asm/clock.h>
#include <cpu/sh7722.h>

/* SH7722 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define IRDACLKCR	0xa4150018
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct sh_clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct sh_clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

#define DIV4(_reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
};

enum { DIV4_IRDA, DIV4_ENABLE_NR };

struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
};

enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };

struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

static struct clk mstp_clks[HWBLK_NR] = {
	[HWBLK_URAM]  = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	[HWBLK_TMU]   = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[HWBLK_CMT]   = SH_CLK_MSTP32(&r_clk,		  MSTPCR0, 14, 0),
	[HWBLK_RWDT]  = SH_CLK_MSTP32(&r_clk,		  MSTPCR0, 13, 0),
	[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),

	[HWBLK_IIC]   = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	[HWBLK_RTC]   = SH_CLK_MSTP32(&r_clk,		  MSTPCR1, 8, 0),

	[HWBLK_SDHI]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk,		  MSTPCR2, 14, 0),
	[HWBLK_USBF]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	[HWBLK_2DG]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
	[HWBLK_SIU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
	[HWBLK_JPU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
	[HWBLK_VOU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	[HWBLK_BEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	[HWBLK_CEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	[HWBLK_VEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
	[HWBLK_VPU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
	[HWBLK_LCDC]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
};

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("rclk", &r_clk),
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("dll_clk", &dll_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),

	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP clocks */
	CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
	CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),

	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU]),
	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU]),
	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),

	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
	CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),

	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),

	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
	CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
	CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
	CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
	CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
	CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_enable_register(div4_enable_clks,
					DIV4_ENABLE_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_reparent_register(div4_reparent_clks,
					DIV4_REPARENT_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR);

	return ret;
}
Commit	Line	Data
1929cb34	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
	3	*
46e9371c	4	* SH7722 clock framework support
1929cb34	5	*
46e9371c	6	* Copyright (C) 2009 Magnus Damm
1929cb34	7	*
46e9371c MD	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1929cb34	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
6d803ba7	24	#include <linux/clkdev.h>
6a06d5bf	25	#include <linux/sh_clk.h>
1929cb34	26	#include <asm/clock.h>
a61c1a63	27	#include <cpu/sh7722.h>
1929cb34	28
46e9371c MD	29	/* SH7722 registers */
	30	#define FRQCR 0xa4150000
	31	#define VCLKCR 0xa4150004
	32	#define SCLKACR 0xa4150008
	33	#define SCLKBCR 0xa415000c
	34	#define IRDACLKCR 0xa4150018
	35	#define PLLCR 0xa4150024
6a06d5bf GL	36	#define MSTPCR0 0xa4150030
	37	#define MSTPCR1 0xa4150034
	38	#define MSTPCR2 0xa4150038
46e9371c MD	39	#define DLLFRQ 0xa4150050
	40
	41	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	42	static struct clk r_clk = {
46e9371c	43	.rate = 32768,
1929cb34	44	};
1929cb34	45
1929cb34	46	/*
46e9371c MD	47	* Default rate for the root input clock, reset this with clk_set_rate()
46e9371c MD	48	* from the platform code.
1929cb34	49	*/
46e9371c	50	struct clk extal_clk = {
46e9371c	51	.rate = 33333333,
1929cb34	52	};
1929cb34	53
46e9371c MD	54	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
46e9371c MD	55	static unsigned long dll_recalc(struct clk *clk)
1929cb34	56	{
46e9371c	57	unsigned long mult;
1929cb34	58
46e9371c MD	59	if (__raw_readl(PLLCR) & 0x1000)
46e9371c MD	60	mult = __raw_readl(DLLFRQ);
1929cb34	61	else
46e9371c	62	mult = 0;
1929cb34	63
46e9371c	64	return clk->parent->rate * mult;
1929cb34	65	}
1929cb34	66
33cb61a4	67	static struct sh_clk_ops dll_clk_ops = {
46e9371c	68	.recalc = dll_recalc,
1312994c MD	69	};
1312994c MD	70
46e9371c	71	static struct clk dll_clk = {
46e9371c MD	72	.ops = &dll_clk_ops,
	73	.parent = &r_clk,
	74	.flags = CLK_ENABLE_ON_INIT,
	75	};
1929cb34	76
46e9371c	77	static unsigned long pll_recalc(struct clk *clk)
1929cb34	78	{
46e9371c MD	79	unsigned long mult = 1;
46e9371c MD	80	unsigned long div = 1;
1929cb34	81
46e9371c MD	82	if (__raw_readl(PLLCR) & 0x4000)
	83	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	84	else
	85	div = 2;
1929cb34	86
46e9371c	87	return (clk->parent->rate * mult) / div;
1929cb34	88	}
1929cb34	89
33cb61a4	90	static struct sh_clk_ops pll_clk_ops = {
46e9371c	91	.recalc = pll_recalc,
1929cb34	92	};
1929cb34	93
46e9371c	94	static struct clk pll_clk = {
46e9371c MD	95	.ops = &pll_clk_ops,
46e9371c MD	96	.flags = CLK_ENABLE_ON_INIT,
1929cb34	97	};
1929cb34	98
46e9371c MD	99	struct clk *main_clks[] = {
	100	&r_clk,
	101	&extal_clk,
	102	&dll_clk,
	103	&pll_clk,
1929cb34	104	};
1929cb34	105
46e9371c MD	106	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
46e9371c MD	107	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
1929cb34	108
0a5f337e	109	static struct clk_div_mult_table div4_div_mult_table = {
46e9371c MD	110	.divisors = divisors,
	111	.nr_divisors = ARRAY_SIZE(divisors),
	112	.multipliers = multipliers,
	113	.nr_multipliers = ARRAY_SIZE(multipliers),
7c7e02a2	114	};
1312994c	115
0a5f337e MD	116	static struct clk_div4_table div4_table = {
	117	.div_mult_table = &div4_div_mult_table,
	118	};
	119
914ebf0b MD	120	#define DIV4(_reg, _bit, _mask, _flags) \
914ebf0b MD	121	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
1929cb34	122
31c3af50 GL	123	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
31c3af50 GL	124
46e9371c	125	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	126	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	127	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	128	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	129	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	130	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	131	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
31c3af50 GL	132	};
	133
	134	enum { DIV4_IRDA, DIV4_ENABLE_NR };
	135
	136	struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
914ebf0b	137	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
31c3af50 GL	138	};
	139
	140	enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
	141
	142	struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
914ebf0b MD	143	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
914ebf0b MD	144	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
1929cb34	145	};
1929cb34	146
098ec49b MD	147	enum { DIV6_V, DIV6_NR };
	148
	149	struct clk div6_clks[DIV6_NR] = {
9e1985e1	150	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
1929cb34	151	};
1929cb34	152
f3d51e13	153	static struct clk mstp_clks[HWBLK_NR] = {
6a06d5bf GL	154	[HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	155	[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	156	[HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	157	[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
	158	[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
	159	[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	160	[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	161	[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	162	[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	163
	164	[HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	165	[HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
	166
	167	[HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	168	[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
	169	[HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	170	[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
	171	[HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
	172	[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
	173	[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	174	[HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	175	[HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	176	[HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
	177	[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
	178	[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
1929cb34	179	};
1929cb34	180
e4e06697	181	static struct clk_lookup lookups[] = {
925bb17b MD	182	/* main clocks */
	183	CLKDEV_CON_ID("rclk", &r_clk),
	184	CLKDEV_CON_ID("extal", &extal_clk),
	185	CLKDEV_CON_ID("dll_clk", &dll_clk),
	186	CLKDEV_CON_ID("pll_clk", &pll_clk),
	187
a3e9f2b7 MD	188	/* DIV4 clocks */
	189	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	190	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	191	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	192	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	193	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	194	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	195	CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
	196	CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
	197	CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
	198
098ec49b MD	199	/* DIV6 clocks */
	200	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
	201
fd30401b MD	202	/* MSTP clocks */
	203	CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
	204	CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
ac6b4fd1 KM	205
	206	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU]),
	207	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU]),
	208	CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
	209
fd30401b	210	CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
6a06d5bf	211	CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
fd30401b	212	CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
ac6b4fd1	213
6a06d5bf GL	214	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
	215	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
	216	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
ac6b4fd1	217
2125a8a6	218	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
fd30401b	219	CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
6a06d5bf GL	220	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
6a06d5bf GL	221	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
fd30401b MD	222	CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
fd30401b MD	223	CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
6a06d5bf GL	224	CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
6a06d5bf GL	225	CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
fd30401b MD	226	CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
fd30401b MD	227	CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
6a06d5bf	228	CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
fd30401b MD	229	CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
fd30401b MD	230	CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
6a06d5bf	231	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
e4e06697 MD	232	};
e4e06697 MD	233
dfbbbe92	234	int __init arch_clk_init(void)
1929cb34	235	{
46e9371c	236	int k, ret = 0;
1929cb34	237
46e9371c MD	238	/* autodetect extal or dll configuration */
	239	if (__raw_readl(PLLCR) & 0x1000)
	240	pll_clk.parent = &dll_clk;
	241	else
	242	pll_clk.parent = &extal_clk;
253b0887	243
46e9371c MD	244	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
46e9371c MD	245	ret = clk_register(main_clks[k]);
7c7e02a2	246
e4e06697 MD	247	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
e4e06697 MD	248
46e9371c MD	249	if (!ret)
46e9371c MD	250	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
7c7e02a2	251
31c3af50 GL	252	if (!ret)
	253	ret = sh_clk_div4_enable_register(div4_enable_clks,
	254	DIV4_ENABLE_NR, &div4_table);
	255
	256	if (!ret)
	257	ret = sh_clk_div4_reparent_register(div4_reparent_clks,
	258	DIV4_REPARENT_NR, &div4_table);
	259
46e9371c	260	if (!ret)
098ec49b	261	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
aea167cb	262
46e9371c	263	if (!ret)
ad3337cb	264	ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR);
0c0daec7	265
46e9371c	266	return ret;
1929cb34	267	}