[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7722.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
 *
 * SH7722 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7722.h>

/* SH7722 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define IRDACLKCR	0xa4150018
#define PLLCR		0xa4150024
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.name           = "rclk",
	.id             = -1,
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.name           = "dll_clk",
	.id             = -1,
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

#define DIV4(_str, _reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
};

enum { DIV4_IRDA, DIV4_ENABLE_NR };

struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
};

enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };

struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
};

struct clk div6_clks[] = {
	SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
};

#define R_CLK &r_clk
#define P_CLK &div4_clks[DIV4_P]
#define B_CLK &div4_clks[DIV4_B]
#define U_CLK &div4_clks[DIV4_U]

static struct clk mstp_clks[HWBLK_NR] = {
	SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
	SH_HWBLK_CLK("tmu_fck", -1, P_CLK, HWBLK_TMU, 0),
	SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
	SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
	SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF0, 0),
	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF1, 0),
	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF2, 0),

	SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
	SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),

	SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
	SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
	SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
	SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
	SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
	SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
	SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
	SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
	SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
	SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
	SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
	SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
};

static struct clk_lookup lookups[] = {
	{
		/* TMU0 */
		.dev_id		= "sh_tmu.0",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	}, {
		/* TMU1 */
		.dev_id		= "sh_tmu.1",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	}, {
		/* TMU2 */
		.dev_id		= "sh_tmu.2",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[HWBLK_TMU],
	}, {
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF0],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF1],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[HWBLK_SCIF2],
	},
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_enable_register(div4_enable_clks,
					DIV4_ENABLE_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div4_reparent_register(div4_reparent_clks,
					DIV4_REPARENT_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));

	if (!ret)
		ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);

	return ret;
}
Commit	Line	Data
1929cb34	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
	3	*
46e9371c	4	* SH7722 clock framework support
1929cb34	5	*
46e9371c	6	* Copyright (C) 2009 Magnus Damm
1929cb34	7	*
46e9371c MD	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1929cb34	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
e4e06697	24	#include <asm/clkdev.h>
1929cb34	25	#include <asm/clock.h>
a61c1a63 MD	26	#include <asm/hwblk.h>
a61c1a63 MD	27	#include <cpu/sh7722.h>
1929cb34	28
46e9371c MD	29	/* SH7722 registers */
	30	#define FRQCR 0xa4150000
	31	#define VCLKCR 0xa4150004
	32	#define SCLKACR 0xa4150008
	33	#define SCLKBCR 0xa415000c
	34	#define IRDACLKCR 0xa4150018
	35	#define PLLCR 0xa4150024
46e9371c MD	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
	40	.name = "rclk",
	41	.id = -1,
	42	.rate = 32768,
1929cb34	43	};
1929cb34	44
1929cb34	45	/*
46e9371c MD	46	* Default rate for the root input clock, reset this with clk_set_rate()
46e9371c MD	47	* from the platform code.
1929cb34	48	*/
46e9371c MD	49	struct clk extal_clk = {
	50	.name = "extal",
	51	.id = -1,
	52	.rate = 33333333,
1929cb34	53	};
1929cb34	54
46e9371c MD	55	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
46e9371c MD	56	static unsigned long dll_recalc(struct clk *clk)
1929cb34	57	{
46e9371c	58	unsigned long mult;
1929cb34	59
46e9371c MD	60	if (__raw_readl(PLLCR) & 0x1000)
46e9371c MD	61	mult = __raw_readl(DLLFRQ);
1929cb34	62	else
46e9371c	63	mult = 0;
1929cb34	64
46e9371c	65	return clk->parent->rate * mult;
1929cb34	66	}
1929cb34	67
46e9371c MD	68	static struct clk_ops dll_clk_ops = {
46e9371c MD	69	.recalc = dll_recalc,
1312994c MD	70	};
1312994c MD	71
46e9371c MD	72	static struct clk dll_clk = {
	73	.name = "dll_clk",
	74	.id = -1,
	75	.ops = &dll_clk_ops,
	76	.parent = &r_clk,
	77	.flags = CLK_ENABLE_ON_INIT,
	78	};
1929cb34	79
46e9371c	80	static unsigned long pll_recalc(struct clk *clk)
1929cb34	81	{
46e9371c MD	82	unsigned long mult = 1;
46e9371c MD	83	unsigned long div = 1;
1929cb34	84
46e9371c MD	85	if (__raw_readl(PLLCR) & 0x4000)
	86	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	87	else
	88	div = 2;
1929cb34	89
46e9371c	90	return (clk->parent->rate * mult) / div;
1929cb34	91	}
1929cb34	92
46e9371c MD	93	static struct clk_ops pll_clk_ops = {
46e9371c MD	94	.recalc = pll_recalc,
1929cb34	95	};
1929cb34	96
46e9371c MD	97	static struct clk pll_clk = {
	98	.name = "pll_clk",
	99	.id = -1,
	100	.ops = &pll_clk_ops,
	101	.flags = CLK_ENABLE_ON_INIT,
1929cb34	102	};
1929cb34	103
46e9371c MD	104	struct clk *main_clks[] = {
	105	&r_clk,
	106	&extal_clk,
	107	&dll_clk,
	108	&pll_clk,
1929cb34	109	};
1929cb34	110
46e9371c MD	111	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
46e9371c MD	112	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
1929cb34	113
0a5f337e	114	static struct clk_div_mult_table div4_div_mult_table = {
46e9371c MD	115	.divisors = divisors,
	116	.nr_divisors = ARRAY_SIZE(divisors),
	117	.multipliers = multipliers,
	118	.nr_multipliers = ARRAY_SIZE(multipliers),
7c7e02a2	119	};
1312994c	120
0a5f337e MD	121	static struct clk_div4_table div4_table = {
	122	.div_mult_table = &div4_div_mult_table,
	123	};
	124
46e9371c MD	125	#define DIV4(_str, _reg, _bit, _mask, _flags) \
46e9371c MD	126	SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
1929cb34	127
31c3af50 GL	128	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
31c3af50 GL	129
46e9371c MD	130	struct clk div4_clks[DIV4_NR] = {
	131	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	132	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	133	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	134	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	135	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	136	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
31c3af50 GL	137	};
	138
	139	enum { DIV4_IRDA, DIV4_ENABLE_NR };
	140
	141	struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
	142	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
	143	};
	144
	145	enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
	146
	147	struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
46e9371c MD	148	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
46e9371c MD	149	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
1929cb34	150	};
1929cb34	151
46e9371c MD	152	struct clk div6_clks[] = {
46e9371c MD	153	SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
1929cb34	154	};
1929cb34	155
a61c1a63 MD	156	#define R_CLK &r_clk
	157	#define P_CLK &div4_clks[DIV4_P]
	158	#define B_CLK &div4_clks[DIV4_B]
	159	#define U_CLK &div4_clks[DIV4_U]
aea167cb	160
f3d51e13	161	static struct clk mstp_clks[HWBLK_NR] = {
a61c1a63 MD	162	SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
a61c1a63 MD	163	SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
04b17317 PM	164	SH_HWBLK_CLK("tmu_fck", -1, P_CLK, HWBLK_TMU, 0),
04b17317 PM	165	SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
a61c1a63 MD	166	SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
a61c1a63 MD	167	SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
e4e06697 MD	168	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF0, 0),
	169	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF1, 0),
	170	SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF2, 0),
a61c1a63 MD	171
	172	SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
	173	SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
	174
	175	SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
	176	SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
	177	SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
	178	SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
	179	SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
	180	SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
cc58f597	181	SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
a61c1a63 MD	182	SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
a61c1a63 MD	183	SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
cc58f597 MD	184	SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
cc58f597 MD	185	SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
a61c1a63	186	SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
1929cb34	187	};
1929cb34	188
e4e06697 MD	189	static struct clk_lookup lookups[] = {
	190	{
	191	/* TMU0 */
	192	.dev_id = "sh_tmu.0",
	193	.con_id = "tmu_fck",
	194	.clk = &mstp_clks[HWBLK_TMU],
	195	}, {
	196	/* TMU1 */
	197	.dev_id = "sh_tmu.1",
	198	.con_id = "tmu_fck",
	199	.clk = &mstp_clks[HWBLK_TMU],
	200	}, {
	201	/* TMU2 */
	202	.dev_id = "sh_tmu.2",
	203	.con_id = "tmu_fck",
	204	.clk = &mstp_clks[HWBLK_TMU],
	205	}, {
	206	/* SCIF0 */
	207	.dev_id = "sh-sci.0",
	208	.con_id = "sci_fck",
	209	.clk = &mstp_clks[HWBLK_SCIF0],
	210	}, {
	211	/* SCIF1 */
	212	.dev_id = "sh-sci.1",
	213	.con_id = "sci_fck",
	214	.clk = &mstp_clks[HWBLK_SCIF1],
	215	}, {
	216	/* SCIF2 */
	217	.dev_id = "sh-sci.2",
	218	.con_id = "sci_fck",
	219	.clk = &mstp_clks[HWBLK_SCIF2],
	220	},
	221	};
	222
dfbbbe92	223	int __init arch_clk_init(void)
1929cb34	224	{
46e9371c	225	int k, ret = 0;
1929cb34	226
46e9371c MD	227	/* autodetect extal or dll configuration */
	228	if (__raw_readl(PLLCR) & 0x1000)
	229	pll_clk.parent = &dll_clk;
	230	else
	231	pll_clk.parent = &extal_clk;
253b0887	232
46e9371c MD	233	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
46e9371c MD	234	ret = clk_register(main_clks[k]);
7c7e02a2	235
e4e06697 MD	236	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
e4e06697 MD	237
46e9371c MD	238	if (!ret)
46e9371c MD	239	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
7c7e02a2	240
31c3af50 GL	241	if (!ret)
	242	ret = sh_clk_div4_enable_register(div4_enable_clks,
	243	DIV4_ENABLE_NR, &div4_table);
	244
	245	if (!ret)
	246	ret = sh_clk_div4_reparent_register(div4_reparent_clks,
	247	DIV4_REPARENT_NR, &div4_table);
	248
46e9371c MD	249	if (!ret)
46e9371c MD	250	ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
aea167cb	251
46e9371c	252	if (!ret)
f3d51e13	253	ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
0c0daec7	254
46e9371c	255	return ret;
1929cb34	256	}