[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / clock-sh7785.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c
 *
 * SH7785 support for the clock framework
 *
 *  Copyright (C) 2007 - 2010  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <cpu/sh7785.h>

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
static struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

static unsigned long pll_recalc(struct clk *clk)
{
	int multiplier;

	multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72;

	return clk->parent->rate * multiplier;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.parent		= &extal_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static struct clk *clks[] = {
	&extal_clk,
	&pll_clk,
};

static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
			       24, 32, 36, 48 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = div2,
	.nr_divisors = ARRAY_SIZE(div2),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
	DIV4_DU, DIV4_P, DIV4_NR };

#define DIV4(_bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_P] = DIV4(0, 0x0f80, 0),
	[DIV4_DU] = DIV4(4, 0x0ff0, 0),
	[DIV4_GA] = DIV4(8, 0x0030, 0),
	[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
	[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
};

#define MSTPCR0		0xffc80030
#define MSTPCR1		0xffc80034

enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
       MSTP021, MSTP020, MSTP017, MSTP016,
       MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
       MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	/* MSTPCR0 */
	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
	[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

	/* MSTPCR1 */
	[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
	[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
	[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* DIV4 clocks */
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
	CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

	/* MSTP32 clocks */
	{
		/* SCIF5 */
		.dev_id		= "sh-sci.5",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP029],
	}, {
		/* SCIF4 */
		.dev_id		= "sh-sci.4",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP028],
	}, {
		/* SCIF3 */
		.dev_id		= "sh-sci.3",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP027],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP026],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP025],
	}, {
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP024],
	},
	CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
	CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
	CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
	CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
	CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
	CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
	{
		/* TMU0 */
		.dev_id		= "sh_tmu.0",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP008],
	}, {
		/* TMU1 */
		.dev_id		= "sh_tmu.1",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP008],
	}, {
		/* TMU2 */
		.dev_id		= "sh_tmu.2",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP008],
	}, {
		/* TMU3 */
		.dev_id		= "sh_tmu.3",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP009],
	}, {
		/* TMU4 */
		.dev_id		= "sh_tmu.4",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP009],
	}, {
		/* TMU5 */
		.dev_id		= "sh_tmu.5",
		.con_id		= "tmu_fck",
		.clk		= &mstp_clks[MSTP009],
	},
	CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
	CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
	CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
	CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
	CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
};

int __init arch_clk_init(void)
{
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(clks); i++)
		ret |= clk_register(clks[i]);
	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
					   &div4_table);
	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
32351a28 PM	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7785.c
	3	*
	4	* SH7785 support for the clock framework
	5	*
c55fbdd3	6	* Copyright (C) 2007 - 2010 Paul Mundt
32351a28 PM	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/kernel.h>
a77b5ac0 PM	14	#include <linux/clk.h>
a77b5ac0 PM	15	#include <linux/io.h>
cc96eace	16	#include <linux/cpufreq.h>
c55fbdd3	17	#include <asm/clkdev.h>
32351a28 PM	18	#include <asm/clock.h>
32351a28 PM	19	#include <asm/freq.h>
1823f6d5	20	#include <cpu/sh7785.h>
32351a28	21
43909a93 MD	22	/*
	23	* Default rate for the root input clock, reset this with clk_set_rate()
	24	* from the platform code.
	25	*/
	26	static struct clk extal_clk = {
	27	.name = "extal",
	28	.id = -1,
	29	.rate = 33333333,
32351a28 PM	30	};
32351a28 PM	31
c9904dd1 MD	32	static unsigned long pll_recalc(struct clk *clk)
c9904dd1 MD	33	{
1823f6d5 MD	34	int multiplier;
1823f6d5 MD	35
0d4fdbb6	36	multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72;
1823f6d5 MD	37
1823f6d5 MD	38	return clk->parent->rate * multiplier;
c9904dd1 MD	39	}
	40
	41	static struct clk_ops pll_clk_ops = {
	42	.recalc = pll_recalc,
	43	};
	44
c9904dd1 MD	45	static struct clk pll_clk = {
	46	.name = "pll_clk",
	47	.id = -1,
	48	.ops = &pll_clk_ops,
	49	.parent = &extal_clk,
	50	.flags = CLK_ENABLE_ON_INIT,
	51	};
	52
43909a93 MD	53	static struct clk *clks[] = {
	54	&extal_clk,
	55	&pll_clk,
32351a28 PM	56	};
32351a28 PM	57
43909a93 MD	58	static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
43909a93 MD	59	24, 32, 36, 48 };
32351a28	60
0a5f337e	61	static struct clk_div_mult_table div4_div_mult_table = {
43909a93 MD	62	.divisors = div2,
43909a93 MD	63	.nr_divisors = ARRAY_SIZE(div2),
a77b5ac0	64	};
32351a28	65
0a5f337e MD	66	static struct clk_div4_table div4_table = {
	67	.div_mult_table = &div4_div_mult_table,
	68	};
	69
43909a93 MD	70	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
43909a93 MD	71	DIV4_DU, DIV4_P, DIV4_NR };
32351a28	72
914ebf0b MD	73	#define DIV4(_bit, _mask, _flags) \
914ebf0b MD	74	SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
32351a28	75
43909a93	76	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	77	[DIV4_P] = DIV4(0, 0x0f80, 0),
	78	[DIV4_DU] = DIV4(4, 0x0ff0, 0),
	79	[DIV4_GA] = DIV4(8, 0x0030, 0),
	80	[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
	81	[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
	82	[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
	83	[DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
	84	[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
32351a28 PM	85	};
32351a28 PM	86
549b5e35 PM	87	#define MSTPCR0 0xffc80030
	88	#define MSTPCR1 0xffc80034
	89
5b10a27e MD	90	enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
	91	MSTP021, MSTP020, MSTP017, MSTP016,
	92	MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
	93	MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
	94	MSTP_NR };
	95
	96	static struct clk mstp_clks[MSTP_NR] = {
549b5e35	97	/* MSTPCR0 */
c77a9c3e MD	98	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
	99	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
	100	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
	101	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
	102	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
	103	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
	104	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	105	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	106	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	107	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
	108	[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
	109	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
	110	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
	111	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
	112	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
	113	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
549b5e35 PM	114
549b5e35 PM	115	/* MSTPCR1 */
c77a9c3e MD	116	[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
	117	[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
	118	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
	119	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
	120	[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
549b5e35 PM	121	};
549b5e35 PM	122
eb85dcaa MD	123	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
eb85dcaa MD	124
c55fbdd3	125	static struct clk_lookup lookups[] = {
956f7f44 MD	126	/* DIV4 clocks */
	127	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	128	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
	129	CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
	130	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
	131	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	132	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	133	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	134	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	135
eb85dcaa MD	136	/* MSTP32 clocks */
	137	{
	138	/* SCIF5 */
	139	.dev_id = "sh-sci.5",
	140	.con_id = "sci_fck",
	141	.clk = &mstp_clks[MSTP029],
	142	}, {
	143	/* SCIF4 */
	144	.dev_id = "sh-sci.4",
	145	.con_id = "sci_fck",
	146	.clk = &mstp_clks[MSTP028],
	147	}, {
	148	/* SCIF3 */
	149	.dev_id = "sh-sci.3",
	150	.con_id = "sci_fck",
	151	.clk = &mstp_clks[MSTP027],
	152	}, {
	153	/* SCIF2 */
	154	.dev_id = "sh-sci.2",
	155	.con_id = "sci_fck",
	156	.clk = &mstp_clks[MSTP026],
	157	}, {
	158	/* SCIF1 */
	159	.dev_id = "sh-sci.1",
	160	.con_id = "sci_fck",
	161	.clk = &mstp_clks[MSTP025],
	162	}, {
	163	/* SCIF0 */
	164	.dev_id = "sh-sci.0",
	165	.con_id = "sci_fck",
	166	.clk = &mstp_clks[MSTP024],
	167	},
	168	CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
	169	CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
	170	CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
	171	CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
	172	CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
	173	CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
c55fbdd3 PM	174	{
	175	/* TMU0 */
	176	.dev_id = "sh_tmu.0",
	177	.con_id = "tmu_fck",
5b10a27e	178	.clk = &mstp_clks[MSTP008],
c55fbdd3 PM	179	}, {
	180	/* TMU1 */
	181	.dev_id = "sh_tmu.1",
	182	.con_id = "tmu_fck",
5b10a27e	183	.clk = &mstp_clks[MSTP008],
c55fbdd3 PM	184	}, {
	185	/* TMU2 */
	186	.dev_id = "sh_tmu.2",
	187	.con_id = "tmu_fck",
5b10a27e	188	.clk = &mstp_clks[MSTP008],
c55fbdd3 PM	189	}, {
	190	/* TMU3 */
	191	.dev_id = "sh_tmu.3",
	192	.con_id = "tmu_fck",
5b10a27e	193	.clk = &mstp_clks[MSTP009],
c55fbdd3 PM	194	}, {
	195	/* TMU4 */
	196	.dev_id = "sh_tmu.4",
	197	.con_id = "tmu_fck",
5b10a27e	198	.clk = &mstp_clks[MSTP009],
c55fbdd3 PM	199	}, {
	200	/* TMU5 */
	201	.dev_id = "sh_tmu.5",
	202	.con_id = "tmu_fck",
5b10a27e	203	.clk = &mstp_clks[MSTP009],
c55fbdd3	204	},
eb85dcaa MD	205	CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
	206	CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
	207	CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
	208	CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
	209	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
	210	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
	211	CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
c55fbdd3 PM	212	};
c55fbdd3 PM	213
9fe5ee0e	214	int __init arch_clk_init(void)
32351a28	215	{
f5c84cf5	216	int i, ret = 0;
32351a28	217
a77b5ac0 PM	218	for (i = 0; i < ARRAY_SIZE(clks); i++)
a77b5ac0 PM	219	ret \|= clk_register(clks[i]);
c55fbdd3 PM	220	for (i = 0; i < ARRAY_SIZE(lookups); i++)
c55fbdd3 PM	221	clkdev_add(&lookups[i]);
e89d53e6	222
43909a93 MD	223	if (!ret)
	224	ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
	225	&div4_table);
e89d53e6	226	if (!ret)
5b10a27e	227	ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
32351a28	228
f5c84cf5	229	return ret;
32351a28	230	}