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32351a28 PM |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7785.c | |
3 | * | |
4 | * SH7785 support for the clock framework | |
5 | * | |
c55fbdd3 | 6 | * Copyright (C) 2007 - 2010 Paul Mundt |
32351a28 PM |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
a77b5ac0 PM |
14 | #include <linux/clk.h> |
15 | #include <linux/io.h> | |
cc96eace | 16 | #include <linux/cpufreq.h> |
c55fbdd3 | 17 | #include <asm/clkdev.h> |
32351a28 PM |
18 | #include <asm/clock.h> |
19 | #include <asm/freq.h> | |
1823f6d5 | 20 | #include <cpu/sh7785.h> |
32351a28 | 21 | |
43909a93 MD |
22 | /* |
23 | * Default rate for the root input clock, reset this with clk_set_rate() | |
24 | * from the platform code. | |
25 | */ | |
26 | static struct clk extal_clk = { | |
27 | .name = "extal", | |
28 | .id = -1, | |
29 | .rate = 33333333, | |
32351a28 PM |
30 | }; |
31 | ||
c9904dd1 MD |
32 | static unsigned long pll_recalc(struct clk *clk) |
33 | { | |
1823f6d5 MD |
34 | int multiplier; |
35 | ||
0d4fdbb6 | 36 | multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; |
1823f6d5 MD |
37 | |
38 | return clk->parent->rate * multiplier; | |
c9904dd1 MD |
39 | } |
40 | ||
41 | static struct clk_ops pll_clk_ops = { | |
42 | .recalc = pll_recalc, | |
43 | }; | |
44 | ||
c9904dd1 MD |
45 | static struct clk pll_clk = { |
46 | .name = "pll_clk", | |
47 | .id = -1, | |
48 | .ops = &pll_clk_ops, | |
49 | .parent = &extal_clk, | |
50 | .flags = CLK_ENABLE_ON_INIT, | |
51 | }; | |
52 | ||
43909a93 MD |
53 | static struct clk *clks[] = { |
54 | &extal_clk, | |
55 | &pll_clk, | |
32351a28 PM |
56 | }; |
57 | ||
43909a93 MD |
58 | static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, |
59 | 24, 32, 36, 48 }; | |
32351a28 | 60 | |
0a5f337e | 61 | static struct clk_div_mult_table div4_div_mult_table = { |
43909a93 MD |
62 | .divisors = div2, |
63 | .nr_divisors = ARRAY_SIZE(div2), | |
a77b5ac0 | 64 | }; |
32351a28 | 65 | |
0a5f337e MD |
66 | static struct clk_div4_table div4_table = { |
67 | .div_mult_table = &div4_div_mult_table, | |
68 | }; | |
69 | ||
43909a93 MD |
70 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, |
71 | DIV4_DU, DIV4_P, DIV4_NR }; | |
32351a28 | 72 | |
43909a93 MD |
73 | #define DIV4(_str, _bit, _mask, _flags) \ |
74 | SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) | |
32351a28 | 75 | |
43909a93 MD |
76 | struct clk div4_clks[DIV4_NR] = { |
77 | [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), | |
78 | [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), | |
79 | [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), | |
80 | [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), | |
81 | [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), | |
82 | [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), | |
83 | [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), | |
84 | [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), | |
32351a28 PM |
85 | }; |
86 | ||
549b5e35 PM |
87 | #define MSTPCR0 0xffc80030 |
88 | #define MSTPCR1 0xffc80034 | |
89 | ||
e89d53e6 | 90 | static struct clk mstp_clks[] = { |
549b5e35 | 91 | /* MSTPCR0 */ |
c7ed1ab3 PM |
92 | SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), |
93 | SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), | |
94 | SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), | |
95 | SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), | |
96 | SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), | |
97 | SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), | |
43909a93 MD |
98 | SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), |
99 | SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), | |
100 | SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), | |
101 | SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), | |
102 | SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), | |
103 | SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), | |
104 | SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), | |
105 | SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), | |
106 | SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), | |
107 | SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), | |
549b5e35 PM |
108 | |
109 | /* MSTPCR1 */ | |
e89d53e6 MD |
110 | SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), |
111 | SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), | |
112 | SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), | |
113 | SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), | |
114 | SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), | |
549b5e35 PM |
115 | }; |
116 | ||
c55fbdd3 PM |
117 | static struct clk_lookup lookups[] = { |
118 | { | |
119 | /* TMU0 */ | |
120 | .dev_id = "sh_tmu.0", | |
121 | .con_id = "tmu_fck", | |
122 | .clk = &mstp_clks[13], /* tmu012_fck */ | |
123 | }, { | |
124 | /* TMU1 */ | |
125 | .dev_id = "sh_tmu.1", | |
126 | .con_id = "tmu_fck", | |
127 | .clk = &mstp_clks[13], | |
128 | }, { | |
129 | /* TMU2 */ | |
130 | .dev_id = "sh_tmu.2", | |
131 | .con_id = "tmu_fck", | |
132 | .clk = &mstp_clks[13], | |
133 | }, { | |
134 | /* TMU3 */ | |
135 | .dev_id = "sh_tmu.3", | |
136 | .con_id = "tmu_fck", | |
137 | .clk = &mstp_clks[12], /* tmu345_fck */ | |
138 | }, { | |
139 | /* TMU4 */ | |
140 | .dev_id = "sh_tmu.4", | |
141 | .con_id = "tmu_fck", | |
142 | .clk = &mstp_clks[12], | |
143 | }, { | |
144 | /* TMU5 */ | |
145 | .dev_id = "sh_tmu.5", | |
146 | .con_id = "tmu_fck", | |
147 | .clk = &mstp_clks[12], | |
148 | }, | |
149 | }; | |
150 | ||
9fe5ee0e | 151 | int __init arch_clk_init(void) |
32351a28 | 152 | { |
f5c84cf5 | 153 | int i, ret = 0; |
32351a28 | 154 | |
a77b5ac0 PM |
155 | for (i = 0; i < ARRAY_SIZE(clks); i++) |
156 | ret |= clk_register(clks[i]); | |
c55fbdd3 PM |
157 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
158 | clkdev_add(&lookups[i]); | |
e89d53e6 | 159 | |
43909a93 MD |
160 | if (!ret) |
161 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | |
162 | &div4_table); | |
e89d53e6 MD |
163 | if (!ret) |
164 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | |
32351a28 | 165 | |
f5c84cf5 | 166 | return ret; |
32351a28 | 167 | } |