[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7343.c

/*
 * SH7343 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_timer.h>
#include <asm/clock.h>

/* Serial */
static struct plat_sci_port scif0_platform_data = {
	.mapbase        = 0xffe00000,
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type           = PORT_SCIF,
	.irqs           = SCIx_IRQ_MUXED(evt2irq(0xC00)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase        = 0xffe10000,
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type           = PORT_SCIF,
	.irqs           = SCIx_IRQ_MUXED(evt2irq(0xC20)),
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase        = 0xffe20000,
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type           = PORT_SCIF,
	.irqs           = SCIx_IRQ_MUXED(evt2irq(0xC40)),
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase        = 0xffe30000,
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type           = PORT_SCIF,
	.irqs           = SCIx_IRQ_MUXED(evt2irq(0xC60)),
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct resource iic0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic0_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic0_resources),
	.resource       = iic0_resources,
};

static struct resource iic1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start  = 0x04750000,
		.end    = 0x04750017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 44,
		.end    = 47,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic1_device = {
	.name           = "i2c-sh_mobile",
	.id             = 1, /* "i2c1" clock */
	.num_resources  = ARRAY_SIZE(iic1_resources),
	.resource       = iic1_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = 54,
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
};

static struct uio_info jpu_platform_data = {
	.name = "JPU",
	.version = "0",
	.irq = 27,
};

static struct resource jpu_resources[] = {
	[0] = {
		.name	= "JPU",
		.start	= 0xfea00000,
		.end	= 0xfea102d3,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device jpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &jpu_platform_data,
	},
	.resource	= jpu_resources,
	.num_resources	= ARRAY_SIZE(jpu_resources),
};

static struct sh_timer_config cmt_platform_data = {
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clockevent_rating = 125,
	.clocksource_rating = 200,
};

static struct resource cmt_resources[] = {
	[0] = {
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 104,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct sh_timer_config tmu0_platform_data = {
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 16,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 17,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.channel_offset = 0x1c,
	.timer_bit = 2,
};

static struct resource tmu2_resources[] = {
	[0] = {
		.start	= 0xffd80020,
		.end	= 0xffd8002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 18,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct platform_device *sh7343_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&iic0_device,
	&iic1_device,
	&vpu_device,
	&veu_device,
	&jpu_device,
};

static int __init sh7343_devices_setup(void)
{
	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);

	return platform_add_devices(sh7343_devices,
				    ARRAY_SIZE(sh7343_devices));
}
arch_initcall(sh7343_devices_setup);

static struct platform_device *sh7343_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7343_early_devices,
				   ARRAY_SIZE(sh7343_early_devices));
}

enum {
	UNUSED = 0,
	ENABLED,
	DISABLED,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF, SCIF1, SCIF2, SCIF3,
	SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	IRDA, SDHI, CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	JPU, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
	INTC_GROUP(USB, USBI0, USBI1),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_desc intc_desc __initdata = {
	.name = "sh7343",
	.force_enable = ENABLED,
	.force_disable = DISABLED,
	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
			   prio_registers, sense_registers, ack_registers),
};

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
e5723e0e PM	1	/*
	2	* SH7343 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
c901c96c	14	#include <linux/uio_driver.h>
46a12f74	15	#include <linux/sh_timer.h>
8fa509ab	16	#include <asm/clock.h>
e5723e0e	17
bcac24d0 MD	18	/* Serial */
	19	static struct plat_sci_port scif0_platform_data = {
	20	.mapbase = 0xffe00000,
	21	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	22	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
f43dc23d PM	23	.scbrr_algo_id = SCBRR_ALGO_2,
bcac24d0	24	.type = PORT_SCIF,
eb0cdbe6	25	.irqs = SCIx_IRQ_MUXED(evt2irq(0xC00)),
bcac24d0 MD	26	};
	27
	28	static struct platform_device scif0_device = {
	29	.name = "sh-sci",
	30	.id = 0,
	31	.dev = {
	32	.platform_data = &scif0_platform_data,
	33	},
	34	};
	35
	36	static struct plat_sci_port scif1_platform_data = {
	37	.mapbase = 0xffe10000,
	38	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	39	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
f43dc23d PM	40	.scbrr_algo_id = SCBRR_ALGO_2,
bcac24d0	41	.type = PORT_SCIF,
eb0cdbe6	42	.irqs = SCIx_IRQ_MUXED(evt2irq(0xC20)),
bcac24d0 MD	43	};
	44
	45	static struct platform_device scif1_device = {
	46	.name = "sh-sci",
	47	.id = 1,
	48	.dev = {
	49	.platform_data = &scif1_platform_data,
	50	},
	51	};
	52
	53	static struct plat_sci_port scif2_platform_data = {
	54	.mapbase = 0xffe20000,
	55	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	56	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
f43dc23d PM	57	.scbrr_algo_id = SCBRR_ALGO_2,
bcac24d0	58	.type = PORT_SCIF,
00d6025e	59	.irqs = SCIx_IRQ_MUXED(evt2irq(0xC40)),
bcac24d0 MD	60	};
	61
	62	static struct platform_device scif2_device = {
	63	.name = "sh-sci",
	64	.id = 2,
	65	.dev = {
	66	.platform_data = &scif2_platform_data,
	67	},
	68	};
	69
	70	static struct plat_sci_port scif3_platform_data = {
	71	.mapbase = 0xffe30000,
	72	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	73	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
f43dc23d PM	74	.scbrr_algo_id = SCBRR_ALGO_2,
bcac24d0	75	.type = PORT_SCIF,
eb0cdbe6	76	.irqs = SCIx_IRQ_MUXED(evt2irq(0xC60)),
bcac24d0 MD	77	};
	78
	79	static struct platform_device scif3_device = {
	80	.name = "sh-sci",
	81	.id = 3,
	82	.dev = {
	83	.platform_data = &scif3_platform_data,
	84	},
	85	};
	86
7549079d MD	87	static struct resource iic0_resources[] = {
	88	[0] = {
	89	.name = "IIC0",
	90	.start = 0x04470000,
	91	.end = 0x04470017,
	92	.flags = IORESOURCE_MEM,
	93	},
	94	[1] = {
	95	.start = 96,
	96	.end = 99,
	97	.flags = IORESOURCE_IRQ,
	98	},
	99	};
	100
	101	static struct platform_device iic0_device = {
	102	.name = "i2c-sh_mobile",
a5616bd0	103	.id = 0, /* "i2c0" clock */
7549079d MD	104	.num_resources = ARRAY_SIZE(iic0_resources),
	105	.resource = iic0_resources,
	106	};
	107
	108	static struct resource iic1_resources[] = {
	109	[0] = {
	110	.name = "IIC1",
	111	.start = 0x04750000,
	112	.end = 0x04750017,
	113	.flags = IORESOURCE_MEM,
	114	},
	115	[1] = {
	116	.start = 44,
	117	.end = 47,
	118	.flags = IORESOURCE_IRQ,
	119	},
	120	};
	121
	122	static struct platform_device iic1_device = {
	123	.name = "i2c-sh_mobile",
a5616bd0	124	.id = 1, /* "i2c1" clock */
7549079d MD	125	.num_resources = ARRAY_SIZE(iic1_resources),
	126	.resource = iic1_resources,
	127	};
	128
c901c96c MD	129	static struct uio_info vpu_platform_data = {
	130	.name = "VPU4",
	131	.version = "0",
	132	.irq = 60,
	133	};
	134
	135	static struct resource vpu_resources[] = {
	136	[0] = {
	137	.name = "VPU",
	138	.start = 0xfe900000,
	139	.end = 0xfe9022eb,
	140	.flags = IORESOURCE_MEM,
	141	},
1eca5c92 MD	142	[1] = {
	143	/* place holder for contiguous memory */
	144	},
c901c96c MD	145	};
	146
	147	static struct platform_device vpu_device = {
	148	.name = "uio_pdrv_genirq",
	149	.id = 0,
	150	.dev = {
	151	.platform_data = &vpu_platform_data,
	152	},
	153	.resource = vpu_resources,
	154	.num_resources = ARRAY_SIZE(vpu_resources),
	155	};
	156
	157	static struct uio_info veu_platform_data = {
	158	.name = "VEU",
	159	.version = "0",
	160	.irq = 54,
	161	};
	162
	163	static struct resource veu_resources[] = {
	164	[0] = {
	165	.name = "VEU",
	166	.start = 0xfe920000,
	167	.end = 0xfe9200b7,
	168	.flags = IORESOURCE_MEM,
	169	},
1eca5c92 MD	170	[1] = {
	171	/* place holder for contiguous memory */
	172	},
c901c96c MD	173	};
	174
	175	static struct platform_device veu_device = {
	176	.name = "uio_pdrv_genirq",
	177	.id = 1,
	178	.dev = {
	179	.platform_data = &veu_platform_data,
	180	},
	181	.resource = veu_resources,
	182	.num_resources = ARRAY_SIZE(veu_resources),
	183	};
	184
3442c0d6 MD	185	static struct uio_info jpu_platform_data = {
	186	.name = "JPU",
	187	.version = "0",
	188	.irq = 27,
	189	};
	190
	191	static struct resource jpu_resources[] = {
	192	[0] = {
	193	.name = "JPU",
	194	.start = 0xfea00000,
	195	.end = 0xfea102d3,
	196	.flags = IORESOURCE_MEM,
	197	},
	198	[1] = {
	199	/* place holder for contiguous memory */
	200	},
	201	};
	202
	203	static struct platform_device jpu_device = {
	204	.name = "uio_pdrv_genirq",
	205	.id = 2,
	206	.dev = {
	207	.platform_data = &jpu_platform_data,
	208	},
	209	.resource = jpu_resources,
	210	.num_resources = ARRAY_SIZE(jpu_resources),
	211	};
	212
46a12f74	213	static struct sh_timer_config cmt_platform_data = {
424f59d0 MD	214	.channel_offset = 0x60,
424f59d0 MD	215	.timer_bit = 5,
424f59d0 MD	216	.clockevent_rating = 125,
	217	.clocksource_rating = 200,
	218	};
	219
	220	static struct resource cmt_resources[] = {
	221	[0] = {
424f59d0 MD	222	.start = 0x044a0060,
	223	.end = 0x044a006b,
	224	.flags = IORESOURCE_MEM,
	225	},
	226	[1] = {
	227	.start = 104,
	228	.flags = IORESOURCE_IRQ,
	229	},
	230	};
	231
	232	static struct platform_device cmt_device = {
	233	.name = "sh_cmt",
	234	.id = 0,
	235	.dev = {
	236	.platform_data = &cmt_platform_data,
	237	},
	238	.resource = cmt_resources,
	239	.num_resources = ARRAY_SIZE(cmt_resources),
	240	};
	241
e37677a4	242	static struct sh_timer_config tmu0_platform_data = {
e37677a4 MD	243	.channel_offset = 0x04,
e37677a4 MD	244	.timer_bit = 0,
e37677a4 MD	245	.clockevent_rating = 200,
	246	};
	247
	248	static struct resource tmu0_resources[] = {
	249	[0] = {
e37677a4 MD	250	.start = 0xffd80008,
	251	.end = 0xffd80013,
	252	.flags = IORESOURCE_MEM,
	253	},
	254	[1] = {
	255	.start = 16,
	256	.flags = IORESOURCE_IRQ,
	257	},
	258	};
	259
	260	static struct platform_device tmu0_device = {
	261	.name = "sh_tmu",
	262	.id = 0,
	263	.dev = {
	264	.platform_data = &tmu0_platform_data,
	265	},
	266	.resource = tmu0_resources,
	267	.num_resources = ARRAY_SIZE(tmu0_resources),
	268	};
	269
	270	static struct sh_timer_config tmu1_platform_data = {
e37677a4 MD	271	.channel_offset = 0x10,
e37677a4 MD	272	.timer_bit = 1,
e37677a4 MD	273	.clocksource_rating = 200,
	274	};
	275
	276	static struct resource tmu1_resources[] = {
	277	[0] = {
e37677a4 MD	278	.start = 0xffd80014,
	279	.end = 0xffd8001f,
	280	.flags = IORESOURCE_MEM,
	281	},
	282	[1] = {
	283	.start = 17,
	284	.flags = IORESOURCE_IRQ,
	285	},
	286	};
	287
	288	static struct platform_device tmu1_device = {
	289	.name = "sh_tmu",
	290	.id = 1,
	291	.dev = {
	292	.platform_data = &tmu1_platform_data,
	293	},
	294	.resource = tmu1_resources,
	295	.num_resources = ARRAY_SIZE(tmu1_resources),
	296	};
	297
	298	static struct sh_timer_config tmu2_platform_data = {
e37677a4 MD	299	.channel_offset = 0x1c,
e37677a4 MD	300	.timer_bit = 2,
e37677a4 MD	301	};
	302
	303	static struct resource tmu2_resources[] = {
	304	[0] = {
e37677a4 MD	305	.start = 0xffd80020,
	306	.end = 0xffd8002b,
	307	.flags = IORESOURCE_MEM,
	308	},
	309	[1] = {
	310	.start = 18,
	311	.flags = IORESOURCE_IRQ,
	312	},
	313	};
	314
	315	static struct platform_device tmu2_device = {
	316	.name = "sh_tmu",
	317	.id = 2,
	318	.dev = {
	319	.platform_data = &tmu2_platform_data,
	320	},
	321	.resource = tmu2_resources,
	322	.num_resources = ARRAY_SIZE(tmu2_resources),
	323	};
	324
e5723e0e	325	static struct platform_device *sh7343_devices[] __initdata = {
bcac24d0 MD	326	&scif0_device,
	327	&scif1_device,
	328	&scif2_device,
	329	&scif3_device,
424f59d0	330	&cmt_device,
e37677a4 MD	331	&tmu0_device,
	332	&tmu1_device,
	333	&tmu2_device,
7549079d MD	334	&iic0_device,
7549079d MD	335	&iic1_device,
c901c96c MD	336	&vpu_device,
c901c96c MD	337	&veu_device,
3442c0d6	338	&jpu_device,
e5723e0e PM	339	};
	340
	341	static int __init sh7343_devices_setup(void)
	342	{
1eca5c92 MD	343	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	344	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
3442c0d6	345	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
8fa509ab	346
e5723e0e PM	347	return platform_add_devices(sh7343_devices,
	348	ARRAY_SIZE(sh7343_devices));
	349	}
ba9a6337	350	arch_initcall(sh7343_devices_setup);
35f3abe9	351
28fde686	352	static struct platform_device *sh7343_early_devices[] __initdata = {
bcac24d0 MD	353	&scif0_device,
	354	&scif1_device,
	355	&scif2_device,
	356	&scif3_device,
28fde686	357	&cmt_device,
e37677a4 MD	358	&tmu0_device,
	359	&tmu1_device,
	360	&tmu2_device,
28fde686 MD	361	};
	362
	363	void __init plat_early_device_setup(void)
	364	{
	365	early_platform_add_devices(sh7343_early_devices,
	366	ARRAY_SIZE(sh7343_early_devices));
	367	}
	368
a4e1d084 YS	369	enum {
a4e1d084 YS	370	UNUSED = 0,
3a0f4c78 MD	371	ENABLED,
3a0f4c78 MD	372	DISABLED,
a4e1d084 YS	373
	374	/* interrupt sources */
	375	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	376	DMAC0, DMAC1, DMAC2, DMAC3,
	377	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	378	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	379	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	380	DMAC4, DMAC5, DMAC_DADERR,
	381	KEYSC,
551ea2b4	382	SCIF, SCIF1, SCIF2, SCIF3,
a4e1d084 YS	383	SIOF0, SIOF1, SIO,
	384	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	385	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	386	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	387	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
3a0f4c78	388	IRDA, SDHI, CMT, TSIF, SIU,
a4e1d084 YS	389	TMU0, TMU1, TMU2,
	390	JPU, LCDC,
	391
	392	/* interrupt groups */
	393
3a0f4c78	394	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
a4e1d084 YS	395	};
	396
	397	static struct intc_vect vectors[] __initdata = {
	398	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	399	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	400	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	401	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	402	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	403	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	404	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	405	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	406	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	407	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	408	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	409	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	410	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	411	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	412	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	413	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	414	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	415	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	416	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	417	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	418	INTC_VECT(SIO, 0xd00),
	419	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	420	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	421	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	422	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
3a0f4c78 MD	423	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
3a0f4c78 MD	424	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
a4e1d084 YS	425	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	426	INTC_VECT(SIU, 0xf80),
	427	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	428	INTC_VECT(TMU2, 0x440),
	429	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
	430	};
	431
	432	static struct intc_group groups[] __initdata = {
	433	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	434	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	435	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	436	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	437	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	438	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	439	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	440	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	441	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
a4e1d084 YS	442	INTC_GROUP(USB, USBI0, USBI1),
	443	};
	444
	445	static struct intc_mask_reg mask_registers[] __initdata = {
	446	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	447	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	448	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	449	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
	450	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	451	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	452	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	453	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	454	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	455	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	456	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	457	{ 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	458	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	459	{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	460	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	461	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
3a0f4c78	462	{ DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
a4e1d084 YS	463	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	464	{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	465	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	466	{ MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	467	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	468	{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	469	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	470	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	471	};
	472
	473	static struct intc_prio_reg prio_registers[] __initdata = {
	474	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	475	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	476	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	477	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	478	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	479	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	480	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	481	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	482	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	483	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	484	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	485	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	486	};
	487
	488	static struct intc_sense_reg sense_registers[] __initdata = {
	489	{ 0xa414001c, 16, 2, /* ICR1 */
	490	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	491	};
	492
	493	static struct intc_mask_reg ack_registers[] __initdata = {
	494	{ 0xa4140024, 0, 8, /* INTREQ00 */
	495	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	496	};
	497
3a0f4c78 MD	498	static struct intc_desc intc_desc __initdata = {
	499	.name = "sh7343",
	500	.force_enable = ENABLED,
	501	.force_disable = DISABLED,
	502	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
	503	prio_registers, sense_registers, ack_registers),
	504	};
a4e1d084	505
35f3abe9 PM	506	void __init plat_irq_setup(void)
35f3abe9 PM	507	{
a4e1d084	508	register_intc_controller(&intc_desc);
35f3abe9	509	}