[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7343.c

/*
 * SH7343 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>

static struct resource iic0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic0_device = {
	.name           = "i2c-sh_mobile",
	.num_resources  = ARRAY_SIZE(iic0_resources),
	.resource       = iic0_resources,
};

static struct resource iic1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start  = 0x04750000,
		.end    = 0x04750017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 44,
		.end    = 47,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic1_device = {
	.name           = "i2c-sh_mobile",
	.num_resources  = ARRAY_SIZE(iic1_resources),
	.resource       = iic1_resources,
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xffe00000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 80, 81, 83, 82 },
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7343_devices[] __initdata = {
	&iic0_device,
	&iic1_device,
	&sci_device,
};

static int __init sh7343_devices_setup(void)
{
	return platform_add_devices(sh7343_devices,
				    ARRAY_SIZE(sh7343_devices));
}
__initcall(sh7343_devices_setup);

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF, SCIF1, SCIF2, SCIF3, SCIF4,
	SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	IRDA,
	SDHI0, SDHI1, SDHI2, SDHI3,
	CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	JPU, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
	INTC_GROUP(USB, USBI0, USBI1),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
e5723e0e PM	1	/*
	2	* SH7343 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
e5723e0e	14
7549079d MD	15	static struct resource iic0_resources[] = {
	16	[0] = {
	17	.name = "IIC0",
	18	.start = 0x04470000,
	19	.end = 0x04470017,
	20	.flags = IORESOURCE_MEM,
	21	},
	22	[1] = {
	23	.start = 96,
	24	.end = 99,
	25	.flags = IORESOURCE_IRQ,
	26	},
	27	};
	28
	29	static struct platform_device iic0_device = {
	30	.name = "i2c-sh_mobile",
	31	.num_resources = ARRAY_SIZE(iic0_resources),
	32	.resource = iic0_resources,
	33	};
	34
	35	static struct resource iic1_resources[] = {
	36	[0] = {
	37	.name = "IIC1",
	38	.start = 0x04750000,
	39	.end = 0x04750017,
	40	.flags = IORESOURCE_MEM,
	41	},
	42	[1] = {
	43	.start = 44,
	44	.end = 47,
	45	.flags = IORESOURCE_IRQ,
	46	},
	47	};
	48
	49	static struct platform_device iic1_device = {
	50	.name = "i2c-sh_mobile",
	51	.num_resources = ARRAY_SIZE(iic1_resources),
	52	.resource = iic1_resources,
	53	};
	54
e5723e0e PM	55	static struct plat_sci_port sci_platform_data[] = {
	56	{
	57	.mapbase = 0xffe00000,
	58	.flags = UPF_BOOT_AUTOCONF,
	59	.type = PORT_SCIF,
	60	.irqs = { 80, 81, 83, 82 },
	61	}, {
	62	.flags = 0,
	63	}
	64	};
	65
	66	static struct platform_device sci_device = {
	67	.name = "sh-sci",
	68	.id = -1,
	69	.dev = {
	70	.platform_data = sci_platform_data,
	71	},
	72	};
	73
	74	static struct platform_device *sh7343_devices[] __initdata = {
7549079d MD	75	&iic0_device,
7549079d MD	76	&iic1_device,
e5723e0e PM	77	&sci_device,
	78	};
	79
	80	static int __init sh7343_devices_setup(void)
	81	{
	82	return platform_add_devices(sh7343_devices,
	83	ARRAY_SIZE(sh7343_devices));
	84	}
	85	__initcall(sh7343_devices_setup);
35f3abe9	86
a4e1d084 YS	87	enum {
	88	UNUSED = 0,
	89
	90	/* interrupt sources */
	91	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	92	DMAC0, DMAC1, DMAC2, DMAC3,
	93	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	94	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	95	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	96	DMAC4, DMAC5, DMAC_DADERR,
	97	KEYSC,
	98	SCIF, SCIF1, SCIF2, SCIF3, SCIF4,
	99	SIOF0, SIOF1, SIO,
	100	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	101	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	102	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	103	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	104	IRDA,
	105	SDHI0, SDHI1, SDHI2, SDHI3,
	106	CMT, TSIF, SIU,
	107	TMU0, TMU1, TMU2,
	108	JPU, LCDC,
	109
	110	/* interrupt groups */
	111
	112	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
	113	};
	114
	115	static struct intc_vect vectors[] __initdata = {
	116	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	117	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	118	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	119	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	120	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	121	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	122	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	123	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	124	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	125	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	126	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	127	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	128	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	129	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	130	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	131	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	132	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	133	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	134	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	135	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	136	INTC_VECT(SIO, 0xd00),
	137	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	138	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	139	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	140	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	141	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	142	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	143	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	144	INTC_VECT(SIU, 0xf80),
	145	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	146	INTC_VECT(TMU2, 0x440),
	147	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
	148	};
	149
	150	static struct intc_group groups[] __initdata = {
151	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
152	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
153	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
154	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
155	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
156	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
157	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
158	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
159	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
160	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
161	INTC_GROUP(USB, USBI0, USBI1),
162	};
163
164	static struct intc_mask_reg mask_registers[] __initdata = {
165	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
166	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
167	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
168	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
169	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
170	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
171	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
172	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
173	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
174	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
175	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
176	{ 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
177	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
178	{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
179	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
180	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
181	{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
182	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
183	{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
184	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
185	{ MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
186	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
187	{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
188	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
189	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
190	};
191
192	static struct intc_prio_reg prio_registers[] __initdata = {
193	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
194	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
195	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
196	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
197	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
198	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
199	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
200	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
201	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
202	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
203	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
204	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
205	};
206
207	static struct intc_sense_reg sense_registers[] __initdata = {
208	{ 0xa414001c, 16, 2, /* ICR1 */
209	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
210	};
211
212	static struct intc_mask_reg ack_registers[] __initdata = {
213	{ 0xa4140024, 0, 8, /* INTREQ00 */
214	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
215	};
216
217	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
218	mask_registers, prio_registers, sense_registers,
219	ack_registers);
220
35f3abe9 PM	221	void __init plat_irq_setup(void)
35f3abe9 PM	222	{
a4e1d084	223	register_intc_controller(&intc_desc);
35f3abe9	224	}