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sh: intc: Tidy up loglevel mismatches.
[deliverable/linux.git] / arch / sh / kernel / cpu / sh4a / setup-sh7786.c
CommitLineData
55ba99eb
KM		 1/*
2 * SH7786 Setup
3 *
050d4cc7 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
55ba99eb 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
c3d480de 6 * Paul Mundt <paul.mundt@renesas.com>
55ba99eb
KM		 7 *
8 * Based on SH7785 Setup
9 *
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
4c3f450b 22#include <linux/dma-mapping.h>
c3d480de 23#include <linux/sh_timer.h>
050d4cc7 24#include <cpu/dma-register.h>
55ba99eb 25#include <asm/mmzone.h>
050d4cc7 26#include <asm/dmaengine.h>
55ba99eb 27
a9571d7b
MD		 28static struct plat_sci_port scif0_platform_data = {
29 .mapbase = 0xffea0000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 40, 41, 43, 42 },
33};
34
35static struct platform_device scif0_device = {
55ba99eb 36 .name = "sh-sci",
a9571d7b
MD		 37 .id = 0,
38 .dev = {
39 .platform_data = &scif0_platform_data,
40 },
41};
42
43/*
44 * The rest of these all have multiplexed IRQs
45 */
46static struct plat_sci_port scif1_platform_data = {
47 .mapbase = 0xffeb0000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIF,
50 .irqs = { 44, 44, 44, 44 },
51};
52
53static struct platform_device scif1_device = {
54 .name = "sh-sci",
55 .id = 1,
56 .dev = {
57 .platform_data = &scif1_platform_data,
58 },
59};
60
61static struct plat_sci_port scif2_platform_data = {
62 .mapbase = 0xffec0000,
63 .flags = UPF_BOOT_AUTOCONF,
64 .type = PORT_SCIF,
65 .irqs = { 50, 50, 50, 50 },
66};
67
68static struct platform_device scif2_device = {
69 .name = "sh-sci",
70 .id = 2,
71 .dev = {
72 .platform_data = &scif2_platform_data,
73 },
74};
75
76static struct plat_sci_port scif3_platform_data = {
77 .mapbase = 0xffed0000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .type = PORT_SCIF,
80 .irqs = { 51, 51, 51, 51 },
81};
82
83static struct platform_device scif3_device = {
84 .name = "sh-sci",
85 .id = 3,
86 .dev = {
87 .platform_data = &scif3_platform_data,
88 },
89};
90
91static struct plat_sci_port scif4_platform_data = {
92 .mapbase = 0xffee0000,
93 .flags = UPF_BOOT_AUTOCONF,
94 .type = PORT_SCIF,
95 .irqs = { 52, 52, 52, 52 },
96};
97
98static struct platform_device scif4_device = {
99 .name = "sh-sci",
100 .id = 4,
101 .dev = {
102 .platform_data = &scif4_platform_data,
103 },
104};
105
106static struct plat_sci_port scif5_platform_data = {
107 .mapbase = 0xffef0000,
108 .flags = UPF_BOOT_AUTOCONF,
109 .type = PORT_SCIF,
110 .irqs = { 53, 53, 53, 53 },
111};
112
113static struct platform_device scif5_device = {
114 .name = "sh-sci",
115 .id = 5,
55ba99eb 116 .dev = {
a9571d7b 117 .platform_data = &scif5_platform_data,
55ba99eb
KM		 118 },
119};
120
c3d480de 121static struct sh_timer_config tmu0_platform_data = {
c3d480de
PM		 122 .channel_offset = 0x04,
123 .timer_bit = 0,
c3d480de
PM		 124 .clockevent_rating = 200,
125};
126
127static struct resource tmu0_resources[] = {
128 [0] = {
c3d480de
PM		 129 .start = 0xffd80008,
130 .end = 0xffd80013,
131 .flags = IORESOURCE_MEM,
132 },
133 [1] = {
134 .start = 16,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139static struct platform_device tmu0_device = {
140 .name = "sh_tmu",
141 .id = 0,
142 .dev = {
143 .platform_data = &tmu0_platform_data,
144 },
145 .resource = tmu0_resources,
146 .num_resources = ARRAY_SIZE(tmu0_resources),
147};
148
149static struct sh_timer_config tmu1_platform_data = {
c3d480de
PM		 150 .channel_offset = 0x10,
151 .timer_bit = 1,
c3d480de
PM		 152 .clocksource_rating = 200,
153};
154
155static struct resource tmu1_resources[] = {
156 [0] = {
c3d480de
PM		 157 .start = 0xffd80014,
158 .end = 0xffd8001f,
159 .flags = IORESOURCE_MEM,
160 },
161 [1] = {
162 .start = 17,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167static struct platform_device tmu1_device = {
168 .name = "sh_tmu",
169 .id = 1,
170 .dev = {
171 .platform_data = &tmu1_platform_data,
172 },
173 .resource = tmu1_resources,
174 .num_resources = ARRAY_SIZE(tmu1_resources),
175};
176
177static struct sh_timer_config tmu2_platform_data = {
c3d480de
PM		 178 .channel_offset = 0x1c,
179 .timer_bit = 2,
c3d480de
PM		 180};
181
182static struct resource tmu2_resources[] = {
183 [0] = {
c3d480de
PM		 184 .start = 0xffd80020,
185 .end = 0xffd8002f,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = 18,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device tmu2_device = {
195 .name = "sh_tmu",
196 .id = 2,
197 .dev = {
198 .platform_data = &tmu2_platform_data,
199 },
200 .resource = tmu2_resources,
201 .num_resources = ARRAY_SIZE(tmu2_resources),
202};
203
204static struct sh_timer_config tmu3_platform_data = {
c3d480de
PM		 205 .channel_offset = 0x04,
206 .timer_bit = 0,
c3d480de
PM		 207};
208
209static struct resource tmu3_resources[] = {
210 [0] = {
c3d480de
PM		 211 .start = 0xffda0008,
212 .end = 0xffda0013,
213 .flags = IORESOURCE_MEM,
214 },
215 [1] = {
216 .start = 20,
217 .flags = IORESOURCE_IRQ,
218 },
219};
220
221static struct platform_device tmu3_device = {
222 .name = "sh_tmu",
223 .id = 3,
224 .dev = {
225 .platform_data = &tmu3_platform_data,
226 },
227 .resource = tmu3_resources,
228 .num_resources = ARRAY_SIZE(tmu3_resources),
229};
230
231static struct sh_timer_config tmu4_platform_data = {
c3d480de
PM		 232 .channel_offset = 0x10,
233 .timer_bit = 1,
c3d480de
PM		 234};
235
236static struct resource tmu4_resources[] = {
237 [0] = {
c3d480de
PM		 238 .start = 0xffda0014,
239 .end = 0xffda001f,
240 .flags = IORESOURCE_MEM,
241 },
242 [1] = {
243 .start = 21,
244 .flags = IORESOURCE_IRQ,
245 },
246};
247
248static struct platform_device tmu4_device = {
249 .name = "sh_tmu",
250 .id = 4,
251 .dev = {
252 .platform_data = &tmu4_platform_data,
253 },
254 .resource = tmu4_resources,
255 .num_resources = ARRAY_SIZE(tmu4_resources),
256};
257
258static struct sh_timer_config tmu5_platform_data = {
c3d480de
PM		 259 .channel_offset = 0x1c,
260 .timer_bit = 2,
c3d480de
PM		 261};
262
263static struct resource tmu5_resources[] = {
264 [0] = {
c3d480de
PM		 265 .start = 0xffda0020,
266 .end = 0xffda002b,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = 22,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device tmu5_device = {
276 .name = "sh_tmu",
277 .id = 5,
278 .dev = {
279 .platform_data = &tmu5_platform_data,
280 },
281 .resource = tmu5_resources,
282 .num_resources = ARRAY_SIZE(tmu5_resources),
283};
284
285static struct sh_timer_config tmu6_platform_data = {
c3d480de
PM		 286 .channel_offset = 0x04,
287 .timer_bit = 0,
c3d480de
PM		 288};
289
290static struct resource tmu6_resources[] = {
291 [0] = {
c3d480de
PM		 292 .start = 0xffdc0008,
293 .end = 0xffdc0013,
294 .flags = IORESOURCE_MEM,
295 },
296 [1] = {
297 .start = 45,
298 .flags = IORESOURCE_IRQ,
299 },
300};
301
302static struct platform_device tmu6_device = {
303 .name = "sh_tmu",
304 .id = 6,
305 .dev = {
306 .platform_data = &tmu6_platform_data,
307 },
308 .resource = tmu6_resources,
309 .num_resources = ARRAY_SIZE(tmu6_resources),
310};
311
312static struct sh_timer_config tmu7_platform_data = {
c3d480de
PM		 313 .channel_offset = 0x10,
314 .timer_bit = 1,
c3d480de
PM		 315};
316
317static struct resource tmu7_resources[] = {
318 [0] = {
c3d480de
PM		 319 .start = 0xffdc0014,
320 .end = 0xffdc001f,
321 .flags = IORESOURCE_MEM,
322 },
323 [1] = {
324 .start = 45,
325 .flags = IORESOURCE_IRQ,
326 },
327};
328
329static struct platform_device tmu7_device = {
330 .name = "sh_tmu",
331 .id = 7,
332 .dev = {
333 .platform_data = &tmu7_platform_data,
334 },
335 .resource = tmu7_resources,
336 .num_resources = ARRAY_SIZE(tmu7_resources),
337};
338
339static struct sh_timer_config tmu8_platform_data = {
c3d480de
PM		 340 .channel_offset = 0x1c,
341 .timer_bit = 2,
c3d480de
PM		 342};
343
344static struct resource tmu8_resources[] = {
345 [0] = {
c3d480de
PM		 346 .start = 0xffdc0020,
347 .end = 0xffdc002b,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = 45,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device tmu8_device = {
357 .name = "sh_tmu",
358 .id = 8,
359 .dev = {
360 .platform_data = &tmu8_platform_data,
361 },
362 .resource = tmu8_resources,
363 .num_resources = ARRAY_SIZE(tmu8_resources),
364};
365
366static struct sh_timer_config tmu9_platform_data = {
c3d480de
PM		 367 .channel_offset = 0x04,
368 .timer_bit = 0,
c3d480de
PM		 369};
370
371static struct resource tmu9_resources[] = {
372 [0] = {
c3d480de
PM		 373 .start = 0xffde0008,
374 .end = 0xffde0013,
375 .flags = IORESOURCE_MEM,
376 },
377 [1] = {
378 .start = 46,
379 .flags = IORESOURCE_IRQ,
380 },
381};
382
383static struct platform_device tmu9_device = {
384 .name = "sh_tmu",
385 .id = 9,
386 .dev = {
387 .platform_data = &tmu9_platform_data,
388 },
389 .resource = tmu9_resources,
390 .num_resources = ARRAY_SIZE(tmu9_resources),
391};
392
393static struct sh_timer_config tmu10_platform_data = {
c3d480de
PM		 394 .channel_offset = 0x10,
395 .timer_bit = 1,
c3d480de
PM		 396};
397
398static struct resource tmu10_resources[] = {
399 [0] = {
c3d480de
PM		 400 .start = 0xffde0014,
401 .end = 0xffde001f,
402 .flags = IORESOURCE_MEM,
403 },
404 [1] = {
405 .start = 46,
406 .flags = IORESOURCE_IRQ,
407 },
408};
409
410static struct platform_device tmu10_device = {
411 .name = "sh_tmu",
412 .id = 10,
413 .dev = {
414 .platform_data = &tmu10_platform_data,
415 },
416 .resource = tmu10_resources,
417 .num_resources = ARRAY_SIZE(tmu10_resources),
418};
419
420static struct sh_timer_config tmu11_platform_data = {
c3d480de
PM		 421 .channel_offset = 0x1c,
422 .timer_bit = 2,
c3d480de
PM		 423};
424
425static struct resource tmu11_resources[] = {
426 [0] = {
c3d480de
PM		 427 .start = 0xffde0020,
428 .end = 0xffde002b,
429 .flags = IORESOURCE_MEM,
430 },
431 [1] = {
432 .start = 46,
433 .flags = IORESOURCE_IRQ,
434 },
435};
436
437static struct platform_device tmu11_device = {
438 .name = "sh_tmu",
439 .id = 11,
440 .dev = {
441 .platform_data = &tmu11_platform_data,
442 },
443 .resource = tmu11_resources,
444 .num_resources = ARRAY_SIZE(tmu11_resources),
445};
446
050d4cc7
PM		 447static struct sh_dmae_channel dmac0_channels[] = {
448 {
449 .offset = 0,
450 .dmars = 0,
451 .dmars_bit = 0,
452 }, {
453 .offset = 0x10,
454 .dmars = 0,
455 .dmars_bit = 8,
456 }, {
457 .offset = 0x20,
458 .dmars = 4,
459 .dmars_bit = 0,
460 }, {
461 .offset = 0x30,
462 .dmars = 4,
463 .dmars_bit = 8,
464 }, {
465 .offset = 0x50,
466 .dmars = 8,
467 .dmars_bit = 0,
468 }, {
469 .offset = 0x60,
470 .dmars = 8,
471 .dmars_bit = 8,
472 }
473};
474
475static unsigned int ts_shift[] = TS_SHIFT;
476
477static struct sh_dmae_pdata dma0_platform_data = {
478 .channel = dmac0_channels,
479 .channel_num = ARRAY_SIZE(dmac0_channels),
480 .ts_low_shift = CHCR_TS_LOW_SHIFT,
481 .ts_low_mask = CHCR_TS_LOW_MASK,
482 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
483 .ts_high_mask = CHCR_TS_HIGH_MASK,
484 .ts_shift = ts_shift,
485 .ts_shift_num = ARRAY_SIZE(ts_shift),
486 .dmaor_init = DMAOR_INIT,
487};
488
489/* Resource order important! */
490static struct resource dmac0_resources[] = {
491 {
492 /* Channel registers and DMAOR */
493 .start = 0xfe008020,
494 .end = 0xfe00808f,
495 .flags = IORESOURCE_MEM,
496 }, {
497 /* DMARSx */
498 .start = 0xfe009000,
499 .end = 0xfe00900b,
500 .flags = IORESOURCE_MEM,
501 }, {
502 /* DMA error IRQ */
503 .start = evt2irq(0x5c0),
504 .end = evt2irq(0x5c0),
505 .flags = IORESOURCE_IRQ,
506 }, {
507 /* IRQ for channels 0-5 */
508 .start = evt2irq(0x500),
509 .end = evt2irq(0x5a0),
510 .flags = IORESOURCE_IRQ,
511 },
512};
513
514static struct platform_device dma0_device = {
515 .name = "sh-dma-engine",
516 .id = 0,
517 .resource = dmac0_resources,
518 .num_resources = ARRAY_SIZE(dmac0_resources),
519 .dev = {
520 .platform_data = &dma0_platform_data,
521 },
522};
523
4c3f450b
KM		 524static struct resource usb_ohci_resources[] = {
525 [0] = {
526 .start = 0xffe70400,
527 .end = 0xffe704ff,
528 .flags = IORESOURCE_MEM,
529 },
530 [1] = {
531 .start = 77,
532 .end = 77,
533 .flags = IORESOURCE_IRQ,
534 },
535};
536
537static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
538static struct platform_device usb_ohci_device = {
539 .name = "sh_ohci",
540 .id = -1,
541 .dev = {
542 .dma_mask = &usb_ohci_dma_mask,
543 .coherent_dma_mask = DMA_BIT_MASK(32),
544 },
545 .num_resources = ARRAY_SIZE(usb_ohci_resources),
546 .resource = usb_ohci_resources,
547};
548
c3d480de 549static struct platform_device *sh7786_early_devices[] __initdata = {
a9571d7b
MD		 550 &scif0_device,
551 &scif1_device,
552 &scif2_device,
553 &scif3_device,
554 &scif4_device,
555 &scif5_device,
c3d480de
PM		 556 &tmu0_device,
557 &tmu1_device,
558 &tmu2_device,
559 &tmu3_device,
560 &tmu4_device,
561 &tmu5_device,
562 &tmu6_device,
563 &tmu7_device,
564 &tmu8_device,
565 &tmu9_device,
566 &tmu10_device,
567 &tmu11_device,
568};
569
55ba99eb 570static struct platform_device *sh7786_devices[] __initdata = {
050d4cc7 571 &dma0_device,
4c3f450b 572 &usb_ohci_device,
55ba99eb
KM		 573};
574
4c3f450b
KM		 575
576/*
577 * Please call this function if your platform board
578 * use external clock for USB
579 * */
580#define USBCTL0 0xffe70858
581#define CLOCK_MODE_MASK 0xffffff7f
582#define EXT_CLOCK_MODE 0x00000080
583void __init sh7786_usb_use_exclock(void)
584{
585 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
586 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
587}
588
589#define USBINITREG1 0xffe70094
590#define USBINITREG2 0xffe7009c
591#define USBINITVAL1 0x00ff0040
592#define USBINITVAL2 0x00000001
593
594#define USBPCTL1 0xffe70804
595#define USBST 0xffe70808
596#define PHY_ENB 0x00000001
597#define PLL_ENB 0x00000002
598#define PHY_RST 0x00000004
599#define ACT_PLL_STATUS 0xc0000000
600static void __init sh7786_usb_setup(void)
601{
602 int i = 1000000;
603
604 /*
605 * USB initial settings
606 *
607 * The following settings are necessary
608 * for using the USB modules.
609 *
610 * see "USB Inital Settings" for detail
611 */
612 __raw_writel(USBINITVAL1, USBINITREG1);
613 __raw_writel(USBINITVAL2, USBINITREG2);
614
615 /*
616 * Set the PHY and PLL enable bit
617 */
618 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
0ee50254
KM		 619 while (i--) {
620 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
621 /* Set the PHY RST bit */
622 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
623 printk(KERN_INFO "sh7786 usb setup done\n");
624 break;
625 }
4c3f450b 626 cpu_relax();
4c3f450b
KM		 627 }
628}
629
55ba99eb
KM		 630static int __init sh7786_devices_setup(void)
631{
c3d480de
PM		 632 int ret;
633
4c3f450b 634 sh7786_usb_setup();
c3d480de
PM		 635
636 ret = platform_add_devices(sh7786_early_devices,
637 ARRAY_SIZE(sh7786_early_devices));
638 if (unlikely(ret != 0))
639 return ret;
640
55ba99eb
KM		 641 return platform_add_devices(sh7786_devices,
642 ARRAY_SIZE(sh7786_devices));
643}
ba9a6337 644arch_initcall(sh7786_devices_setup);
55ba99eb 645
c3d480de
PM		 646void __init plat_early_device_setup(void)
647{
648 early_platform_add_devices(sh7786_early_devices,
649 ARRAY_SIZE(sh7786_early_devices));
650}
651
55ba99eb
KM		 652enum {
653 UNUSED = 0,
654
655 /* interrupt sources */
656
657 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
658 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
659 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
660 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
661
662 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
663 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
664 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
665 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
666
667 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
668 WDT,
669 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
670 TMU1_0, TMU1_1, TMU1_2,
671 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
672 HUDI1, HUDI0,
673 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
674 HPB_0, HPB_1, HPB_2,
675 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
676 SCIF1,
677 TMU2, TMU3,
678 SCIF2, SCIF3, SCIF4, SCIF5,
679 Eth_0, Eth_1,
680 PCIeC0_0, PCIeC0_1, PCIeC0_2,
681 PCIeC1_0, PCIeC1_1, PCIeC1_2,
682 USB,
683 I2C0, I2C1,
684 DU,
685 SSI0, SSI1, SSI2, SSI3,
686 PCIeC2_0, PCIeC2_1, PCIeC2_2,
687 HAC0, HAC1,
688 FLCTL,
689 HSPI,
690 GPIO0, GPIO1,
691 Thermal,
2eb2a436
PM		 692 INTICI0, INTICI1, INTICI2, INTICI3,
693 INTICI4, INTICI5, INTICI6, INTICI7,
55ba99eb
KM		 694};
695
696static struct intc_vect vectors[] __initdata = {
697 INTC_VECT(WDT, 0x3e0),
698 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
699 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
700 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
701 INTC_VECT(TMU1_2, 0x4c0),
702 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
703 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
704 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
705 INTC_VECT(DMAC0_6, 0x5c0),
706 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
707 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
708 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
709 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
710 INTC_VECT(HPB_2, 0x6e0),
711 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
712 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
713 INTC_VECT(SCIF1, 0x780),
714 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
715 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
716 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
717 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
718 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
719 INTC_VECT(PCIeC0_2, 0xb20),
720 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
721 INTC_VECT(PCIeC1_2, 0xb80),
722 INTC_VECT(USB, 0xba0),
723 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
724 INTC_VECT(DU, 0xd00),
725 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
726 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
727 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
728 INTC_VECT(PCIeC2_2, 0xde0),
729 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
730 INTC_VECT(FLCTL, 0xe40),
731 INTC_VECT(HSPI, 0xe80),
732 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
733 INTC_VECT(Thermal, 0xee0),
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PM		 734 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
735 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
736 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
737 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
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KM		 738};
739
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KM		 740#define CnINTMSK0 0xfe410030
741#define CnINTMSK1 0xfe410040
742#define CnINTMSKCLR0 0xfe410050
743#define CnINTMSKCLR1 0xfe410060
744#define CnINT2MSKR0 0xfe410a20
745#define CnINT2MSKR1 0xfe410a24
746#define CnINT2MSKR2 0xfe410a28
747#define CnINT2MSKR3 0xfe410a2c
748#define CnINT2MSKCR0 0xfe410a30
749#define CnINT2MSKCR1 0xfe410a34
750#define CnINT2MSKCR2 0xfe410a38
751#define CnINT2MSKCR3 0xfe410a3c
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KM		 752#define INTMSK2 0xfe410068
753#define INTMSKCLR2 0xfe41006c
754
755static struct intc_mask_reg mask_registers[] __initdata = {
756 { CnINTMSK0, CnINTMSKCLR0, 32,
757 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
758 { INTMSK2, INTMSKCLR2, 32,
759 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
760 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
761 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
762 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
763 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
764 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
765 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
766 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
767 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
768 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
770 { CnINT2MSKR1, CnINT2MSKCR1, 32,
771 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
772 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
773 HUDI1, HUDI0,
774 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
775 HPB_0, HPB_1, HPB_2,
776 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
777 SCIF1,
778 TMU2, TMU3, 0, } },
779 { CnINT2MSKR2, CnINT2MSKCR2, 32,
780 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
781 Eth_0, Eth_1,
782 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
783 PCIeC0_0, PCIeC0_1, PCIeC0_2,
784 PCIeC1_0, PCIeC1_1, PCIeC1_2,
785 USB, 0, 0 } },
786 { CnINT2MSKR3, CnINT2MSKCR3, 32,
787 { 0, 0, 0, 0, 0, 0,
788 I2C0, I2C1,
789 DU, SSI0, SSI1, SSI2, SSI3,
790 PCIeC2_0, PCIeC2_1, PCIeC2_2,
791 HAC0, HAC1,
792 FLCTL, 0,
793 HSPI, GPIO0, GPIO1, Thermal,
794 0, 0, 0, 0, 0, 0, 0, 0 } },
795};
796
797static struct intc_prio_reg prio_registers[] __initdata = {
798 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
799 IRQ4, IRQ5, IRQ6, IRQ7 } },
800 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
801 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
802 TMU0_2, TMU0_3 } },
803 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
804 TMU1_2, 0 } },
805 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
806 DMAC0_2, DMAC0_3 } },
807 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
808 DMAC0_6, HUDI1 } },
809 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
810 DMAC1_1, DMAC1_2 } },
811 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
812 HPB_1, HPB_2 } },
813 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
814 SCIF0_2, SCIF0_3 } },
815 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
816 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
817 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
818 Eth_0, Eth_1 } },
819 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
820 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
821 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
822 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
823 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
824 PCIeC1_0, PCIeC1_1 } },
825 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
826 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
827 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
828 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
829 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
830 PCIeC2_1, PCIeC2_2 } },
831 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
832 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
833 GPIO1, Thermal } },
834 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
835 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
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PM		 836 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
837 { INTICI7, INTICI6, INTICI5, INTICI4,
838 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
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KM		 839};
840
841static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
842 mask_registers, prio_registers, NULL);
843
844/* Support for external interrupt pins in IRQ mode */
845
846static struct intc_vect vectors_irq0123[] __initdata = {
847 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
848 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
849};
850
851static struct intc_vect vectors_irq4567[] __initdata = {
852 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
853 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
854};
855
856static struct intc_sense_reg sense_registers[] __initdata = {
857 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
858 IRQ4, IRQ5, IRQ6, IRQ7 } },
859};
860
861static struct intc_mask_reg ack_registers[] __initdata = {
862 { 0xfe410024, 0, 32, /* INTREQ */
863 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
864};
865
866static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
867 vectors_irq0123, NULL, mask_registers,
868 prio_registers, sense_registers, ack_registers);
869
870static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
871 vectors_irq4567, NULL, mask_registers,
872 prio_registers, sense_registers, ack_registers);
873
874/* External interrupt pins in IRL mode */
875
876static struct intc_vect vectors_irl0123[] __initdata = {
877 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
878 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
879 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
880 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
881 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
882 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
883 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
884 INTC_VECT(IRL0_HHHL, 0x3c0),
885};
886
887static struct intc_vect vectors_irl4567[] __initdata = {
888 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
889 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
890 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
891 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
892 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
893 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
894 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
895 INTC_VECT(IRL4_HHHL, 0xac0),
896};
897
898static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
899 NULL, mask_registers, NULL, NULL);
900
901static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
902 NULL, mask_registers, NULL, NULL);
903
904#define INTC_ICR0 0xfe410000
905#define INTC_INTMSK0 CnINTMSK0
906#define INTC_INTMSK1 CnINTMSK1
907#define INTC_INTMSK2 INTMSK2
908#define INTC_INTMSKCLR1 CnINTMSKCLR1
909#define INTC_INTMSKCLR2 INTMSKCLR2
910
911void __init plat_irq_setup(void)
912{
913 /* disable IRQ3-0 + IRQ7-4 */
9d56dd3b 914 __raw_writel(0xff000000, INTC_INTMSK0);
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KM		 915
916 /* disable IRL3-0 + IRL7-4 */
9d56dd3b
PM		 917 __raw_writel(0xc0000000, INTC_INTMSK1);
918 __raw_writel(0xfffefffe, INTC_INTMSK2);
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KM		 919
920 /* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b 921 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
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KM		 922
923 register_intc_controller(&intc_desc);
924}
925
926void __init plat_irq_setup_pins(int mode)
927{
928 switch (mode) {
929 case IRQ_MODE_IRQ7654:
930 /* select IRQ mode for IRL7-4 */
9d56dd3b 931 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
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KM		 932 register_intc_controller(&intc_desc_irq4567);
933 break;
934 case IRQ_MODE_IRQ3210:
935 /* select IRQ mode for IRL3-0 */
9d56dd3b 936 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
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KM		 937 register_intc_controller(&intc_desc_irq0123);
938 break;
939 case IRQ_MODE_IRL7654:
940 /* enable IRL7-4 but don't provide any masking */
9d56dd3b
PM		 941 __raw_writel(0x40000000, INTC_INTMSKCLR1);
942 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
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KM		 943 break;
944 case IRQ_MODE_IRL3210:
945 /* enable IRL0-3 but don't provide any masking */
9d56dd3b
PM		 946 __raw_writel(0x80000000, INTC_INTMSKCLR1);
947 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
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KM		 948 break;
949 case IRQ_MODE_IRL7654_MASK:
950 /* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b 951 __raw_writel(0x40000000, INTC_INTMSKCLR1);
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KM		 952 register_intc_controller(&intc_desc_irl4567);
953 break;
954 case IRQ_MODE_IRL3210_MASK:
955 /* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b 956 __raw_writel(0x80000000, INTC_INTMSKCLR1);
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KM		 957 register_intc_controller(&intc_desc_irl0123);
958 break;
959 default:
960 BUG();
961 }
962}
963
964void __init plat_mem_setup(void)
965{
966}
Linux kernel - Deliverables
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