projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d1839136 PM |
1 | /* |
| 2 | * arch/sh/kernel/cpu/sh5/probe.c | |
| 3 | * | |
| 4 | * CPU Subtype Probing for SH-5. | |
| 5 | * | |
| 6 | * Copyright (C) 2000, 2001 Paolo Alberelli | |
| 7 | * Copyright (C) 2003 - 2007 Paul Mundt | |
| 8 | * | |
| 9 | * This file is subject to the terms and conditions of the GNU General Public | |
| 10 | * License. See the file "COPYING" in the main directory of this archive | |
| 11 | * for more details. | |
| 12 | */ | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/io.h> | |
| 15 | #include <linux/string.h> | |
| 16 | #include <asm/processor.h> | |
| 17 | #include <asm/cache.h> | |
| 2a6b8148 | 18 | #include <asm/tlb.h> |
| d1839136 | 19 | |
| 4603f53a | 20 | void cpu_probe(void) |
| d1839136 PM |
21 | { |
| 22 | unsigned long long cir; | |
| 23 | ||
| 38350e0a PM |
24 | /* |
| 25 | * Do peeks in real mode to avoid having to set up a mapping for | |
| 26 | * the WPC registers. On SH5-101 cut2, such a mapping would be | |
| 27 | * exposed to an address translation erratum which would make it | |
| 28 | * hard to set up correctly. | |
| 29 | */ | |
| d1839136 | 30 | cir = peek_real_address_q(0x0d000008); |
| 38350e0a | 31 | if ((cir & 0xffff) == 0x5103) |
| d1839136 | 32 | boot_cpu_data.type = CPU_SH5_103; |
| 38350e0a | 33 | else if (((cir >> 32) & 0xffff) == 0x51e2) |
| d1839136 PM |
34 | /* CPU.VCR aliased at CIR address on SH5-101 */ |
| 35 | boot_cpu_data.type = CPU_SH5_101; | |
| d1839136 | 36 | |
| e82da214 PM |
37 | boot_cpu_data.family = CPU_FAMILY_SH5; |
| 38 | ||
| d1839136 PM |
39 | /* |
| 40 | * First, setup some sane values for the I-cache. | |
| 41 | */ | |
| 42 | boot_cpu_data.icache.ways = 4; | |
| 43 | boot_cpu_data.icache.sets = 256; | |
| 44 | boot_cpu_data.icache.linesz = L1_CACHE_BYTES; | |
| 38350e0a PM |
45 | boot_cpu_data.icache.way_incr = (1 << 13); |
| 46 | boot_cpu_data.icache.entry_shift = 5; | |
| 47 | boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * | |
| 48 | boot_cpu_data.icache.linesz; | |
| 49 | boot_cpu_data.icache.entry_mask = 0x1fe0; | |
| 50 | boot_cpu_data.icache.flags = 0; | |
| d1839136 | 51 | |
| d1839136 | 52 | /* |
| 38350e0a PM |
53 | * Next, setup some sane values for the D-cache. |
| 54 | * | |
| 55 | * On the SH5, these are pretty consistent with the I-cache settings, | |
| 56 | * so we just copy over the existing definitions.. these can be fixed | |
| 57 | * up later, especially if we add runtime CPU probing. | |
| 58 | * | |
| 59 | * Though in the meantime it saves us from having to duplicate all of | |
| 60 | * the above definitions.. | |
| d1839136 | 61 | */ |
| 38350e0a | 62 | boot_cpu_data.dcache = boot_cpu_data.icache; |
| d1839136 PM |
63 | |
| 64 | /* | |
| 38350e0a | 65 | * Setup any cache-related flags here |
| d1839136 | 66 | */ |
| 38350e0a PM |
67 | #if defined(CONFIG_CACHE_WRITETHROUGH) |
| 68 | set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags)); | |
| 69 | #elif defined(CONFIG_CACHE_WRITEBACK) | |
| 70 | set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); | |
| d1839136 PM |
71 | #endif |
| 72 | ||
| 2a6b8148 PM |
73 | /* Setup some I/D TLB defaults */ |
| 74 | sh64_tlb_init(); | |
| d1839136 | 75 | } |