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ac44e669 PM |
1 | /* |
2 | * Performance event support framework for SuperH hardware counters. | |
3 | * | |
4 | * Copyright (C) 2009 Paul Mundt | |
5 | * | |
6 | * Heavily based on the x86 and PowerPC implementations. | |
7 | * | |
8 | * x86: | |
9 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
10 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
11 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
12 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
13 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
14 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
15 | * | |
16 | * ppc: | |
17 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
18 | * | |
19 | * This file is subject to the terms and conditions of the GNU General Public | |
20 | * License. See the file "COPYING" in the main directory of this archive | |
21 | * for more details. | |
22 | */ | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/perf_event.h> | |
28 | #include <asm/processor.h> | |
29 | ||
30 | struct cpu_hw_events { | |
31 | struct perf_event *events[MAX_HWEVENTS]; | |
32 | unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; | |
33 | unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; | |
34 | }; | |
35 | ||
36 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | |
37 | ||
38 | static struct sh_pmu *sh_pmu __read_mostly; | |
39 | ||
40 | /* Number of perf_events counting hardware events */ | |
41 | static atomic_t num_events; | |
42 | /* Used to avoid races in calling reserve/release_pmc_hardware */ | |
43 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
44 | ||
45 | /* | |
46 | * Stub these out for now, do something more profound later. | |
47 | */ | |
48 | int reserve_pmc_hardware(void) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | void release_pmc_hardware(void) | |
54 | { | |
55 | } | |
56 | ||
57 | static inline int sh_pmu_initialized(void) | |
58 | { | |
59 | return !!sh_pmu; | |
60 | } | |
61 | ||
62 | /* | |
63 | * Release the PMU if this is the last perf_event. | |
64 | */ | |
65 | static void hw_perf_event_destroy(struct perf_event *event) | |
66 | { | |
67 | if (!atomic_add_unless(&num_events, -1, 1)) { | |
68 | mutex_lock(&pmc_reserve_mutex); | |
69 | if (atomic_dec_return(&num_events) == 0) | |
70 | release_pmc_hardware(); | |
71 | mutex_unlock(&pmc_reserve_mutex); | |
72 | } | |
73 | } | |
74 | ||
75 | static int hw_perf_cache_event(int config, int *evp) | |
76 | { | |
77 | unsigned long type, op, result; | |
78 | int ev; | |
79 | ||
80 | if (!sh_pmu->cache_events) | |
81 | return -EINVAL; | |
82 | ||
83 | /* unpack config */ | |
84 | type = config & 0xff; | |
85 | op = (config >> 8) & 0xff; | |
86 | result = (config >> 16) & 0xff; | |
87 | ||
88 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
89 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
90 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
91 | return -EINVAL; | |
92 | ||
93 | ev = (*sh_pmu->cache_events)[type][op][result]; | |
94 | if (ev == 0) | |
95 | return -EOPNOTSUPP; | |
96 | if (ev == -1) | |
97 | return -EINVAL; | |
98 | *evp = ev; | |
99 | return 0; | |
100 | } | |
101 | ||
102 | static int __hw_perf_event_init(struct perf_event *event) | |
103 | { | |
104 | struct perf_event_attr *attr = &event->attr; | |
105 | struct hw_perf_event *hwc = &event->hw; | |
8820002c | 106 | int config = -1; |
ac44e669 PM |
107 | int err; |
108 | ||
109 | if (!sh_pmu_initialized()) | |
110 | return -ENODEV; | |
111 | ||
112 | /* | |
113 | * All of the on-chip counters are "limited", in that they have | |
114 | * no interrupts, and are therefore unable to do sampling without | |
115 | * further work and timer assistance. | |
116 | */ | |
117 | if (hwc->sample_period) | |
118 | return -EINVAL; | |
119 | ||
120 | /* | |
121 | * See if we need to reserve the counter. | |
122 | * | |
123 | * If no events are currently in use, then we have to take a | |
124 | * mutex to ensure that we don't race with another task doing | |
125 | * reserve_pmc_hardware or release_pmc_hardware. | |
126 | */ | |
127 | err = 0; | |
128 | if (!atomic_inc_not_zero(&num_events)) { | |
129 | mutex_lock(&pmc_reserve_mutex); | |
130 | if (atomic_read(&num_events) == 0 && | |
131 | reserve_pmc_hardware()) | |
132 | err = -EBUSY; | |
133 | else | |
134 | atomic_inc(&num_events); | |
135 | mutex_unlock(&pmc_reserve_mutex); | |
136 | } | |
137 | ||
138 | if (err) | |
139 | return err; | |
140 | ||
141 | event->destroy = hw_perf_event_destroy; | |
142 | ||
143 | switch (attr->type) { | |
144 | case PERF_TYPE_RAW: | |
145 | config = attr->config & sh_pmu->raw_event_mask; | |
146 | break; | |
147 | case PERF_TYPE_HW_CACHE: | |
148 | err = hw_perf_cache_event(attr->config, &config); | |
149 | if (err) | |
150 | return err; | |
151 | break; | |
152 | case PERF_TYPE_HARDWARE: | |
153 | if (attr->config >= sh_pmu->max_events) | |
154 | return -EINVAL; | |
155 | ||
156 | config = sh_pmu->event_map(attr->config); | |
157 | break; | |
ac44e669 PM |
158 | } |
159 | ||
160 | if (config == -1) | |
161 | return -EINVAL; | |
162 | ||
163 | hwc->config |= config; | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static void sh_perf_event_update(struct perf_event *event, | |
169 | struct hw_perf_event *hwc, int idx) | |
170 | { | |
171 | u64 prev_raw_count, new_raw_count; | |
172 | s64 delta; | |
173 | int shift = 0; | |
174 | ||
175 | /* | |
176 | * Depending on the counter configuration, they may or may not | |
177 | * be chained, in which case the previous counter value can be | |
178 | * updated underneath us if the lower-half overflows. | |
179 | * | |
180 | * Our tactic to handle this is to first atomically read and | |
181 | * exchange a new raw count - then add that new-prev delta | |
182 | * count to the generic counter atomically. | |
183 | * | |
184 | * As there is no interrupt associated with the overflow events, | |
185 | * this is the simplest approach for maintaining consistency. | |
186 | */ | |
187 | again: | |
e7850595 | 188 | prev_raw_count = local64_read(&hwc->prev_count); |
ac44e669 PM |
189 | new_raw_count = sh_pmu->read(idx); |
190 | ||
e7850595 | 191 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ac44e669 PM |
192 | new_raw_count) != prev_raw_count) |
193 | goto again; | |
194 | ||
195 | /* | |
196 | * Now we have the new raw value and have updated the prev | |
197 | * timestamp already. We can now calculate the elapsed delta | |
198 | * (counter-)time and add that to the generic counter. | |
199 | * | |
200 | * Careful, not all hw sign-extends above the physical width | |
201 | * of the count. | |
202 | */ | |
203 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
204 | delta >>= shift; | |
205 | ||
e7850595 | 206 | local64_add(delta, &event->count); |
ac44e669 PM |
207 | } |
208 | ||
a4eaf7f1 | 209 | static void sh_pmu_stop(struct perf_event *event, int flags) |
ac44e669 PM |
210 | { |
211 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
212 | struct hw_perf_event *hwc = &event->hw; | |
213 | int idx = hwc->idx; | |
214 | ||
a4eaf7f1 PZ |
215 | if (!(event->hw.state & PERF_HES_STOPPED)) { |
216 | sh_pmu->disable(hwc, idx); | |
217 | cpuc->events[idx] = NULL; | |
218 | event->hw.state |= PERF_HES_STOPPED; | |
219 | } | |
ac44e669 | 220 | |
a4eaf7f1 PZ |
221 | if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) { |
222 | sh_perf_event_update(event, &event->hw, idx); | |
223 | event->hw.state |= PERF_HES_UPTODATE; | |
224 | } | |
225 | } | |
ac44e669 | 226 | |
a4eaf7f1 PZ |
227 | static void sh_pmu_start(struct perf_event *event, int flags) |
228 | { | |
229 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
230 | struct hw_perf_event *hwc = &event->hw; | |
231 | int idx = hwc->idx; | |
ac44e669 | 232 | |
a4eaf7f1 PZ |
233 | if (WARN_ON_ONCE(idx == -1)) |
234 | return; | |
235 | ||
236 | if (flags & PERF_EF_RELOAD) | |
237 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
238 | ||
239 | cpuc->events[idx] = event; | |
240 | event->hw.state = 0; | |
241 | sh_pmu->enable(hwc, idx); | |
242 | } | |
243 | ||
244 | static void sh_pmu_del(struct perf_event *event, int flags) | |
245 | { | |
246 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
247 | ||
248 | sh_pmu_stop(event, PERF_EF_UPDATE); | |
249 | __clear_bit(event->hw.idx, cpuc->used_mask); | |
ac44e669 PM |
250 | |
251 | perf_event_update_userpage(event); | |
252 | } | |
253 | ||
a4eaf7f1 | 254 | static int sh_pmu_add(struct perf_event *event, int flags) |
ac44e669 PM |
255 | { |
256 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
257 | struct hw_perf_event *hwc = &event->hw; | |
258 | int idx = hwc->idx; | |
24cd7f54 PZ |
259 | int ret = -EAGAIN; |
260 | ||
33696fc0 | 261 | perf_pmu_disable(event->pmu); |
ac44e669 | 262 | |
a4eaf7f1 | 263 | if (__test_and_set_bit(idx, cpuc->used_mask)) { |
ac44e669 PM |
264 | idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); |
265 | if (idx == sh_pmu->num_events) | |
24cd7f54 | 266 | goto out; |
ac44e669 | 267 | |
a4eaf7f1 | 268 | __set_bit(idx, cpuc->used_mask); |
ac44e669 PM |
269 | hwc->idx = idx; |
270 | } | |
271 | ||
272 | sh_pmu->disable(hwc, idx); | |
273 | ||
a4eaf7f1 PZ |
274 | event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
275 | if (flags & PERF_EF_START) | |
276 | sh_pmu_start(event, PERF_EF_RELOAD); | |
ac44e669 PM |
277 | |
278 | perf_event_update_userpage(event); | |
24cd7f54 PZ |
279 | ret = 0; |
280 | out: | |
33696fc0 | 281 | perf_pmu_enable(event->pmu); |
24cd7f54 | 282 | return ret; |
ac44e669 PM |
283 | } |
284 | ||
285 | static void sh_pmu_read(struct perf_event *event) | |
286 | { | |
287 | sh_perf_event_update(event, &event->hw, event->hw.idx); | |
288 | } | |
289 | ||
b0a873eb | 290 | static int sh_pmu_event_init(struct perf_event *event) |
ac44e669 | 291 | { |
b0a873eb PZ |
292 | int err; |
293 | ||
294 | switch (event->attr.type) { | |
295 | case PERF_TYPE_RAW: | |
296 | case PERF_TYPE_HW_CACHE: | |
297 | case PERF_TYPE_HARDWARE: | |
298 | err = __hw_perf_event_init(event); | |
299 | break; | |
300 | ||
301 | default: | |
302 | return -ENOENT; | |
303 | } | |
304 | ||
ac44e669 PM |
305 | if (unlikely(err)) { |
306 | if (event->destroy) | |
307 | event->destroy(event); | |
ac44e669 PM |
308 | } |
309 | ||
b0a873eb | 310 | return err; |
ac44e669 PM |
311 | } |
312 | ||
a4eaf7f1 | 313 | static void sh_pmu_enable(struct pmu *pmu) |
33696fc0 PZ |
314 | { |
315 | if (!sh_pmu_initialized()) | |
316 | return; | |
317 | ||
318 | sh_pmu->enable_all(); | |
319 | } | |
320 | ||
a4eaf7f1 | 321 | static void sh_pmu_disable(struct pmu *pmu) |
33696fc0 PZ |
322 | { |
323 | if (!sh_pmu_initialized()) | |
324 | return; | |
325 | ||
326 | sh_pmu->disable_all(); | |
327 | } | |
328 | ||
b0a873eb | 329 | static struct pmu pmu = { |
a4eaf7f1 PZ |
330 | .pmu_enable = sh_pmu_enable, |
331 | .pmu_disable = sh_pmu_disable, | |
b0a873eb | 332 | .event_init = sh_pmu_event_init, |
a4eaf7f1 PZ |
333 | .add = sh_pmu_add, |
334 | .del = sh_pmu_del, | |
335 | .start = sh_pmu_start, | |
336 | .stop = sh_pmu_stop, | |
b0a873eb PZ |
337 | .read = sh_pmu_read, |
338 | }; | |
339 | ||
3f6da390 | 340 | static void sh_pmu_setup(int cpu) |
b0a873eb | 341 | |
ac44e669 PM |
342 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
343 | ||
344 | memset(cpuhw, 0, sizeof(struct cpu_hw_events)); | |
345 | } | |
346 | ||
3f6da390 PZ |
347 | static int __cpuinit |
348 | sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
349 | { | |
350 | unsigned int cpu = (long)hcpu; | |
351 | ||
352 | switch (action & ~CPU_TASKS_FROZEN) { | |
353 | case CPU_UP_PREPARE: | |
354 | sh_pmu_setup(cpu); | |
355 | break; | |
356 | ||
357 | default: | |
358 | break; | |
359 | } | |
360 | ||
361 | return NOTIFY_OK; | |
362 | } | |
363 | ||
a4eaf7f1 | 364 | int __cpuinit register_sh_pmu(struct sh_pmu *_pmu) |
ac44e669 PM |
365 | { |
366 | if (sh_pmu) | |
367 | return -EBUSY; | |
a4eaf7f1 | 368 | sh_pmu = _pmu; |
ac44e669 | 369 | |
a4eaf7f1 | 370 | pr_info("Performance Events: %s support registered\n", _pmu->name); |
ac44e669 | 371 | |
a4eaf7f1 | 372 | WARN_ON(_pmu->num_events > MAX_HWEVENTS); |
ac44e669 | 373 | |
b0a873eb | 374 | perf_pmu_register(&pmu); |
3f6da390 | 375 | perf_cpu_notifier(sh_pmu_notifier); |
ac44e669 PM |
376 | return 0; |
377 | } |