Commit | Line | Data |
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9d4436a6 YS |
1 | /* |
2 | * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support | |
3 | * | |
4 | * Copyright (C) 2005 Yoshinori Sato | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/seqlock.h> | |
16 | #include <asm/timer.h> | |
17 | #include <asm/rtc.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/irq.h> | |
20 | #include <asm/clock.h> | |
21 | ||
22 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) | |
23 | #define CMT_CMSTR 0xf84a0070 | |
24 | #define CMT_CMCSR_0 0xf84a0072 | |
25 | #define CMT_CMCNT_0 0xf84a0074 | |
26 | #define CMT_CMCOR_0 0xf84a0076 | |
27 | #define CMT_CMCSR_1 0xf84a0078 | |
28 | #define CMT_CMCNT_1 0xf84a007a | |
29 | #define CMT_CMCOR_1 0xf84a007c | |
30 | ||
31 | #define STBCR3 0xf80a0000 | |
32 | #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0) | |
33 | #define CMT_CMCSR_INIT 0x0040 | |
34 | #define CMT_CMCSR_CALIB 0x0000 | |
35 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) | |
36 | #define CMT_CMSTR 0xfffec000 | |
37 | #define CMT_CMCSR_0 0xfffec002 | |
38 | #define CMT_CMCNT_0 0xfffec004 | |
39 | #define CMT_CMCOR_0 0xfffec006 | |
40 | ||
41 | #define STBCR4 0xfffe040c | |
42 | #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0) | |
43 | #define CMT_CMCSR_INIT 0x0040 | |
44 | #define CMT_CMCSR_CALIB 0x0000 | |
45 | #else | |
46 | #error "Unknown CPU SUBTYPE" | |
47 | #endif | |
48 | ||
49 | static DEFINE_SPINLOCK(cmt0_lock); | |
50 | ||
51 | static unsigned long cmt_timer_get_offset(void) | |
52 | { | |
53 | int count; | |
54 | unsigned long flags; | |
55 | ||
56 | static unsigned short count_p = 0xffff; /* for the first call after boot */ | |
57 | static unsigned long jiffies_p = 0; | |
58 | ||
59 | /* | |
60 | * cache volatile jiffies temporarily; we have IRQs turned off. | |
61 | */ | |
62 | unsigned long jiffies_t; | |
63 | ||
64 | spin_lock_irqsave(&cmt0_lock, flags); | |
65 | /* timer count may underflow right here */ | |
66 | count = ctrl_inw(CMT_CMCOR_0); | |
67 | count -= ctrl_inw(CMT_CMCNT_0); | |
68 | ||
69 | jiffies_t = jiffies; | |
70 | ||
71 | /* | |
72 | * avoiding timer inconsistencies (they are rare, but they happen)... | |
73 | * there is one kind of problem that must be avoided here: | |
74 | * 1. the timer counter underflows | |
75 | */ | |
76 | ||
77 | if (jiffies_t == jiffies_p) { | |
78 | if (count > count_p) { | |
79 | /* the nutcase */ | |
80 | if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */ | |
81 | count -= LATCH; | |
82 | } else { | |
83 | printk("%s (): hardware timer problem?\n", | |
84 | __FUNCTION__); | |
85 | } | |
86 | } | |
87 | } else | |
88 | jiffies_p = jiffies_t; | |
89 | ||
90 | count_p = count; | |
91 | spin_unlock_irqrestore(&cmt0_lock, flags); | |
92 | ||
93 | count = ((LATCH-1) - count) * TICK_SIZE; | |
94 | count = (count + LATCH/2) / LATCH; | |
95 | ||
96 | return count; | |
97 | } | |
98 | ||
710ee0cc | 99 | static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id) |
9d4436a6 YS |
100 | { |
101 | unsigned long timer_status; | |
102 | ||
103 | /* Clear CMF bit */ | |
104 | timer_status = ctrl_inw(CMT_CMCSR_0); | |
105 | timer_status &= ~0x80; | |
106 | ctrl_outw(timer_status, CMT_CMCSR_0); | |
107 | ||
108 | /* | |
109 | * Here we are in the timer irq handler. We just have irqs locally | |
110 | * disabled but we don't know if the timer_bh is running on the other | |
111 | * CPU. We need to avoid to SMP race with it. NOTE: we don' t need | |
112 | * the irq version of write_lock because as just said we have irq | |
113 | * locally disabled. -arca | |
114 | */ | |
115 | write_seqlock(&xtime_lock); | |
710ee0cc | 116 | handle_timer_tick(); |
9d4436a6 YS |
117 | write_sequnlock(&xtime_lock); |
118 | ||
119 | return IRQ_HANDLED; | |
120 | } | |
121 | ||
122 | static struct irqaction cmt_irq = { | |
123 | .name = "timer", | |
124 | .handler = cmt_timer_interrupt, | |
710ee0cc | 125 | .flags = IRQF_DISABLED, |
9d4436a6 YS |
126 | .mask = CPU_MASK_NONE, |
127 | }; | |
128 | ||
9d4436a6 YS |
129 | static void cmt_clk_init(struct clk *clk) |
130 | { | |
131 | u8 divisor = CMT_CMCSR_INIT & 0x3; | |
132 | ctrl_inw(CMT_CMCSR_0); | |
133 | ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0); | |
134 | clk->parent = clk_get("module_clk"); | |
135 | clk->rate = clk->parent->rate / (8 << (divisor << 1)); | |
136 | } | |
137 | ||
138 | static void cmt_clk_recalc(struct clk *clk) | |
139 | { | |
140 | u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3; | |
141 | clk->rate = clk->parent->rate / (8 << (divisor << 1)); | |
142 | } | |
143 | ||
144 | static struct clk_ops cmt_clk_ops = { | |
145 | .init = cmt_clk_init, | |
146 | .recalc = cmt_clk_recalc, | |
147 | }; | |
148 | ||
149 | static struct clk cmt0_clk = { | |
150 | .name = "cmt0_clk", | |
151 | .ops = &cmt_clk_ops, | |
152 | }; | |
153 | ||
154 | static int cmt_timer_start(void) | |
155 | { | |
156 | ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | static int cmt_timer_stop(void) | |
161 | { | |
162 | ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static int cmt_timer_init(void) | |
167 | { | |
168 | unsigned long interval; | |
169 | ||
170 | cmt_clock_enable(); | |
171 | ||
172 | setup_irq(TIMER_IRQ, &cmt_irq); | |
173 | ||
174 | cmt0_clk.parent = clk_get("module_clk"); | |
175 | ||
176 | cmt_timer_stop(); | |
177 | ||
178 | interval = cmt0_clk.parent->rate / 8 / HZ; | |
179 | printk(KERN_INFO "Interval = %ld\n", interval); | |
180 | ||
181 | ctrl_outw(interval, CMT_CMCOR_0); | |
182 | ||
183 | clk_register(&cmt0_clk); | |
184 | clk_enable(&cmt0_clk); | |
185 | ||
186 | cmt_timer_start(); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | struct sys_timer_ops cmt_timer_ops = { | |
192 | .init = cmt_timer_init, | |
193 | .start = cmt_timer_start, | |
194 | .stop = cmt_timer_stop, | |
710ee0cc | 195 | #ifndef CONFIG_GENERIC_TIME |
9d4436a6 | 196 | .get_offset = cmt_timer_get_offset, |
710ee0cc | 197 | #endif |
9d4436a6 YS |
198 | }; |
199 | ||
200 | struct sys_timer cmt_timer = { | |
201 | .name = "cmt", | |
202 | .ops = &cmt_timer_ops, | |
203 | }; |