Commit | Line | Data |
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9d4436a6 YS |
1 | /* |
2 | * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support | |
3 | * | |
4 | * Copyright (C) 2005 Yoshinori Sato | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/interrupt.h> | |
9d4436a6 YS |
14 | #include <linux/seqlock.h> |
15 | #include <asm/timer.h> | |
16 | #include <asm/rtc.h> | |
17 | #include <asm/io.h> | |
18 | #include <asm/irq.h> | |
19 | #include <asm/clock.h> | |
20 | ||
21 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) | |
22 | #define CMT_CMSTR 0xf84a0070 | |
23 | #define CMT_CMCSR_0 0xf84a0072 | |
24 | #define CMT_CMCNT_0 0xf84a0074 | |
25 | #define CMT_CMCOR_0 0xf84a0076 | |
26 | #define CMT_CMCSR_1 0xf84a0078 | |
27 | #define CMT_CMCNT_1 0xf84a007a | |
28 | #define CMT_CMCOR_1 0xf84a007c | |
29 | ||
30 | #define STBCR3 0xf80a0000 | |
31 | #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0) | |
32 | #define CMT_CMCSR_INIT 0x0040 | |
33 | #define CMT_CMCSR_CALIB 0x0000 | |
a8f67f4b PM |
34 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
35 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | |
36 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
9d4436a6 YS |
37 | #define CMT_CMSTR 0xfffec000 |
38 | #define CMT_CMCSR_0 0xfffec002 | |
39 | #define CMT_CMCNT_0 0xfffec004 | |
40 | #define CMT_CMCOR_0 0xfffec006 | |
41 | ||
42 | #define STBCR4 0xfffe040c | |
43 | #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0) | |
44 | #define CMT_CMCSR_INIT 0x0040 | |
45 | #define CMT_CMCSR_CALIB 0x0000 | |
46 | #else | |
47 | #error "Unknown CPU SUBTYPE" | |
48 | #endif | |
49 | ||
9d4436a6 YS |
50 | static unsigned long cmt_timer_get_offset(void) |
51 | { | |
52 | int count; | |
9d4436a6 YS |
53 | static unsigned short count_p = 0xffff; /* for the first call after boot */ |
54 | static unsigned long jiffies_p = 0; | |
55 | ||
56 | /* | |
57 | * cache volatile jiffies temporarily; we have IRQs turned off. | |
58 | */ | |
59 | unsigned long jiffies_t; | |
60 | ||
9d4436a6 YS |
61 | /* timer count may underflow right here */ |
62 | count = ctrl_inw(CMT_CMCOR_0); | |
63 | count -= ctrl_inw(CMT_CMCNT_0); | |
64 | ||
65 | jiffies_t = jiffies; | |
66 | ||
67 | /* | |
68 | * avoiding timer inconsistencies (they are rare, but they happen)... | |
69 | * there is one kind of problem that must be avoided here: | |
70 | * 1. the timer counter underflows | |
71 | */ | |
72 | ||
73 | if (jiffies_t == jiffies_p) { | |
74 | if (count > count_p) { | |
75 | /* the nutcase */ | |
76 | if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */ | |
77 | count -= LATCH; | |
78 | } else { | |
79 | printk("%s (): hardware timer problem?\n", | |
80 | __FUNCTION__); | |
81 | } | |
82 | } | |
83 | } else | |
84 | jiffies_p = jiffies_t; | |
85 | ||
86 | count_p = count; | |
9d4436a6 YS |
87 | |
88 | count = ((LATCH-1) - count) * TICK_SIZE; | |
89 | count = (count + LATCH/2) / LATCH; | |
90 | ||
91 | return count; | |
92 | } | |
93 | ||
710ee0cc | 94 | static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id) |
9d4436a6 YS |
95 | { |
96 | unsigned long timer_status; | |
97 | ||
98 | /* Clear CMF bit */ | |
99 | timer_status = ctrl_inw(CMT_CMCSR_0); | |
100 | timer_status &= ~0x80; | |
101 | ctrl_outw(timer_status, CMT_CMCSR_0); | |
102 | ||
103 | /* | |
104 | * Here we are in the timer irq handler. We just have irqs locally | |
105 | * disabled but we don't know if the timer_bh is running on the other | |
106 | * CPU. We need to avoid to SMP race with it. NOTE: we don' t need | |
107 | * the irq version of write_lock because as just said we have irq | |
108 | * locally disabled. -arca | |
109 | */ | |
110 | write_seqlock(&xtime_lock); | |
710ee0cc | 111 | handle_timer_tick(); |
9d4436a6 YS |
112 | write_sequnlock(&xtime_lock); |
113 | ||
114 | return IRQ_HANDLED; | |
115 | } | |
116 | ||
117 | static struct irqaction cmt_irq = { | |
118 | .name = "timer", | |
119 | .handler = cmt_timer_interrupt, | |
e9485bae | 120 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
9d4436a6 YS |
121 | .mask = CPU_MASK_NONE, |
122 | }; | |
123 | ||
9d4436a6 YS |
124 | static void cmt_clk_init(struct clk *clk) |
125 | { | |
126 | u8 divisor = CMT_CMCSR_INIT & 0x3; | |
127 | ctrl_inw(CMT_CMCSR_0); | |
128 | ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0); | |
1d118562 | 129 | clk->parent = clk_get(NULL, "module_clk"); |
9d4436a6 YS |
130 | clk->rate = clk->parent->rate / (8 << (divisor << 1)); |
131 | } | |
132 | ||
133 | static void cmt_clk_recalc(struct clk *clk) | |
134 | { | |
135 | u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3; | |
136 | clk->rate = clk->parent->rate / (8 << (divisor << 1)); | |
137 | } | |
138 | ||
139 | static struct clk_ops cmt_clk_ops = { | |
140 | .init = cmt_clk_init, | |
141 | .recalc = cmt_clk_recalc, | |
142 | }; | |
143 | ||
144 | static struct clk cmt0_clk = { | |
145 | .name = "cmt0_clk", | |
146 | .ops = &cmt_clk_ops, | |
147 | }; | |
148 | ||
149 | static int cmt_timer_start(void) | |
150 | { | |
151 | ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | static int cmt_timer_stop(void) | |
156 | { | |
157 | ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR); | |
158 | return 0; | |
159 | } | |
160 | ||
161 | static int cmt_timer_init(void) | |
162 | { | |
163 | unsigned long interval; | |
164 | ||
165 | cmt_clock_enable(); | |
166 | ||
417528a2 | 167 | setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq); |
9d4436a6 | 168 | |
1d118562 | 169 | cmt0_clk.parent = clk_get(NULL, "module_clk"); |
9d4436a6 YS |
170 | |
171 | cmt_timer_stop(); | |
172 | ||
173 | interval = cmt0_clk.parent->rate / 8 / HZ; | |
174 | printk(KERN_INFO "Interval = %ld\n", interval); | |
175 | ||
176 | ctrl_outw(interval, CMT_CMCOR_0); | |
177 | ||
178 | clk_register(&cmt0_clk); | |
179 | clk_enable(&cmt0_clk); | |
180 | ||
181 | cmt_timer_start(); | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
186 | struct sys_timer_ops cmt_timer_ops = { | |
187 | .init = cmt_timer_init, | |
188 | .start = cmt_timer_start, | |
189 | .stop = cmt_timer_stop, | |
710ee0cc | 190 | #ifndef CONFIG_GENERIC_TIME |
9d4436a6 | 191 | .get_offset = cmt_timer_get_offset, |
710ee0cc | 192 | #endif |
9d4436a6 YS |
193 | }; |
194 | ||
195 | struct sys_timer cmt_timer = { | |
196 | .name = "cmt", | |
197 | .ops = &cmt_timer_ops, | |
198 | }; |