[deliverable/linux.git] / arch / sh / kernel / timers / timer-tmu.c

/*
 * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
 *
 *  Copyright (C) 2005 - 2007  Paul Mundt
 *
 * TMU handling code hacked out of arch/sh/kernel/time.c
 *
 *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
 *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
 *  Copyright (C) 2002, 2003, 2004  Paul Mundt
 *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/seqlock.h>
#include <linux/clockchips.h>
#include <asm/timer.h>
#include <asm/rtc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/clock.h>

#define TMU_TOCR_INIT	0x00
#define TMU_TCR_INIT	0x0020

#define TMU0		(0)
#define TMU1		(1)

static inline void _tmu_start(int tmu_num)
{
	ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
}

static inline void _tmu_set_irq(int tmu_num, int enabled)
{
	register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
	ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
}

static inline void _tmu_stop(int tmu_num)
{
	ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
}

static inline void _tmu_clear_status(int tmu_num)
{
	register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
	/* Clear UNF bit */
	ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
}

static inline unsigned long _tmu_read(int tmu_num)
{
        return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
}

static int tmu_timer_start(void)
{
	_tmu_start(TMU0);
	_tmu_start(TMU1);
	_tmu_set_irq(TMU0,1);
	return 0;
}

static int tmu_timer_stop(void)
{
	_tmu_stop(TMU0);
	_tmu_stop(TMU1);
	_tmu_clear_status(TMU0);
	return 0;
}

/*
 * also when the module_clk is scaled the TMU1
 * will show the same frequency
 */
static int tmus_are_scaled;

static cycle_t tmu_timer_read(struct clocksource *cs)
{
	return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
}


static unsigned long tmu_latest_interval[3];
static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
{
	unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
	unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;

	_tmu_stop(tmu_num);

	ctrl_outl(interval, tmu_tcnt);
	tmu_latest_interval[tmu_num] = interval;

	/*
	 * TCNT reloads from TCOR on underflow, clear it if we don't
	 * intend to auto-reload
	 */
	ctrl_outl( reload ? interval : 0 , tmu_tcor);

	_tmu_start(tmu_num);
}

static int tmu_set_next_event(unsigned long cycles,
			      struct clock_event_device *evt)
{
	tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
	_tmu_set_irq(TMU0,1);
	return 0;
}

static void tmu_set_mode(enum clock_event_mode mode,
			 struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		ctrl_outl(0, TMU0_TCOR);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device tmu0_clockevent = {
	.name		= "tmu0",
	.shift		= 32,
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= tmu_set_mode,
	.set_next_event	= tmu_set_next_event,
};

static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
{
	struct clock_event_device *evt = &tmu0_clockevent;
	_tmu_clear_status(TMU0);
	_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);

	switch (tmu0_clockevent.mode) {
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_PERIODIC:
		evt->event_handler(evt);
		break;
	default:
		break;
	}

	return IRQ_HANDLED;
}

static struct irqaction tmu0_irq = {
	.name		= "periodic/oneshot timer",
	.handler	= tmu_timer_interrupt,
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
};

static void __init tmu_clk_init(struct clk *clk)
{
	u8 divisor  = TMU_TCR_INIT & 0x7;
	int tmu_num = clk->name[3]-'0';
	ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
	clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
}

static void tmu_clk_recalc(struct clk *clk)
{
	int tmu_num = clk->name[3]-'0';
	unsigned long prev_rate = clk_get_rate(clk);
	unsigned long flags;
	u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
	clk->rate  = clk_get_rate(clk->parent) / (4 << (divisor << 1));

	if(prev_rate==clk_get_rate(clk))
		return;

	if(tmu_num)
		return; /* No more work on TMU1 */

	local_irq_save(flags);
	tmus_are_scaled = (prev_rate > clk->rate);

	_tmu_stop(TMU0);

	tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
				tmu0_clockevent.shift);
	tmu0_clockevent.max_delta_ns =
			clockevent_delta2ns(-1, &tmu0_clockevent);
	tmu0_clockevent.min_delta_ns =
			clockevent_delta2ns(1, &tmu0_clockevent);

	if (tmus_are_scaled)
		tmu_latest_interval[TMU0] >>= 1;
	else
		tmu_latest_interval[TMU0] <<= 1;

	tmu_timer_set_interval(TMU0,
		tmu_latest_interval[TMU0],
		tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);

	_tmu_start(TMU0);

	local_irq_restore(flags);
}

static struct clk_ops tmu_clk_ops = {
	.init		= tmu_clk_init,
	.recalc		= tmu_clk_recalc,
};

static struct clk tmu0_clk = {
	.name		= "tmu0_clk",
	.ops		= &tmu_clk_ops,
};

static struct clk tmu1_clk = {
	.name		= "tmu1_clk",
	.ops		= &tmu_clk_ops,
};

static int tmu_timer_init(void)
{
	unsigned long interval;
	unsigned long frequency;

	setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);

	tmu0_clk.parent = clk_get(NULL, "module_clk");
	tmu1_clk.parent = clk_get(NULL, "module_clk");

	tmu_timer_stop();

#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
    !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
    !defined(CONFIG_CPU_SUBTYPE_SHX3)
	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif

	clk_register(&tmu0_clk);
	clk_register(&tmu1_clk);
	clk_enable(&tmu0_clk);
	clk_enable(&tmu1_clk);

	frequency = clk_get_rate(&tmu0_clk);
	interval = (frequency + HZ / 2) / HZ;

	tmu_timer_set_interval(TMU0,interval, 1);
	tmu_timer_set_interval(TMU1,~0,1);

	_tmu_start(TMU1);

	clocksource_sh.rating = 200;
	clocksource_sh.mask = CLOCKSOURCE_MASK(32);
	clocksource_sh.read = tmu_timer_read;
	clocksource_sh.shift = 10;
	clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
						  clocksource_sh.shift);
	clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	clocksource_register(&clocksource_sh);

	tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
				      tmu0_clockevent.shift);
	tmu0_clockevent.max_delta_ns =
			clockevent_delta2ns(-1, &tmu0_clockevent);
	tmu0_clockevent.min_delta_ns =
			clockevent_delta2ns(1, &tmu0_clockevent);

	tmu0_clockevent.cpumask = cpumask_of(0);
	tmu0_clockevent.rating = 100;

	clockevents_register_device(&tmu0_clockevent);

	return 0;
}

static struct sys_timer_ops tmu_timer_ops = {
	.init		= tmu_timer_init,
	.start		= tmu_timer_start,
	.stop		= tmu_timer_stop,
};

struct sys_timer tmu_timer = {
	.name	= "tmu",
	.ops	= &tmu_timer_ops,
};
Commit	Line	Data
aa01666d PM	1	/*
	2	* arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
	3	*
57be2b48	4	* Copyright (C) 2005 - 2007 Paul Mundt
aa01666d PM	5	*
	6	* TMU handling code hacked out of arch/sh/kernel/time.c
	7	*
	8	* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
	9	* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
	10	* Copyright (C) 2002, 2003, 2004 Paul Mundt
	11	* Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
	12	*
	13	* This file is subject to the terms and conditions of the GNU General Public
	14	* License. See the file "COPYING" in the main directory of this archive
	15	* for more details.
	16	*/
	17	#include <linux/init.h>
	18	#include <linux/kernel.h>
	19	#include <linux/interrupt.h>
aa01666d	20	#include <linux/seqlock.h>
57be2b48	21	#include <linux/clockchips.h>
aa01666d PM	22	#include <asm/timer.h>
	23	#include <asm/rtc.h>
	24	#include <asm/io.h>
	25	#include <asm/irq.h>
	26	#include <asm/clock.h>
	27
	28	#define TMU_TOCR_INIT 0x00
57be2b48	29	#define TMU_TCR_INIT 0x0020
aa01666d	30
61c66387 FV	31	#define TMU0 (0)
	32	#define TMU1 (1)
	33
	34	static inline void _tmu_start(int tmu_num)
57be2b48	35	{
61c66387	36	ctrl_outb(ctrl_inb(TMU_012_TSTR) \| (0x1<<tmu_num), TMU_012_TSTR);
57be2b48	37	}
aa01666d	38
61c66387	39	static inline void _tmu_set_irq(int tmu_num, int enabled)
aa01666d	40	{
61c66387 FV	41	register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
	42	ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) \| (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
	43	}
aa01666d	44
61c66387 FV	45	static inline void _tmu_stop(int tmu_num)
	46	{
	47	ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
	48	}
	49
	50	static inline void _tmu_clear_status(int tmu_num)
	51	{
	52	register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
	53	/* Clear UNF bit */
	54	ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
	55	}
aa01666d	56
61c66387 FV	57	static inline unsigned long _tmu_read(int tmu_num)
	58	{
	59	return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
	60	}
	61
	62	static int tmu_timer_start(void)
	63	{
	64	_tmu_start(TMU0);
	65	_tmu_start(TMU1);
	66	_tmu_set_irq(TMU0,1);
	67	return 0;
57be2b48	68	}
aa01666d	69
57be2b48 PM	70	static int tmu_timer_stop(void)
57be2b48 PM	71	{
61c66387 FV	72	_tmu_stop(TMU0);
	73	_tmu_stop(TMU1);
	74	_tmu_clear_status(TMU0);
57be2b48 PM	75	return 0;
57be2b48 PM	76	}
aa01666d	77
61c66387 FV	78	/*
	79	* also when the module_clk is scaled the TMU1
	80	* will show the same frequency
	81	*/
	82	static int tmus_are_scaled;
	83
8e19608e	84	static cycle_t tmu_timer_read(struct clocksource *cs)
57be2b48	85	{
61c66387 FV	86	return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
	87	}
	88
	89
	90	static unsigned long tmu_latest_interval[3];
	91	static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
	92	{
	93	unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
	94	unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
	95
	96	_tmu_stop(tmu_num);
	97
	98	ctrl_outl(interval, tmu_tcnt);
	99	tmu_latest_interval[tmu_num] = interval;
	100
	101	/*
	102	* TCNT reloads from TCOR on underflow, clear it if we don't
	103	* intend to auto-reload
	104	*/
	105	ctrl_outl( reload ? interval : 0 , tmu_tcor);
	106
	107	_tmu_start(tmu_num);
57be2b48 PM	108	}
	109
	110	static int tmu_set_next_event(unsigned long cycles,
	111	struct clock_event_device *evt)
	112	{
61c66387 FV	113	tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
61c66387 FV	114	_tmu_set_irq(TMU0,1);
57be2b48 PM	115	return 0;
57be2b48 PM	116	}
aa01666d	117
57be2b48 PM	118	static void tmu_set_mode(enum clock_event_mode mode,
	119	struct clock_event_device *evt)
	120	{
	121	switch (mode) {
	122	case CLOCK_EVT_MODE_PERIODIC:
2cd0ebc8	123	ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
57be2b48 PM	124	break;
	125	case CLOCK_EVT_MODE_ONESHOT:
	126	ctrl_outl(0, TMU0_TCOR);
	127	break;
	128	case CLOCK_EVT_MODE_UNUSED:
	129	case CLOCK_EVT_MODE_SHUTDOWN:
18de5bc4	130	case CLOCK_EVT_MODE_RESUME:
57be2b48 PM	131	break;
57be2b48 PM	132	}
aa01666d PM	133	}
aa01666d PM	134
57be2b48 PM	135	static struct clock_event_device tmu0_clockevent = {
	136	.name = "tmu0",
	137	.shift = 32,
	138	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	139	.set_mode = tmu_set_mode,
	140	.set_next_event = tmu_set_next_event,
	141	};
	142
35f3c518	143	static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
aa01666d	144	{
57be2b48	145	struct clock_event_device *evt = &tmu0_clockevent;
61c66387 FV	146	_tmu_clear_status(TMU0);
61c66387 FV	147	_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
aa01666d	148
70f08001 MD	149	switch (tmu0_clockevent.mode) {
	150	case CLOCK_EVT_MODE_ONESHOT:
	151	case CLOCK_EVT_MODE_PERIODIC:
	152	evt->event_handler(evt);
	153	break;
	154	default:
	155	break;
	156	}
aa01666d PM	157
	158	return IRQ_HANDLED;
	159	}
	160
57be2b48	161	static struct irqaction tmu0_irq = {
61c66387	162	.name = "periodic/oneshot timer",
aa01666d	163	.handler = tmu_timer_interrupt,
e9485bae	164	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
aa01666d PM	165	};
aa01666d PM	166
61c66387	167	static void __init tmu_clk_init(struct clk *clk)
aa01666d	168	{
61c66387 FV	169	u8 divisor = TMU_TCR_INIT & 0x7;
	170	int tmu_num = clk->name[3]-'0';
	171	ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
	172	clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
aa01666d PM	173	}
aa01666d PM	174
61c66387	175	static void tmu_clk_recalc(struct clk *clk)
aa01666d	176	{
61c66387 FV	177	int tmu_num = clk->name[3]-'0';
	178	unsigned long prev_rate = clk_get_rate(clk);
	179	unsigned long flags;
	180	u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
	181	clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
aa01666d	182
61c66387 FV	183	if(prev_rate==clk_get_rate(clk))
61c66387 FV	184	return;
aa01666d	185
61c66387 FV	186	if(tmu_num)
61c66387 FV	187	return; /* No more work on TMU1 */
aa01666d	188
61c66387 FV	189	local_irq_save(flags);
61c66387 FV	190	tmus_are_scaled = (prev_rate > clk->rate);
3aa770e7	191
61c66387 FV	192	_tmu_stop(TMU0);
	193
	194	tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
	195	tmu0_clockevent.shift);
	196	tmu0_clockevent.max_delta_ns =
	197	clockevent_delta2ns(-1, &tmu0_clockevent);
	198	tmu0_clockevent.min_delta_ns =
	199	clockevent_delta2ns(1, &tmu0_clockevent);
	200
	201	if (tmus_are_scaled)
	202	tmu_latest_interval[TMU0] >>= 1;
	203	else
	204	tmu_latest_interval[TMU0] <<= 1;
	205
	206	tmu_timer_set_interval(TMU0,
	207	tmu_latest_interval[TMU0],
	208	tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
	209
	210	_tmu_start(TMU0);
	211
	212	local_irq_restore(flags);
3aa770e7 AS	213	}
3aa770e7 AS	214
61c66387 FV	215	static struct clk_ops tmu_clk_ops = {
	216	.init = tmu_clk_init,
	217	.recalc = tmu_clk_recalc,
	218	};
	219
	220	static struct clk tmu0_clk = {
	221	.name = "tmu0_clk",
	222	.ops = &tmu_clk_ops,
57be2b48 PM	223	};
	224
	225	static struct clk tmu1_clk = {
	226	.name = "tmu1_clk",
61c66387	227	.ops = &tmu_clk_ops,
57be2b48 PM	228	};
57be2b48 PM	229
aa01666d PM	230	static int tmu_timer_init(void)
	231	{
	232	unsigned long interval;
57be2b48	233	unsigned long frequency;
aa01666d	234
57be2b48	235	setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
aa01666d	236
1d118562	237	tmu0_clk.parent = clk_get(NULL, "module_clk");
57be2b48	238	tmu1_clk.parent = clk_get(NULL, "module_clk");
aa01666d	239
3aa770e7	240	tmu_timer_stop();
57be2b48	241
3ea6bc3d	242	#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
31a49c4b	243	!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
3ea6bc3d	244	!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
2b1bd1ac	245	!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
55ba99eb	246	!defined(CONFIG_CPU_SUBTYPE_SH7786) && \
2b1bd1ac	247	!defined(CONFIG_CPU_SUBTYPE_SHX3)
aa01666d PM	248	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
	249	#endif
	250
	251	clk_register(&tmu0_clk);
57be2b48	252	clk_register(&tmu1_clk);
aa01666d	253	clk_enable(&tmu0_clk);
57be2b48	254	clk_enable(&tmu1_clk);
aa01666d	255
57be2b48 PM	256	frequency = clk_get_rate(&tmu0_clk);
57be2b48 PM	257	interval = (frequency + HZ / 2) / HZ;
aa01666d	258
61c66387 FV	259	tmu_timer_set_interval(TMU0,interval, 1);
61c66387 FV	260	tmu_timer_set_interval(TMU1,~0,1);
aa01666d	261
61c66387 FV	262	_tmu_start(TMU1);
61c66387 FV	263
955c0778 MD	264	clocksource_sh.rating = 200;
	265	clocksource_sh.mask = CLOCKSOURCE_MASK(32);
	266	clocksource_sh.read = tmu_timer_read;
	267	clocksource_sh.shift = 10;
	268	clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
	269	clocksource_sh.shift);
	270	clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	271	clocksource_register(&clocksource_sh);
57be2b48 PM	272
	273	tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
	274	tmu0_clockevent.shift);
	275	tmu0_clockevent.max_delta_ns =
	276	clockevent_delta2ns(-1, &tmu0_clockevent);
	277	tmu0_clockevent.min_delta_ns =
	278	clockevent_delta2ns(1, &tmu0_clockevent);
	279
320ab2b0	280	tmu0_clockevent.cpumask = cpumask_of(0);
70f08001	281	tmu0_clockevent.rating = 100;
57be2b48 PM	282
57be2b48 PM	283	clockevents_register_device(&tmu0_clockevent);
aa01666d PM	284
	285	return 0;
	286	}
	287
4c1cfab1	288	static struct sys_timer_ops tmu_timer_ops = {
aa01666d	289	.init = tmu_timer_init,
3aa770e7 AS	290	.start = tmu_timer_start,
3aa770e7 AS	291	.stop = tmu_timer_stop,
aa01666d PM	292	};
	293
	294	struct sys_timer tmu_timer = {
	295	.name = "tmu",
	296	.ops = &tmu_timer_ops,
	297	};