Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Precise Delay Loops for SuperH | |
3 | * | |
4 | * Copyright (C) 1999 Niibe Yutaka & Kaz Kojima | |
5 | */ | |
6 | ||
7 | #include <linux/sched.h> | |
8 | #include <linux/delay.h> | |
9 | ||
10 | void __delay(unsigned long loops) | |
11 | { | |
12 | __asm__ __volatile__( | |
a0865368 SM |
13 | /* |
14 | * ST40-300 appears to have an issue with this code, | |
15 | * normally taking two cycles each loop, as with all | |
16 | * other SH variants. If however the branch and the | |
17 | * delay slot straddle an 8 byte boundary, this increases | |
18 | * to 3 cycles. | |
19 | * This align directive ensures this doesn't occur. | |
20 | */ | |
21 | ".balign 8\n\t" | |
22 | ||
1da177e4 LT |
23 | "tst %0, %0\n\t" |
24 | "1:\t" | |
25 | "bf/s 1b\n\t" | |
26 | " dt %0" | |
27 | : "=r" (loops) | |
28 | : "0" (loops) | |
29 | : "t"); | |
30 | } | |
31 | ||
32 | inline void __const_udelay(unsigned long xloops) | |
33 | { | |
bd4fb4d4 | 34 | xloops *= 4; |
1da177e4 LT |
35 | __asm__("dmulu.l %0, %2\n\t" |
36 | "sts mach, %0" | |
37 | : "=r" (xloops) | |
c71861e6 | 38 | : "0" (xloops), |
bd4fb4d4 | 39 | "r" (cpu_data[raw_smp_processor_id()].loops_per_jiffy * (HZ/4)) |
1da177e4 | 40 | : "macl", "mach"); |
bd4fb4d4 | 41 | __delay(++xloops); |
1da177e4 LT |
42 | } |
43 | ||
44 | void __udelay(unsigned long usecs) | |
45 | { | |
46 | __const_udelay(usecs * 0x000010c6); /* 2**32 / 1000000 */ | |
47 | } | |
48 | ||
49 | void __ndelay(unsigned long nsecs) | |
50 | { | |
51 | __const_udelay(nsecs * 0x00000005); | |
52 | } | |
53 |