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cad82448 PM |
1 | # |
2 | # Processor families | |
3 | # | |
4 | config CPU_SH2 | |
9d4436a6 | 5 | select SH_WRITETHROUGH if !CPU_SH2A |
cad82448 | 6 | bool |
9d4436a6 YS |
7 | |
8 | config CPU_SH2A | |
9 | bool | |
10 | select CPU_SH2 | |
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11 | |
12 | config CPU_SH3 | |
13 | bool | |
14 | select CPU_HAS_INTEVT | |
15 | select CPU_HAS_SR_RB | |
16 | ||
17 | config CPU_SH4 | |
18 | bool | |
19 | select CPU_HAS_INTEVT | |
20 | select CPU_HAS_SR_RB | |
26b7a78c | 21 | select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 |
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22 | |
23 | config CPU_SH4A | |
24 | bool | |
25 | select CPU_SH4 | |
cad82448 | 26 | |
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27 | config CPU_SH4AL_DSP |
28 | bool | |
29 | select CPU_SH4A | |
ac79fd58 | 30 | select CPU_HAS_DSP |
e5723e0e | 31 | |
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32 | config CPU_SUBTYPE_ST40 |
33 | bool | |
34 | select CPU_SH4 | |
35 | select CPU_HAS_INTC2_IRQ | |
36 | ||
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37 | config CPU_SHX2 |
38 | bool | |
39 | ||
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40 | config CPU_SHX3 |
41 | bool | |
42 | ||
f3d22298 PM |
43 | choice |
44 | prompt "Processor sub-type selection" | |
45 | ||
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46 | # |
47 | # Processor subtypes | |
48 | # | |
49 | ||
f3d22298 | 50 | # SH-2 Processor Support |
cad82448 | 51 | |
9d4436a6 YS |
52 | config CPU_SUBTYPE_SH7619 |
53 | bool "Support SH7619 processor" | |
54 | select CPU_SH2 | |
357d5946 | 55 | select CPU_HAS_IPR_IRQ |
9d4436a6 | 56 | |
f3d22298 | 57 | # SH-2A Processor Support |
9d4436a6 YS |
58 | |
59 | config CPU_SUBTYPE_SH7206 | |
60 | bool "Support SH7206 processor" | |
61 | select CPU_SH2A | |
fa1ec92e | 62 | select CPU_HAS_IPR_IRQ |
9d4436a6 | 63 | |
f3d22298 | 64 | # SH-3 Processor Support |
cad82448 | 65 | |
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66 | config CPU_SUBTYPE_SH7705 |
67 | bool "Support SH7705 processor" | |
68 | select CPU_SH3 | |
70e8be0a | 69 | select CPU_HAS_INTC_IRQ |
cad82448 | 70 | |
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71 | config CPU_SUBTYPE_SH7706 |
72 | bool "Support SH7706 processor" | |
73 | select CPU_SH3 | |
ec58f1f3 | 74 | select CPU_HAS_INTC_IRQ |
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75 | help |
76 | Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. | |
77 | ||
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78 | config CPU_SUBTYPE_SH7707 |
79 | bool "Support SH7707 processor" | |
80 | select CPU_SH3 | |
ec58f1f3 | 81 | select CPU_HAS_INTC_IRQ |
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82 | help |
83 | Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. | |
84 | ||
85 | config CPU_SUBTYPE_SH7708 | |
86 | bool "Support SH7708 processor" | |
87 | select CPU_SH3 | |
ec58f1f3 | 88 | select CPU_HAS_INTC_IRQ |
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89 | help |
90 | Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or | |
91 | if you have a 100 Mhz SH-3 HD6417708R CPU. | |
92 | ||
93 | config CPU_SUBTYPE_SH7709 | |
94 | bool "Support SH7709 processor" | |
95 | select CPU_SH3 | |
ec58f1f3 | 96 | select CPU_HAS_INTC_IRQ |
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97 | help |
98 | Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. | |
99 | ||
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100 | config CPU_SUBTYPE_SH7710 |
101 | bool "Support SH7710 processor" | |
102 | select CPU_SH3 | |
28b146c8 | 103 | select CPU_HAS_INTC_IRQ |
ac79fd58 | 104 | select CPU_HAS_DSP |
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105 | help |
106 | Select SH7710 if you have a SH3-DSP SH7710 CPU. | |
107 | ||
9465a54f NI |
108 | config CPU_SUBTYPE_SH7712 |
109 | bool "Support SH7712 processor" | |
110 | select CPU_SH3 | |
28b146c8 | 111 | select CPU_HAS_INTC_IRQ |
ac79fd58 | 112 | select CPU_HAS_DSP |
9465a54f NI |
113 | help |
114 | Select SH7712 if you have a SH3-DSP SH7712 CPU. | |
115 | ||
f3d22298 | 116 | # SH-4 Processor Support |
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117 | |
118 | config CPU_SUBTYPE_SH7750 | |
119 | bool "Support SH7750 processor" | |
120 | select CPU_SH4 | |
56386f64 | 121 | select CPU_HAS_INTC_IRQ |
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122 | help |
123 | Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. | |
124 | ||
125 | config CPU_SUBTYPE_SH7091 | |
126 | bool "Support SH7091 processor" | |
127 | select CPU_SH4 | |
56386f64 | 128 | select CPU_HAS_INTC_IRQ |
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129 | help |
130 | Select SH7091 if you have an SH-4 based Sega device (such as | |
131 | the Dreamcast, Naomi, and Naomi 2). | |
132 | ||
133 | config CPU_SUBTYPE_SH7750R | |
134 | bool "Support SH7750R processor" | |
135 | select CPU_SH4 | |
56386f64 | 136 | select CPU_HAS_INTC_IRQ |
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137 | |
138 | config CPU_SUBTYPE_SH7750S | |
139 | bool "Support SH7750S processor" | |
140 | select CPU_SH4 | |
56386f64 | 141 | select CPU_HAS_INTC_IRQ |
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142 | |
143 | config CPU_SUBTYPE_SH7751 | |
144 | bool "Support SH7751 processor" | |
145 | select CPU_SH4 | |
56386f64 | 146 | select CPU_HAS_INTC_IRQ |
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147 | help |
148 | Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, | |
149 | or if you have a HD6417751R CPU. | |
150 | ||
151 | config CPU_SUBTYPE_SH7751R | |
152 | bool "Support SH7751R processor" | |
153 | select CPU_SH4 | |
56386f64 | 154 | select CPU_HAS_INTC_IRQ |
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155 | |
156 | config CPU_SUBTYPE_SH7760 | |
157 | bool "Support SH7760 processor" | |
158 | select CPU_SH4 | |
159 | select CPU_HAS_INTC2_IRQ | |
6dcda6f1 | 160 | select CPU_HAS_IPR_IRQ |
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161 | |
162 | config CPU_SUBTYPE_SH4_202 | |
163 | bool "Support SH4-202 processor" | |
164 | select CPU_SH4 | |
165 | ||
f3d22298 | 166 | # ST40 Processor Support |
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167 | |
168 | config CPU_SUBTYPE_ST40STB1 | |
169 | bool "Support ST40STB1/ST40RA processors" | |
170 | select CPU_SUBTYPE_ST40 | |
171 | help | |
172 | Select ST40STB1 if you have a ST40RA CPU. | |
173 | This was previously called the ST40STB1, hence the option name. | |
174 | ||
175 | config CPU_SUBTYPE_ST40GX1 | |
176 | bool "Support ST40GX1 processor" | |
177 | select CPU_SUBTYPE_ST40 | |
178 | help | |
179 | Select ST40GX1 if you have a ST40GX1 CPU. | |
180 | ||
f3d22298 | 181 | # SH-4A Processor Support |
cad82448 | 182 | |
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183 | config CPU_SUBTYPE_SH7770 |
184 | bool "Support SH7770 processor" | |
185 | select CPU_SH4A | |
186 | ||
187 | config CPU_SUBTYPE_SH7780 | |
188 | bool "Support SH7780 processor" | |
189 | select CPU_SH4A | |
39c7aa9e | 190 | select CPU_HAS_INTC_IRQ |
cad82448 | 191 | |
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192 | config CPU_SUBTYPE_SH7785 |
193 | bool "Support SH7785 processor" | |
194 | select CPU_SH4A | |
41504c39 | 195 | select CPU_SHX2 |
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196 | select CPU_HAS_INTC2_IRQ |
197 | ||
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198 | config CPU_SUBTYPE_SHX3 |
199 | bool "Support SH-X3 processor" | |
200 | select CPU_SH4A | |
201 | select CPU_SHX3 | |
202 | select CPU_HAS_INTC2_IRQ | |
203 | ||
f3d22298 | 204 | # SH4AL-DSP Processor Support |
e5723e0e | 205 | |
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206 | config CPU_SUBTYPE_SH7343 |
207 | bool "Support SH7343 processor" | |
208 | select CPU_SH4AL_DSP | |
209 | ||
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210 | config CPU_SUBTYPE_SH7722 |
211 | bool "Support SH7722 processor" | |
212 | select CPU_SH4AL_DSP | |
213 | select CPU_SHX2 | |
1b06428e | 214 | select CPU_HAS_INTC_IRQ |
520588f4 | 215 | select ARCH_SPARSEMEM_ENABLE |
357d5946 | 216 | select SYS_SUPPORTS_NUMA |
41504c39 | 217 | |
f3d22298 | 218 | endchoice |
cad82448 PM |
219 | |
220 | menu "Memory management options" | |
221 | ||
5f8c9908 PM |
222 | config QUICKLIST |
223 | def_bool y | |
224 | ||
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225 | config MMU |
226 | bool "Support for memory management hardware" | |
227 | depends on !CPU_SH2 | |
228 | default y | |
229 | help | |
230 | Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to | |
231 | boot on these systems, this option must not be set. | |
232 | ||
233 | On other systems (such as the SH-3 and 4) where an MMU exists, | |
234 | turning this off will boot the kernel on these machines with the | |
235 | MMU implicitly switched off. | |
236 | ||
e7f93a35 PM |
237 | config PAGE_OFFSET |
238 | hex | |
239 | default "0x80000000" if MMU | |
240 | default "0x00000000" | |
241 | ||
242 | config MEMORY_START | |
243 | hex "Physical memory start address" | |
244 | default "0x08000000" | |
245 | ---help--- | |
246 | Computers built with Hitachi SuperH processors always | |
247 | map the ROM starting at address zero. But the processor | |
248 | does not specify the range that RAM takes. | |
249 | ||
250 | The physical memory (RAM) start address will be automatically | |
251 | set to 08000000. Other platforms, such as the Solution Engine | |
252 | boards typically map RAM at 0C000000. | |
253 | ||
254 | Tweak this only when porting to a new machine which does not | |
255 | already have a defconfig. Changing it from the known correct | |
256 | value on any of the known systems will only lead to disaster. | |
257 | ||
258 | config MEMORY_SIZE | |
259 | hex "Physical memory size" | |
260 | default "0x00400000" | |
261 | help | |
262 | This sets the default memory size assumed by your SH kernel. It can | |
263 | be overridden as normal by the 'mem=' argument on the kernel command | |
264 | line. If unsure, consult your board specifications or just leave it | |
265 | as 0x00400000 which was the default value before this became | |
266 | configurable. | |
267 | ||
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268 | config 32BIT |
269 | bool "Support 32-bit physical addressing through PMB" | |
50f63f25 | 270 | depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) |
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271 | default y |
272 | help | |
273 | If you say Y here, physical addressing will be extended to | |
274 | 32-bits through the SH-4A PMB. If this is not set, legacy | |
275 | 29-bit physical addressing will be used. | |
276 | ||
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277 | config X2TLB |
278 | bool "Enable extended TLB mode" | |
41504c39 | 279 | depends on CPU_SHX2 && MMU && EXPERIMENTAL |
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280 | help |
281 | Selecting this option will enable the extended mode of the SH-X2 | |
282 | TLB. For legacy SH-X behaviour and interoperability, say N. For | |
283 | all of the fun new features and a willingless to submit bug reports, | |
284 | say Y. | |
285 | ||
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286 | config VSYSCALL |
287 | bool "Support vsyscall page" | |
288 | depends on MMU | |
289 | default y | |
290 | help | |
291 | This will enable support for the kernel mapping a vDSO page | |
292 | in process space, and subsequently handing down the entry point | |
293 | to the libc through the ELF auxiliary vector. | |
294 | ||
295 | From the kernel side this is used for the signal trampoline. | |
296 | For systems with an MMU that can afford to give up a page, | |
297 | (the default value) say Y. | |
298 | ||
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299 | config NUMA |
300 | bool "Non Uniform Memory Access (NUMA) Support" | |
357d5946 | 301 | depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL |
b241cb0c PM |
302 | default n |
303 | help | |
304 | Some SH systems have many various memories scattered around | |
305 | the address space, each with varying latencies. This enables | |
306 | support for these blocks by binding them to nodes and allowing | |
307 | memory policies to be used for prioritizing and controlling | |
308 | allocation behaviour. | |
309 | ||
01066625 PM |
310 | config NODES_SHIFT |
311 | int | |
312 | default "1" | |
313 | depends on NEED_MULTIPLE_NODES | |
314 | ||
315 | config ARCH_FLATMEM_ENABLE | |
316 | def_bool y | |
357d5946 | 317 | depends on !NUMA |
01066625 | 318 | |
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319 | config ARCH_SPARSEMEM_ENABLE |
320 | def_bool y | |
321 | select SPARSEMEM_STATIC | |
322 | ||
323 | config ARCH_SPARSEMEM_DEFAULT | |
324 | def_bool y | |
325 | ||
1ce7ddd5 PM |
326 | config MAX_ACTIVE_REGIONS |
327 | int | |
520588f4 | 328 | default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM) |
1ce7ddd5 PM |
329 | default "1" |
330 | ||
01066625 PM |
331 | config ARCH_POPULATES_NODE_MAP |
332 | def_bool y | |
333 | ||
dfbb9042 PM |
334 | config ARCH_SELECT_MEMORY_MODEL |
335 | def_bool y | |
336 | ||
33d63bd8 PM |
337 | config ARCH_ENABLE_MEMORY_HOTPLUG |
338 | def_bool y | |
339 | depends on SPARSEMEM | |
340 | ||
341 | config ARCH_MEMORY_PROBE | |
342 | def_bool y | |
343 | depends on MEMORY_HOTPLUG | |
344 | ||
21440cf0 PM |
345 | choice |
346 | prompt "Kernel page size" | |
347 | default PAGE_SIZE_4KB | |
348 | ||
349 | config PAGE_SIZE_4KB | |
350 | bool "4kB" | |
351 | help | |
352 | This is the default page size used by all SuperH CPUs. | |
353 | ||
354 | config PAGE_SIZE_8KB | |
355 | bool "8kB" | |
356 | depends on EXPERIMENTAL && X2TLB | |
357 | help | |
358 | This enables 8kB pages as supported by SH-X2 and later MMUs. | |
359 | ||
360 | config PAGE_SIZE_64KB | |
361 | bool "64kB" | |
362 | depends on EXPERIMENTAL && CPU_SH4 | |
363 | help | |
364 | This enables support for 64kB pages, possible on all SH-4 | |
365 | CPUs and later. Highly experimental, not recommended. | |
366 | ||
367 | endchoice | |
368 | ||
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369 | choice |
370 | prompt "HugeTLB page size" | |
371 | depends on HUGETLB_PAGE && CPU_SH4 && MMU | |
372 | default HUGETLB_PAGE_SIZE_64K | |
373 | ||
374 | config HUGETLB_PAGE_SIZE_64K | |
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375 | bool "64kB" |
376 | ||
377 | config HUGETLB_PAGE_SIZE_256K | |
378 | bool "256kB" | |
379 | depends on X2TLB | |
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380 | |
381 | config HUGETLB_PAGE_SIZE_1MB | |
382 | bool "1MB" | |
383 | ||
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384 | config HUGETLB_PAGE_SIZE_4MB |
385 | bool "4MB" | |
386 | depends on X2TLB | |
387 | ||
388 | config HUGETLB_PAGE_SIZE_64MB | |
389 | bool "64MB" | |
390 | depends on X2TLB | |
391 | ||
cad82448 PM |
392 | endchoice |
393 | ||
394 | source "mm/Kconfig" | |
395 | ||
396 | endmenu | |
397 | ||
398 | menu "Cache configuration" | |
399 | ||
400 | config SH7705_CACHE_32KB | |
401 | bool "Enable 32KB cache size for SH7705" | |
402 | depends on CPU_SUBTYPE_SH7705 | |
403 | default y | |
404 | ||
405 | config SH_DIRECT_MAPPED | |
406 | bool "Use direct-mapped caching" | |
407 | default n | |
408 | help | |
409 | Selecting this option will configure the caches to be direct-mapped, | |
410 | even if the cache supports a 2 or 4-way mode. This is useful primarily | |
411 | for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, | |
412 | SH4-202, SH4-501, etc.) | |
413 | ||
414 | Turn this option off for platforms that do not have a direct-mapped | |
415 | cache, and you have no need to run the caches in such a configuration. | |
416 | ||
417 | config SH_WRITETHROUGH | |
418 | bool "Use write-through caching" | |
cad82448 PM |
419 | help |
420 | Selecting this option will configure the caches in write-through | |
421 | mode, as opposed to the default write-back configuration. | |
422 | ||
423 | Since there's sill some aliasing issues on SH-4, this option will | |
424 | unfortunately still require the majority of flushing functions to | |
425 | be implemented to deal with aliasing. | |
426 | ||
427 | If unsure, say N. | |
428 | ||
cad82448 | 429 | endmenu |