[deliverable/linux.git] / arch / sh / mm / Makefile

#
# Makefile for the Linux SuperH-specific parts of the memory manager.
#

obj-y			:= alignment.o cache.o init.o consistent.o mmap.o

cacheops-$(CONFIG_CPU_SH2)		:= cache-sh2.o
cacheops-$(CONFIG_CPU_SH2A)		:= cache-sh2a.o
cacheops-$(CONFIG_CPU_SH3)		:= cache-sh3.o
cacheops-$(CONFIG_CPU_SH4)		:= cache-sh4.o flush-sh4.o
cacheops-$(CONFIG_CPU_SH5)		:= cache-sh5.o flush-sh4.o
cacheops-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o
cacheops-$(CONFIG_CPU_SHX3)		+= cache-shx3.o

obj-y			+= $(cacheops-y)

mmu-y			:= nommu.o extable_32.o
mmu-$(CONFIG_MMU)	:= extable_$(BITS).o fault.o gup.o ioremap.o kmap.o \
			   pgtable.o tlbex_$(BITS).o tlbflush_$(BITS).o

obj-y			+= $(mmu-y)

debugfs-y			:= asids-debugfs.o
ifndef CONFIG_CACHE_OFF
debugfs-$(CONFIG_CPU_SH4)	+= cache-debugfs.o
endif

ifdef CONFIG_MMU
debugfs-$(CONFIG_CPU_SH4)	+= tlb-debugfs.o
tlb-$(CONFIG_CPU_SH3)		:= tlb-sh3.o
tlb-$(CONFIG_CPU_SH4)		:= tlb-sh4.o tlb-urb.o
tlb-$(CONFIG_CPU_SH5)		:= tlb-sh5.o
tlb-$(CONFIG_CPU_HAS_PTEAEX)	:= tlb-pteaex.o tlb-urb.o
obj-y				+= $(tlb-y)
endif

obj-$(CONFIG_DEBUG_FS)		+= $(debugfs-y)
obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
obj-$(CONFIG_PMB)		+= pmb.o
obj-$(CONFIG_NUMA)		+= numa.o
obj-$(CONFIG_IOREMAP_FIXED)	+= ioremap_fixed.o
obj-$(CONFIG_UNCACHED_MAPPING)	+= uncached.o
obj-$(CONFIG_HAVE_SRAM_POOL)	+= sram.o

GCOV_PROFILE_pmb.o := n

# Special flags for tlbex_64.o.  This puts restrictions on the number of
# caller-save registers that the compiler can target when building this file.
# This is required because the code is called from a context in entry.S where
# very few registers have been saved in the exception handler (for speed
# reasons).
# The caller save registers that have been saved and which can be used are
# r2,r3,r4,r5 : argument passing
# r15, r18 : SP and LINK
# tr0-4 : allow all caller-save TR's.  The compiler seems to be able to make
#         use of them, so it's probably beneficial to performance to save them
#         and have them available for it.
#
# The resources not listed below are callee save, i.e. the compiler is free to
# use any of them and will spill them to the stack itself.

CFLAGS_tlbex_64.o += -ffixed-r7 \
	-ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \
	-ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \
	-ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \
	-ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \
	-ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \
	-ffixed-r41 -ffixed-r42 -ffixed-r43  \
	-ffixed-r60 -ffixed-r61 -ffixed-r62 \
	-fomit-frame-pointer

ccflags-y := -Werror
Commit	Line	Data
1b3edd97 PM	1	#
	2	# Makefile for the Linux SuperH-specific parts of the memory manager.
	3	#
	4
a99eae54	5	obj-y := alignment.o cache.o init.o consistent.o mmap.o
1b3edd97	6
1b3edd97 PM	7	cacheops-$(CONFIG_CPU_SH2) := cache-sh2.o
	8	cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o
	9	cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o
	10	cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
	11	cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o
	12	cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
3cf6fa1e	13	cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o
1b3edd97 PM	14
	15	obj-y += $(cacheops-y)
	16
	17	mmu-y := nommu.o extable_32.o
28080329 PM	18	mmu-$(CONFIG_MMU) := extable_$(BITS).o fault.o gup.o ioremap.o kmap.o \
28080329 PM	19	pgtable.o tlbex_$(BITS).o tlbflush_$(BITS).o
1b3edd97 PM	20
1b3edd97 PM	21	obj-y += $(mmu-y)
1b3edd97	22
6ae66502 MF	23	debugfs-y := asids-debugfs.o
	24	ifndef CONFIG_CACHE_OFF
	25	debugfs-$(CONFIG_CPU_SH4) += cache-debugfs.o
1b3edd97 PM	26	endif
	27
	28	ifdef CONFIG_MMU
6ae66502	29	debugfs-$(CONFIG_CPU_SH4) += tlb-debugfs.o
1b3edd97	30	tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
bb29c677	31	tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o
1b3edd97	32	tlb-$(CONFIG_CPU_SH5) := tlb-sh5.o
bb29c677	33	tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o
1b3edd97 PM	34	obj-y += $(tlb-y)
	35	endif
	36
6ae66502	37	obj-$(CONFIG_DEBUG_FS) += $(debugfs-y)
1b3edd97	38	obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
a0ab3668	39	obj-$(CONFIG_PMB) += pmb.o
1b3edd97	40	obj-$(CONFIG_NUMA) += numa.o
4d35b93a	41	obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o
9edef286	42	obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o
c993487e	43	obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o
1b3edd97	44
d4f7e513 CS	45	GCOV_PROFILE_pmb.o := n
d4f7e513 CS	46
2ec08e14	47	# Special flags for tlbex_64.o. This puts restrictions on the number of
1b3edd97 PM	48	# caller-save registers that the compiler can target when building this file.
	49	# This is required because the code is called from a context in entry.S where
	50	# very few registers have been saved in the exception handler (for speed
	51	# reasons).
	52	# The caller save registers that have been saved and which can be used are
	53	# r2,r3,r4,r5 : argument passing
	54	# r15, r18 : SP and LINK
	55	# tr0-4 : allow all caller-save TR's. The compiler seems to be able to make
	56	# use of them, so it's probably beneficial to performance to save them
	57	# and have them available for it.
	58	#
	59	# The resources not listed below are callee save, i.e. the compiler is free to
	60	# use any of them and will spill them to the stack itself.
	61
2ec08e14	62	CFLAGS_tlbex_64.o += -ffixed-r7 \
1b3edd97 PM	63	-ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \
	64	-ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \
	65	-ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \
	66	-ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \
	67	-ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \
	68	-ffixed-r41 -ffixed-r42 -ffixed-r43 \
	69	-ffixed-r60 -ffixed-r61 -ffixed-r62 \
	70	-fomit-frame-pointer
	71
a234ca0f	72	ccflags-y := -Werror