[deliverable/linux.git] / arch / sh / mm / cache-debugfs.c

/*
 * debugfs ops for the L1 cache
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <asm/cache.h>
#include <asm/io.h>

enum cache_type {
	CACHE_TYPE_ICACHE,
	CACHE_TYPE_DCACHE,
	CACHE_TYPE_UNIFIED,
};

static int cache_seq_show(struct seq_file *file, void *iter)
{
	unsigned int cache_type = (unsigned int)file->private;
	struct cache_info *cache;
	unsigned int waysize, way;
	unsigned long ccr;
	unsigned long addrstart = 0;

	/*
	 * Go uncached immediately so we don't skew the results any
	 * more than we already are..
	 */
	jump_to_uncached();

	ccr = __raw_readl(SH_CCR);
	if ((ccr & CCR_CACHE_ENABLE) == 0) {
		back_to_cached();

		seq_printf(file, "disabled\n");
		return 0;
	}

	if (cache_type == CACHE_TYPE_DCACHE) {
		addrstart = CACHE_OC_ADDRESS_ARRAY;
		cache = &current_cpu_data.dcache;
	} else {
		addrstart = CACHE_IC_ADDRESS_ARRAY;
		cache = &current_cpu_data.icache;
	}

	waysize = cache->sets;

	/*
	 * If the OC is already in RAM mode, we only have
	 * half of the entries to consider..
	 */
	if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
		waysize >>= 1;

	waysize <<= cache->entry_shift;

	for (way = 0; way < cache->ways; way++) {
		unsigned long addr;
		unsigned int line;

		seq_printf(file, "-----------------------------------------\n");
		seq_printf(file, "Way %d\n", way);
		seq_printf(file, "-----------------------------------------\n");

		for (addr = addrstart, line = 0;
		     addr < addrstart + waysize;
		     addr += cache->linesz, line++) {
			unsigned long data = __raw_readl(addr);

			/* Check the V bit, ignore invalid cachelines */
			if ((data & 1) == 0)
				continue;

			/* U: Dirty, cache tag is 10 bits up */
			seq_printf(file, "%3d: %c 0x%lx\n",
				   line, data & 2 ? 'U' : ' ',
				   data & 0x1ffffc00);
		}

		addrstart += cache->way_incr;
	}

	back_to_cached();

	return 0;
}

static int cache_debugfs_open(struct inode *inode, struct file *file)
{
	return single_open(file, cache_seq_show, inode->i_private);
}

static const struct file_operations cache_debugfs_fops = {
	.owner		= THIS_MODULE,
	.open		= cache_debugfs_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init cache_debugfs_init(void)
{
	struct dentry *dcache_dentry, *icache_dentry;

	dcache_dentry = debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
					    (unsigned int *)CACHE_TYPE_DCACHE,
					    &cache_debugfs_fops);
	if (!dcache_dentry)
		return -ENOMEM;

	icache_dentry = debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
					    (unsigned int *)CACHE_TYPE_ICACHE,
					    &cache_debugfs_fops);
	if (!icache_dentry) {
		debugfs_remove(dcache_dentry);
		return -ENOMEM;
	}

	return 0;
}
module_init(cache_debugfs_init);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
15f57a29 PM	1	/*
	2	* debugfs ops for the L1 cache
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/module.h>
	12	#include <linux/debugfs.h>
	13	#include <linux/seq_file.h>
	14	#include <asm/processor.h>
	15	#include <asm/uaccess.h>
	16	#include <asm/cache.h>
	17	#include <asm/io.h>
	18
	19	enum cache_type {
	20	CACHE_TYPE_ICACHE,
	21	CACHE_TYPE_DCACHE,
	22	CACHE_TYPE_UNIFIED,
	23	};
	24
2dc2f8e0	25	static int cache_seq_show(struct seq_file file, void iter)
15f57a29 PM	26	{
	27	unsigned int cache_type = (unsigned int)file->private;
	28	struct cache_info *cache;
298c48a8 SK	29	unsigned int waysize, way;
	30	unsigned long ccr;
	31	unsigned long addrstart = 0;
15f57a29 PM	32
	33	/*
	34	* Go uncached immediately so we don't skew the results any
	35	* more than we already are..
	36	*/
cbaa118e	37	jump_to_uncached();
15f57a29	38
a5f6ea29	39	ccr = __raw_readl(SH_CCR);
15f57a29	40	if ((ccr & CCR_CACHE_ENABLE) == 0) {
cbaa118e	41	back_to_cached();
15f57a29 PM	42
	43	seq_printf(file, "disabled\n");
	44	return 0;
	45	}
	46
	47	if (cache_type == CACHE_TYPE_DCACHE) {
298c48a8	48	addrstart = CACHE_OC_ADDRESS_ARRAY;
11c19656	49	cache = &current_cpu_data.dcache;
15f57a29	50	} else {
298c48a8	51	addrstart = CACHE_IC_ADDRESS_ARRAY;
11c19656	52	cache = &current_cpu_data.icache;
15f57a29 PM	53	}
15f57a29 PM	54
15f57a29 PM	55	waysize = cache->sets;
	56
	57	/*
	58	* If the OC is already in RAM mode, we only have
	59	* half of the entries to consider..
	60	*/
	61	if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
	62	waysize >>= 1;
	63
	64	waysize <<= cache->entry_shift;
	65
	66	for (way = 0; way < cache->ways; way++) {
	67	unsigned long addr;
	68	unsigned int line;
	69
	70	seq_printf(file, "-----------------------------------------\n");
	71	seq_printf(file, "Way %d\n", way);
	72	seq_printf(file, "-----------------------------------------\n");
	73
	74	for (addr = addrstart, line = 0;
	75	addr < addrstart + waysize;
	76	addr += cache->linesz, line++) {
9d56dd3b	77	unsigned long data = __raw_readl(addr);
15f57a29 PM	78
	79	/* Check the V bit, ignore invalid cachelines */
	80	if ((data & 1) == 0)
	81	continue;
	82
	83	/* U: Dirty, cache tag is 10 bits up */
	84	seq_printf(file, "%3d: %c 0x%lx\n",
	85	line, data & 2 ? 'U' : ' ',
	86	data & 0x1ffffc00);
	87	}
	88
	89	addrstart += cache->way_incr;
	90	}
	91
cbaa118e	92	back_to_cached();
15f57a29 PM	93
	94	return 0;
	95	}
	96
	97	static int cache_debugfs_open(struct inode inode, struct file file)
	98	{
711fa809	99	return single_open(file, cache_seq_show, inode->i_private);
15f57a29 PM	100	}
15f57a29 PM	101
5dfe4c96	102	static const struct file_operations cache_debugfs_fops = {
15f57a29 PM	103	.owner = THIS_MODULE,
	104	.open = cache_debugfs_open,
	105	.read = seq_read,
	106	.llseek = seq_lseek,
45dabf14	107	.release = single_release,
15f57a29 PM	108	};
	109
	110	static int __init cache_debugfs_init(void)
	111	{
	112	struct dentry dcache_dentry, icache_dentry;
	113
3f224f4e	114	dcache_dentry = debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
15f57a29 PM	115	(unsigned int *)CACHE_TYPE_DCACHE,
15f57a29 PM	116	&cache_debugfs_fops);
25627c7f Z	117	if (!dcache_dentry)
25627c7f Z	118	return -ENOMEM;
15f57a29	119
3f224f4e	120	icache_dentry = debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
15f57a29 PM	121	(unsigned int *)CACHE_TYPE_ICACHE,
15f57a29 PM	122	&cache_debugfs_fops);
25627c7f Z	123	if (!icache_dentry) {
	124	debugfs_remove(dcache_dentry);
	125	return -ENOMEM;
	126	}
15f57a29 PM	127
	128	return 0;
	129	}
	130	module_init(cache_debugfs_init);
	131
	132	MODULE_LICENSE("GPL v2");