[deliverable/linux.git] / arch / sh / mm / cache.c

/*
 * arch/sh/mm/cache.c
 *
 * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
 * Copyright (C) 2002 - 2010  Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/smp.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void (*local_flush_cache_all)(void *args) = cache_noop;
void (*local_flush_cache_mm)(void *args) = cache_noop;
void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
void (*local_flush_cache_page)(void *args) = cache_noop;
void (*local_flush_cache_range)(void *args) = cache_noop;
void (*local_flush_dcache_page)(void *args) = cache_noop;
void (*local_flush_icache_range)(void *args) = cache_noop;
void (*local_flush_icache_page)(void *args) = cache_noop;
void (*local_flush_cache_sigtramp)(void *args) = cache_noop;

void (*__flush_wback_region)(void *start, int size);
EXPORT_SYMBOL(__flush_wback_region);
void (*__flush_purge_region)(void *start, int size);
EXPORT_SYMBOL(__flush_purge_region);
void (*__flush_invalidate_region)(void *start, int size);
EXPORT_SYMBOL(__flush_invalidate_region);

static inline void noop__flush_region(void *start, int size)
{
}

static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
                                   int wait)
{
	preempt_disable();

	/*
	 * It's possible that this gets called early on when IRQs are
	 * still disabled due to ioremapping by the boot CPU, so don't
	 * even attempt IPIs unless there are other CPUs online.
	 */
	if (num_online_cpus() > 1)
		smp_call_function(func, info, wait);

	func(info);

	preempt_enable();
}

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long vaddr, void *dst, const void *src,
		       unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
	    test_bit(PG_dcache_clean, &page->flags)) {
		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(vto, src, len);
		kunmap_coherent(vto);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			clear_bit(PG_dcache_clean, &page->flags);
	}

	if (vma->vm_flags & VM_EXEC)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
}

void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
			 unsigned long vaddr, void *dst, const void *src,
			 unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
	    test_bit(PG_dcache_clean, &page->flags)) {
		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(dst, vfrom, len);
		kunmap_coherent(vfrom);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			clear_bit(PG_dcache_clean, &page->flags);
	}
}

void copy_user_highpage(struct page *to, struct page *from,
			unsigned long vaddr, struct vm_area_struct *vma)
{
	void *vfrom, *vto;

	vto = kmap_atomic(to);

	if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
	    test_bit(PG_dcache_clean, &from->flags)) {
		vfrom = kmap_coherent(from, vaddr);
		copy_page(vto, vfrom);
		kunmap_coherent(vfrom);
	} else {
		vfrom = kmap_atomic(from);
		copy_page(vto, vfrom);
		kunmap_atomic(vfrom);
	}

	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
	    (vma->vm_flags & VM_EXEC))
		__flush_purge_region(vto, PAGE_SIZE);

	kunmap_atomic(vto);
	/* Make sure this page is cleared on other CPU's too before using it */
	smp_wmb();
}
EXPORT_SYMBOL(copy_user_highpage);

void clear_user_highpage(struct page *page, unsigned long vaddr)
{
	void *kaddr = kmap_atomic(page);

	clear_page(kaddr);

	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
		__flush_purge_region(kaddr, PAGE_SIZE);

	kunmap_atomic(kaddr);
}
EXPORT_SYMBOL(clear_user_highpage);

void __update_cache(struct vm_area_struct *vma,
		    unsigned long address, pte_t pte)
{
	struct page *page;
	unsigned long pfn = pte_pfn(pte);

	if (!boot_cpu_data.dcache.n_aliases)
		return;

	page = pfn_to_page(pfn);
	if (pfn_valid(pfn)) {
		int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
		if (dirty)
			__flush_purge_region(page_address(page), PAGE_SIZE);
	}
}

void __flush_anon_page(struct page *page, unsigned long vmaddr)
{
	unsigned long addr = (unsigned long) page_address(page);

	if (pages_do_alias(addr, vmaddr)) {
		if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
		    test_bit(PG_dcache_clean, &page->flags)) {
			void *kaddr;

			kaddr = kmap_coherent(page, vmaddr);
			/* XXX.. For now kunmap_coherent() does a purge */
			/* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
			kunmap_coherent(kaddr);
		} else
			__flush_purge_region((void *)addr, PAGE_SIZE);
	}
}

void flush_cache_all(void)
{
	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
}
EXPORT_SYMBOL(flush_cache_all);

void flush_cache_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
}

void flush_cache_dup_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
}

void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
		      unsigned long pfn)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = addr;
	data.addr2 = pfn;

	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
}

void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
		       unsigned long end)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_cache_range);

void flush_dcache_page(struct page *page)
{
	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
}
EXPORT_SYMBOL(flush_dcache_page);

void flush_icache_range(unsigned long start, unsigned long end)
{
	struct flusher_data data;

	data.vma = NULL;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_icache_range);

void flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
	/* Nothing uses the VMA, so just pass the struct page along */
	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
}

void flush_cache_sigtramp(unsigned long address)
{
	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
}

static void compute_alias(struct cache_info *c)
{
	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}

static void __init emit_cache_params(void)
{
	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.icache.ways,
		boot_cpu_data.icache.sets,
		boot_cpu_data.icache.way_incr);
	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.icache.entry_mask,
		boot_cpu_data.icache.alias_mask,
		boot_cpu_data.icache.n_aliases);
	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.dcache.ways,
		boot_cpu_data.dcache.sets,
		boot_cpu_data.dcache.way_incr);
	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.dcache.entry_mask,
		boot_cpu_data.dcache.alias_mask,
		boot_cpu_data.dcache.n_aliases);

	/*
	 * Emit Secondary Cache parameters if the CPU has a probed L2.
	 */
	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
		printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
			boot_cpu_data.scache.ways,
			boot_cpu_data.scache.sets,
			boot_cpu_data.scache.way_incr);
		printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
			boot_cpu_data.scache.entry_mask,
			boot_cpu_data.scache.alias_mask,
			boot_cpu_data.scache.n_aliases);
	}
}

void __init cpu_cache_init(void)
{
	unsigned int cache_disabled = 0;

#ifdef SH_CCR
	cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
#endif

	compute_alias(&boot_cpu_data.icache);
	compute_alias(&boot_cpu_data.dcache);
	compute_alias(&boot_cpu_data.scache);

	__flush_wback_region		= noop__flush_region;
	__flush_purge_region		= noop__flush_region;
	__flush_invalidate_region	= noop__flush_region;

	/*
	 * No flushing is necessary in the disabled cache case so we can
	 * just keep the noop functions in local_flush_..() and __flush_..()
	 */
	if (unlikely(cache_disabled))
		goto skip;

	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
		extern void __weak sh2_cache_init(void);

		sh2_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
		extern void __weak sh2a_cache_init(void);

		sh2a_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
		extern void __weak sh3_cache_init(void);

		sh3_cache_init();

		if ((boot_cpu_data.type == CPU_SH7705) &&
		    (boot_cpu_data.dcache.sets == 512)) {
			extern void __weak sh7705_cache_init(void);

			sh7705_cache_init();
		}
	}

	if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
		extern void __weak sh4_cache_init(void);

		sh4_cache_init();

		if ((boot_cpu_data.type == CPU_SH7786) ||
		    (boot_cpu_data.type == CPU_SHX3)) {
			extern void __weak shx3_cache_init(void);

			shx3_cache_init();
		}
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
		extern void __weak sh5_cache_init(void);

		sh5_cache_init();
	}

skip:
	emit_cache_params();
}
Commit	Line	Data
1da177e4	1	/*
f26b2a56	2	* arch/sh/mm/cache.c
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
a6198a23	5	* Copyright (C) 2002 - 2010 Paul Mundt
1da177e4 LT	6	*
	7	* Released under the terms of the GNU GPL v2.0.
	8	*/
1da177e4	9	#include <linux/mm.h>
acca4f4d	10	#include <linux/init.h>
52e27782	11	#include <linux/mutex.h>
e06c4e57	12	#include <linux/fs.h>
f26b2a56	13	#include <linux/smp.h>
7747b9a4 PM	14	#include <linux/highmem.h>
7747b9a4 PM	15	#include <linux/module.h>
1da177e4 LT	16	#include <asm/mmu_context.h>
	17	#include <asm/cacheflush.h>
	18
f26b2a56 PM	19	void (local_flush_cache_all)(void args) = cache_noop;
	20	void (local_flush_cache_mm)(void args) = cache_noop;
	21	void (local_flush_cache_dup_mm)(void args) = cache_noop;
	22	void (local_flush_cache_page)(void args) = cache_noop;
	23	void (local_flush_cache_range)(void args) = cache_noop;
	24	void (local_flush_dcache_page)(void args) = cache_noop;
	25	void (local_flush_icache_range)(void args) = cache_noop;
	26	void (local_flush_icache_page)(void args) = cache_noop;
	27	void (local_flush_cache_sigtramp)(void args) = cache_noop;
	28
37443ef3	29	void (__flush_wback_region)(void start, int size);
0a993b0a	30	EXPORT_SYMBOL(__flush_wback_region);
37443ef3	31	void (__flush_purge_region)(void start, int size);
0a993b0a	32	EXPORT_SYMBOL(__flush_purge_region);
37443ef3	33	void (__flush_invalidate_region)(void start, int size);
0a993b0a	34	EXPORT_SYMBOL(__flush_invalidate_region);
37443ef3	35
37443ef3 PM	36	static inline void noop__flush_region(void *start, int size)
	37	{
	38	}
	39
6f379578 PM	40	static inline void cacheop_on_each_cpu(void (func) (void info), void *info,
	41	int wait)
	42	{
	43	preempt_disable();
a6198a23 PM	44
	45	/*
	46	* It's possible that this gets called early on when IRQs are
	47	* still disabled due to ioremapping by the boot CPU, so don't
	48	* even attempt IPIs unless there are other CPUs online.
	49	*/
	50	if (num_online_cpus() > 1)
	51	smp_call_function(func, info, wait);
	52
6f379578	53	func(info);
a6198a23	54
6f379578 PM	55	preempt_enable();
	56	}
	57
ba1789ef PM	58	void copy_to_user_page(struct vm_area_struct vma, struct page page,
	59	unsigned long vaddr, void dst, const void src,
	60	unsigned long len)
1da177e4	61	{
e1534ae9	62	if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
55661fc1	63	test_bit(PG_dcache_clean, &page->flags)) {
2277ab4a PM	64	void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	65	memcpy(vto, src, len);
0906a3ad	66	kunmap_coherent(vto);
2277ab4a PM	67	} else {
2277ab4a PM	68	memcpy(dst, src, len);
0dfae7d5	69	if (boot_cpu_data.dcache.n_aliases)
55661fc1	70	clear_bit(PG_dcache_clean, &page->flags);
2277ab4a	71	}
ba1789ef PM	72
	73	if (vma->vm_flags & VM_EXEC)
	74	flush_cache_page(vma, vaddr, page_to_pfn(page));
	75	}
	76
	77	void copy_from_user_page(struct vm_area_struct vma, struct page page,
	78	unsigned long vaddr, void dst, const void src,
	79	unsigned long len)
	80	{
e1534ae9	81	if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
55661fc1	82	test_bit(PG_dcache_clean, &page->flags)) {
2277ab4a PM	83	void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	84	memcpy(dst, vfrom, len);
0906a3ad	85	kunmap_coherent(vfrom);
2277ab4a PM	86	} else {
2277ab4a PM	87	memcpy(dst, src, len);
0dfae7d5	88	if (boot_cpu_data.dcache.n_aliases)
55661fc1	89	clear_bit(PG_dcache_clean, &page->flags);
2277ab4a	90	}
1da177e4	91	}
39e688a9	92
7747b9a4 PM	93	void copy_user_highpage(struct page to, struct page from,
	94	unsigned long vaddr, struct vm_area_struct *vma)
	95	{
	96	void vfrom, vto;
	97
bc3e11be	98	vto = kmap_atomic(to);
7747b9a4	99
e1534ae9	100	if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
55661fc1	101	test_bit(PG_dcache_clean, &from->flags)) {
7e01c949	102	vfrom = kmap_coherent(from, vaddr);
2277ab4a	103	copy_page(vto, vfrom);
7e01c949 PM	104	kunmap_coherent(vfrom);
7e01c949 PM	105	} else {
bc3e11be	106	vfrom = kmap_atomic(from);
7e01c949	107	copy_page(vto, vfrom);
bc3e11be	108	kunmap_atomic(vfrom);
7e01c949	109	}
7747b9a4	110
a25bbe12 SM	111	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) \|\|
a25bbe12 SM	112	(vma->vm_flags & VM_EXEC))
7e01c949	113	__flush_purge_region(vto, PAGE_SIZE);
39ac11c1	114
bc3e11be	115	kunmap_atomic(vto);
7747b9a4 PM	116	/* Make sure this page is cleared on other CPU's too before using it */
	117	smp_wmb();
	118	}
	119	EXPORT_SYMBOL(copy_user_highpage);
dfff0fa6 PM	120
	121	void clear_user_highpage(struct page *page, unsigned long vaddr)
	122	{
bc3e11be	123	void *kaddr = kmap_atomic(page);
dfff0fa6	124
7e01c949	125	clear_page(kaddr);
dfff0fa6	126
7e01c949 PM	127	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
7e01c949 PM	128	__flush_purge_region(kaddr, PAGE_SIZE);
dfff0fa6	129
bc3e11be	130	kunmap_atomic(kaddr);
dfff0fa6 PM	131	}
dfff0fa6 PM	132	EXPORT_SYMBOL(clear_user_highpage);
9cef7492 PM	133
	134	void __update_cache(struct vm_area_struct *vma,
	135	unsigned long address, pte_t pte)
	136	{
	137	struct page *page;
	138	unsigned long pfn = pte_pfn(pte);
	139
	140	if (!boot_cpu_data.dcache.n_aliases)
	141	return;
	142
	143	page = pfn_to_page(pfn);
964f7e5a	144	if (pfn_valid(pfn)) {
55661fc1	145	int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
76382b5b MP	146	if (dirty)
76382b5b MP	147	__flush_purge_region(page_address(page), PAGE_SIZE);
9cef7492 PM	148	}
9cef7492 PM	149	}
c0fe478d PM	150
	151	void __flush_anon_page(struct page *page, unsigned long vmaddr)
	152	{
	153	unsigned long addr = (unsigned long) page_address(page);
	154
	155	if (pages_do_alias(addr, vmaddr)) {
e1534ae9	156	if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
55661fc1	157	test_bit(PG_dcache_clean, &page->flags)) {
c0fe478d PM	158	void *kaddr;
	159
	160	kaddr = kmap_coherent(page, vmaddr);
6e4154d4 PM	161	/* XXX.. For now kunmap_coherent() does a purge */
6e4154d4 PM	162	/* __flush_purge_region((void )kaddr, PAGE_SIZE); /
0906a3ad	163	kunmap_coherent(kaddr);
c0fe478d	164	} else
6e4154d4	165	__flush_purge_region((void *)addr, PAGE_SIZE);
c0fe478d PM	166	}
c0fe478d PM	167	}
ecba1060	168
f26b2a56 PM	169	void flush_cache_all(void)
f26b2a56 PM	170	{
6f379578	171	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
f26b2a56	172	}
0a993b0a	173	EXPORT_SYMBOL(flush_cache_all);
f26b2a56 PM	174
	175	void flush_cache_mm(struct mm_struct *mm)
	176	{
654d364e PM	177	if (boot_cpu_data.dcache.n_aliases == 0)
	178	return;
	179
6f379578	180	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
f26b2a56 PM	181	}
	182
	183	void flush_cache_dup_mm(struct mm_struct *mm)
	184	{
654d364e PM	185	if (boot_cpu_data.dcache.n_aliases == 0)
	186	return;
	187
6f379578	188	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
f26b2a56 PM	189	}
	190
	191	void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
	192	unsigned long pfn)
	193	{
	194	struct flusher_data data;
	195
	196	data.vma = vma;
	197	data.addr1 = addr;
	198	data.addr2 = pfn;
	199
6f379578	200	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
f26b2a56 PM	201	}
	202
	203	void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
	204	unsigned long end)
	205	{
	206	struct flusher_data data;
	207
	208	data.vma = vma;
	209	data.addr1 = start;
	210	data.addr2 = end;
	211
6f379578	212	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
f26b2a56	213	}
0a993b0a	214	EXPORT_SYMBOL(flush_cache_range);
f26b2a56 PM	215
	216	void flush_dcache_page(struct page *page)
	217	{
6f379578	218	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
f26b2a56	219	}
0a993b0a	220	EXPORT_SYMBOL(flush_dcache_page);
f26b2a56 PM	221
	222	void flush_icache_range(unsigned long start, unsigned long end)
	223	{
	224	struct flusher_data data;
	225
	226	data.vma = NULL;
	227	data.addr1 = start;
	228	data.addr2 = end;
	229
6f379578	230	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
f26b2a56	231	}
e3560305	232	EXPORT_SYMBOL(flush_icache_range);
f26b2a56 PM	233
	234	void flush_icache_page(struct vm_area_struct vma, struct page page)
	235	{
	236	/* Nothing uses the VMA, so just pass the struct page along */
6f379578	237	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
f26b2a56 PM	238	}
	239
	240	void flush_cache_sigtramp(unsigned long address)
	241	{
6f379578	242	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
f26b2a56 PM	243	}
f26b2a56 PM	244
27d59ec1 PM	245	static void compute_alias(struct cache_info *c)
	246	{
	247	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	248	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
	249	}
	250
	251	static void __init emit_cache_params(void)
	252	{
	253	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	254	boot_cpu_data.icache.ways,
	255	boot_cpu_data.icache.sets,
	256	boot_cpu_data.icache.way_incr);
	257	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	258	boot_cpu_data.icache.entry_mask,
	259	boot_cpu_data.icache.alias_mask,
	260	boot_cpu_data.icache.n_aliases);
	261	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	262	boot_cpu_data.dcache.ways,
	263	boot_cpu_data.dcache.sets,
	264	boot_cpu_data.dcache.way_incr);
	265	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	266	boot_cpu_data.dcache.entry_mask,
	267	boot_cpu_data.dcache.alias_mask,
	268	boot_cpu_data.dcache.n_aliases);
	269
	270	/*
	271	* Emit Secondary Cache parameters if the CPU has a probed L2.
	272	*/
	273	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
	274	printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	275	boot_cpu_data.scache.ways,
	276	boot_cpu_data.scache.sets,
	277	boot_cpu_data.scache.way_incr);
	278	printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	279	boot_cpu_data.scache.entry_mask,
	280	boot_cpu_data.scache.alias_mask,
	281	boot_cpu_data.scache.n_aliases);
	282	}
	283	}
	284
ecba1060 PM	285	void __init cpu_cache_init(void)
ecba1060 PM	286	{
3af539e5 PM	287	unsigned int cache_disabled = 0;
3af539e5 PM	288
a5f6ea29 GU	289	#ifdef SH_CCR
a5f6ea29 GU	290	cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
3af539e5	291	#endif
5fb80ae8	292
27d59ec1 PM	293	compute_alias(&boot_cpu_data.icache);
	294	compute_alias(&boot_cpu_data.dcache);
	295	compute_alias(&boot_cpu_data.scache);
	296
37443ef3 PM	297	__flush_wback_region = noop__flush_region;
	298	__flush_purge_region = noop__flush_region;
	299	__flush_invalidate_region = noop__flush_region;
	300
5fb80ae8 MD	301	/*
	302	* No flushing is necessary in the disabled cache case so we can
	303	* just keep the noop functions in local_flush_..() and __flush_..()
	304	*/
	305	if (unlikely(cache_disabled))
	306	goto skip;
	307
109b44a8 PM	308	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
	309	extern void __weak sh2_cache_init(void);
	310
	311	sh2_cache_init();
	312	}
	313
a58e1a2a PM	314	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
	315	extern void __weak sh2a_cache_init(void);
	316
	317	sh2a_cache_init();
	318	}
	319
79f1c9da PM	320	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
	321	extern void __weak sh3_cache_init(void);
	322
	323	sh3_cache_init();
0d051d90 PM	324
	325	if ((boot_cpu_data.type == CPU_SH7705) &&
	326	(boot_cpu_data.dcache.sets == 512)) {
	327	extern void __weak sh7705_cache_init(void);
	328
	329	sh7705_cache_init();
	330	}
79f1c9da PM	331	}
79f1c9da PM	332
ecba1060 PM	333	if ((boot_cpu_data.family == CPU_FAMILY_SH4) \|\|
	334	(boot_cpu_data.family == CPU_FAMILY_SH4A) \|\|
	335	(boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
	336	extern void __weak sh4_cache_init(void);
	337
	338	sh4_cache_init();
3cf6fa1e PM	339
	340	if ((boot_cpu_data.type == CPU_SH7786) \|\|
	341	(boot_cpu_data.type == CPU_SHX3)) {
	342	extern void __weak shx3_cache_init(void);
	343
	344	shx3_cache_init();
	345	}
ecba1060	346	}
27d59ec1	347
2b431518 PM	348	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
	349	extern void __weak sh5_cache_init(void);
	350
	351	sh5_cache_init();
	352	}
	353
5fb80ae8	354	skip:
27d59ec1	355	emit_cache_params();
ecba1060	356	}