[deliverable/linux.git] / arch / sh / mm / cache.c

/*
 * arch/sh/mm/cache.c
 *
 * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
 * Copyright (C) 2002 - 2009  Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/smp.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void (*local_flush_cache_all)(void *args) = cache_noop;
void (*local_flush_cache_mm)(void *args) = cache_noop;
void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
void (*local_flush_cache_page)(void *args) = cache_noop;
void (*local_flush_cache_range)(void *args) = cache_noop;
void (*local_flush_dcache_page)(void *args) = cache_noop;
void (*local_flush_icache_range)(void *args) = cache_noop;
void (*local_flush_icache_page)(void *args) = cache_noop;
void (*local_flush_cache_sigtramp)(void *args) = cache_noop;

void (*__flush_wback_region)(void *start, int size);
EXPORT_SYMBOL(__flush_wback_region);
void (*__flush_purge_region)(void *start, int size);
EXPORT_SYMBOL(__flush_purge_region);
void (*__flush_invalidate_region)(void *start, int size);
EXPORT_SYMBOL(__flush_invalidate_region);

static inline void noop__flush_region(void *start, int size)
{
}

static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
                                   int wait)
{
	preempt_disable();
	smp_call_function(func, info, wait);
	func(info);
	preempt_enable();
}

/*
 * copy_to_user_page
 * @vma: vm_area_struct holding the pages
 * @page: struct page
 * @vaddr: user space address
 * @dst: address of page in kernel space (possibly from kmap)
 * @src: source address in kernel logical memory
 * @len: length of data in bytes (may be less than PAGE_SIZE)
 *
 * Copy data into the address space of a process other than the current
 * process (eg for ptrace).
 */
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long vaddr, void *dst, const void *src,
		       unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	    !test_bit(PG_dcache_dirty, &page->flags)) {
		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(vto, src, len);
		kunmap_coherent(vto);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			set_bit(PG_dcache_dirty, &page->flags);
	}

	if (vma->vm_flags & VM_EXEC)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
}

void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
			 unsigned long vaddr, void *dst, const void *src,
			 unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	    !test_bit(PG_dcache_dirty, &page->flags)) {
		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(dst, vfrom, len);
		kunmap_coherent(vfrom);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			set_bit(PG_dcache_dirty, &page->flags);
	}
}

/*
 * copy_user_highpage
 * @to: destination page
 * @from: source page
 * @vaddr: address of pages in user address space
 * @vma: vm_area_struct holding the pages
 *
 * This is used in COW implementation to copy data from page @from to
 * page @to. @from was previousl mapped at @vaddr, and @to will be.
 * As this is used only in the COW implementation, this means that the
 * source is unmodified, and so we don't have to worry about cache
 * aliasing on that side.
 */
#ifdef CONFIG_HIGHMEM
/*
 * If we ever have a real highmem system, this code will need fixing
 * (as will clear_user/clear_user_highmem), because the kmap potentitally
 * creates another alias risk.
 */
#error This code is broken with real HIGHMEM
#endif
void copy_user_highpage(struct page *to, struct page *from,
			unsigned long vaddr, struct vm_area_struct *vma)
{
	void *vfrom, *vto;

	vto = kmap_atomic(to, KM_USER1);
	vfrom = kmap_atomic(from, KM_USER0);

	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
		__flush_invalidate_region(vto, PAGE_SIZE);

	if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
	    !test_bit(PG_dcache_dirty, &from->flags)) {
		void *vto_coloured = kmap_coherent(to, vaddr);
		copy_page(vto_coloured, vfrom);
		kunmap_coherent(vto_coloured);
	} else
		copy_page(vto, vfrom);

	kunmap_atomic(vfrom, KM_USER0);
	kunmap_atomic(vto, KM_USER1);

	/* Make sure this page is cleared on other CPU's too before using it */
	smp_wmb();
}
EXPORT_SYMBOL(copy_user_highpage);

void clear_user_highpage(struct page *page, unsigned long vaddr)
{
	void *kaddr = kmap_atomic(page, KM_USER0);

	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK)) {
		void *vto;

		/* Kernel alias may have modified data in the cache. */
		__flush_invalidate_region(kaddr, PAGE_SIZE);

		vto = kmap_coherent(page, vaddr);
		clear_page(vto);
		kunmap_coherent(vto);
	} else
		clear_page(kaddr);

	kunmap_atomic(kaddr, KM_USER0);
}
EXPORT_SYMBOL(clear_user_highpage);

void __update_cache(struct vm_area_struct *vma,
		    unsigned long address, pte_t pte)
{
	struct page *page;
	unsigned long pfn = pte_pfn(pte);

	if (!boot_cpu_data.dcache.n_aliases)
		return;

	page = pfn_to_page(pfn);
	if (pfn_valid(pfn)) {
		int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
		if (dirty) {
			unsigned long addr = (unsigned long)page_address(page);

			if (pages_do_alias(addr, address & PAGE_MASK))
				__flush_purge_region((void *)addr, PAGE_SIZE);
		}
	}
}

void __flush_anon_page(struct page *page, unsigned long vmaddr)
{
	unsigned long addr = (unsigned long) page_address(page);

	if (pages_do_alias(addr, vmaddr)) {
		if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
		    !test_bit(PG_dcache_dirty, &page->flags)) {
			void *kaddr;

			kaddr = kmap_coherent(page, vmaddr);
			/* XXX.. For now kunmap_coherent() does a purge */
			/* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
			kunmap_coherent(kaddr);
		} else
			__flush_purge_region((void *)addr, PAGE_SIZE);
	}
}

void flush_cache_all(void)
{
	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
}
EXPORT_SYMBOL(flush_cache_all);

void flush_cache_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
}

void flush_cache_dup_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
}

void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
		      unsigned long pfn)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = addr;
	data.addr2 = pfn;

	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
}

void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
		       unsigned long end)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_cache_range);

void flush_dcache_page(struct page *page)
{
	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
}
EXPORT_SYMBOL(flush_dcache_page);

void flush_icache_range(unsigned long start, unsigned long end)
{
	struct flusher_data data;

	data.vma = NULL;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
}

void flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
	/* Nothing uses the VMA, so just pass the struct page along */
	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
}

void flush_cache_sigtramp(unsigned long address)
{
	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
}

static void compute_alias(struct cache_info *c)
{
	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}

static void __init emit_cache_params(void)
{
	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.icache.ways,
		boot_cpu_data.icache.sets,
		boot_cpu_data.icache.way_incr);
	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.icache.entry_mask,
		boot_cpu_data.icache.alias_mask,
		boot_cpu_data.icache.n_aliases);
	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.dcache.ways,
		boot_cpu_data.dcache.sets,
		boot_cpu_data.dcache.way_incr);
	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.dcache.entry_mask,
		boot_cpu_data.dcache.alias_mask,
		boot_cpu_data.dcache.n_aliases);

	/*
	 * Emit Secondary Cache parameters if the CPU has a probed L2.
	 */
	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
		printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
			boot_cpu_data.scache.ways,
			boot_cpu_data.scache.sets,
			boot_cpu_data.scache.way_incr);
		printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
			boot_cpu_data.scache.entry_mask,
			boot_cpu_data.scache.alias_mask,
			boot_cpu_data.scache.n_aliases);
	}
}

void __init cpu_cache_init(void)
{
	unsigned int cache_disabled = 0;

#ifdef CCR
	cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
#endif

	compute_alias(&boot_cpu_data.icache);
	compute_alias(&boot_cpu_data.dcache);
	compute_alias(&boot_cpu_data.scache);

	__flush_wback_region		= noop__flush_region;
	__flush_purge_region		= noop__flush_region;
	__flush_invalidate_region	= noop__flush_region;

	/*
	 * No flushing is necessary in the disabled cache case so we can
	 * just keep the noop functions in local_flush_..() and __flush_..()
	 */
	if (unlikely(cache_disabled))
		goto skip;

	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
		extern void __weak sh2_cache_init(void);

		sh2_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
		extern void __weak sh2a_cache_init(void);

		sh2a_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
		extern void __weak sh3_cache_init(void);

		sh3_cache_init();

		if ((boot_cpu_data.type == CPU_SH7705) &&
		    (boot_cpu_data.dcache.sets == 512)) {
			extern void __weak sh7705_cache_init(void);

			sh7705_cache_init();
		}
	}

	if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
		extern void __weak sh4_cache_init(void);

		sh4_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
		extern void __weak sh5_cache_init(void);

		sh5_cache_init();
	}

skip:
	emit_cache_params();
}
Commit	Line	Data
1da177e4	1	/*
f26b2a56	2	* arch/sh/mm/cache.c
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
dfff0fa6	5	* Copyright (C) 2002 - 2009 Paul Mundt
1da177e4 LT	6	*
	7	* Released under the terms of the GNU GPL v2.0.
	8	*/
1da177e4	9	#include <linux/mm.h>
acca4f4d	10	#include <linux/init.h>
52e27782	11	#include <linux/mutex.h>
e06c4e57	12	#include <linux/fs.h>
f26b2a56	13	#include <linux/smp.h>
7747b9a4 PM	14	#include <linux/highmem.h>
7747b9a4 PM	15	#include <linux/module.h>
1da177e4 LT	16	#include <asm/mmu_context.h>
	17	#include <asm/cacheflush.h>
	18
f26b2a56 PM	19	void (local_flush_cache_all)(void args) = cache_noop;
	20	void (local_flush_cache_mm)(void args) = cache_noop;
	21	void (local_flush_cache_dup_mm)(void args) = cache_noop;
	22	void (local_flush_cache_page)(void args) = cache_noop;
	23	void (local_flush_cache_range)(void args) = cache_noop;
	24	void (local_flush_dcache_page)(void args) = cache_noop;
	25	void (local_flush_icache_range)(void args) = cache_noop;
	26	void (local_flush_icache_page)(void args) = cache_noop;
	27	void (local_flush_cache_sigtramp)(void args) = cache_noop;
	28
37443ef3	29	void (__flush_wback_region)(void start, int size);
0a993b0a	30	EXPORT_SYMBOL(__flush_wback_region);
37443ef3	31	void (__flush_purge_region)(void start, int size);
0a993b0a	32	EXPORT_SYMBOL(__flush_purge_region);
37443ef3	33	void (__flush_invalidate_region)(void start, int size);
0a993b0a	34	EXPORT_SYMBOL(__flush_invalidate_region);
37443ef3	35
37443ef3 PM	36	static inline void noop__flush_region(void *start, int size)
	37	{
	38	}
	39
6f379578 PM	40	static inline void cacheop_on_each_cpu(void (func) (void info), void *info,
	41	int wait)
	42	{
	43	preempt_disable();
	44	smp_call_function(func, info, wait);
	45	func(info);
	46	preempt_enable();
	47	}
	48
39ac11c1 SM	49	/*
	50	* copy_to_user_page
	51	* @vma: vm_area_struct holding the pages
	52	* @page: struct page
	53	* @vaddr: user space address
	54	* @dst: address of page in kernel space (possibly from kmap)
	55	* @src: source address in kernel logical memory
	56	* @len: length of data in bytes (may be less than PAGE_SIZE)
	57	*
	58	* Copy data into the address space of a process other than the current
	59	* process (eg for ptrace).
	60	*/
ba1789ef PM	61	void copy_to_user_page(struct vm_area_struct vma, struct page page,
	62	unsigned long vaddr, void dst, const void src,
	63	unsigned long len)
1da177e4	64	{
0dfae7d5 PM	65	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
0dfae7d5 PM	66	!test_bit(PG_dcache_dirty, &page->flags)) {
2277ab4a PM	67	void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	68	memcpy(vto, src, len);
0906a3ad	69	kunmap_coherent(vto);
2277ab4a PM	70	} else {
2277ab4a PM	71	memcpy(dst, src, len);
0dfae7d5 PM	72	if (boot_cpu_data.dcache.n_aliases)
0dfae7d5 PM	73	set_bit(PG_dcache_dirty, &page->flags);
2277ab4a	74	}
ba1789ef PM	75
	76	if (vma->vm_flags & VM_EXEC)
	77	flush_cache_page(vma, vaddr, page_to_pfn(page));
	78	}
	79
	80	void copy_from_user_page(struct vm_area_struct vma, struct page page,
	81	unsigned long vaddr, void dst, const void src,
	82	unsigned long len)
	83	{
0dfae7d5 PM	84	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
0dfae7d5 PM	85	!test_bit(PG_dcache_dirty, &page->flags)) {
2277ab4a PM	86	void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	87	memcpy(dst, vfrom, len);
0906a3ad	88	kunmap_coherent(vfrom);
2277ab4a PM	89	} else {
2277ab4a PM	90	memcpy(dst, src, len);
0dfae7d5 PM	91	if (boot_cpu_data.dcache.n_aliases)
0dfae7d5 PM	92	set_bit(PG_dcache_dirty, &page->flags);
2277ab4a	93	}
1da177e4	94	}
39e688a9	95
39ac11c1 SM	96	/*
	97	* copy_user_highpage
	98	* @to: destination page
	99	* @from: source page
	100	* @vaddr: address of pages in user address space
	101	* @vma: vm_area_struct holding the pages
	102	*
	103	* This is used in COW implementation to copy data from page @from to
	104	* page @to. @from was previousl mapped at @vaddr, and @to will be.
	105	* As this is used only in the COW implementation, this means that the
	106	* source is unmodified, and so we don't have to worry about cache
	107	* aliasing on that side.
	108	*/
	109	#ifdef CONFIG_HIGHMEM
	110	/*
	111	* If we ever have a real highmem system, this code will need fixing
	112	* (as will clear_user/clear_user_highmem), because the kmap potentitally
	113	* creates another alias risk.
	114	*/
	115	#error This code is broken with real HIGHMEM
	116	#endif
7747b9a4 PM	117	void copy_user_highpage(struct page to, struct page from,
	118	unsigned long vaddr, struct vm_area_struct *vma)
	119	{
	120	void vfrom, vto;
	121
7747b9a4	122	vto = kmap_atomic(to, KM_USER1);
39ac11c1 SM	123	vfrom = kmap_atomic(from, KM_USER0);
	124
	125	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
	126	__flush_invalidate_region(vto, PAGE_SIZE);
7747b9a4	127
0dfae7d5 PM	128	if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
0dfae7d5 PM	129	!test_bit(PG_dcache_dirty, &from->flags)) {
39ac11c1 SM	130	void *vto_coloured = kmap_coherent(to, vaddr);
	131	copy_page(vto_coloured, vfrom);
	132	kunmap_coherent(vto_coloured);
	133	} else
2277ab4a	134	copy_page(vto, vfrom);
7747b9a4	135
39ac11c1	136	kunmap_atomic(vfrom, KM_USER0);
7747b9a4	137	kunmap_atomic(vto, KM_USER1);
39ac11c1	138
7747b9a4 PM	139	/* Make sure this page is cleared on other CPU's too before using it */
	140	smp_wmb();
	141	}
	142	EXPORT_SYMBOL(copy_user_highpage);
dfff0fa6 PM	143
	144	void clear_user_highpage(struct page *page, unsigned long vaddr)
	145	{
	146	void *kaddr = kmap_atomic(page, KM_USER0);
	147
39ac11c1 SM	148	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK)) {
39ac11c1 SM	149	void *vto;
dfff0fa6	150
39ac11c1 SM	151	/* Kernel alias may have modified data in the cache. */
	152	__flush_invalidate_region(kaddr, PAGE_SIZE);
	153
	154	vto = kmap_coherent(page, vaddr);
	155	clear_page(vto);
	156	kunmap_coherent(vto);
	157	} else
	158	clear_page(kaddr);
dfff0fa6 PM	159
	160	kunmap_atomic(kaddr, KM_USER0);
	161	}
	162	EXPORT_SYMBOL(clear_user_highpage);
9cef7492 PM	163
	164	void __update_cache(struct vm_area_struct *vma,
	165	unsigned long address, pte_t pte)
	166	{
	167	struct page *page;
	168	unsigned long pfn = pte_pfn(pte);
	169
	170	if (!boot_cpu_data.dcache.n_aliases)
	171	return;
	172
	173	page = pfn_to_page(pfn);
964f7e5a	174	if (pfn_valid(pfn)) {
9cef7492 PM	175	int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
	176	if (dirty) {
	177	unsigned long addr = (unsigned long)page_address(page);
	178
	179	if (pages_do_alias(addr, address & PAGE_MASK))
6e4154d4	180	__flush_purge_region((void *)addr, PAGE_SIZE);
9cef7492 PM	181	}
	182	}
	183	}
c0fe478d PM	184
	185	void __flush_anon_page(struct page *page, unsigned long vmaddr)
	186	{
	187	unsigned long addr = (unsigned long) page_address(page);
	188
	189	if (pages_do_alias(addr, vmaddr)) {
	190	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	191	!test_bit(PG_dcache_dirty, &page->flags)) {
	192	void *kaddr;
	193
	194	kaddr = kmap_coherent(page, vmaddr);
6e4154d4 PM	195	/* XXX.. For now kunmap_coherent() does a purge */
6e4154d4 PM	196	/* __flush_purge_region((void )kaddr, PAGE_SIZE); /
0906a3ad	197	kunmap_coherent(kaddr);
c0fe478d	198	} else
6e4154d4	199	__flush_purge_region((void *)addr, PAGE_SIZE);
c0fe478d PM	200	}
c0fe478d PM	201	}
ecba1060	202
f26b2a56 PM	203	void flush_cache_all(void)
f26b2a56 PM	204	{
6f379578	205	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
f26b2a56	206	}
0a993b0a	207	EXPORT_SYMBOL(flush_cache_all);
f26b2a56 PM	208
	209	void flush_cache_mm(struct mm_struct *mm)
	210	{
654d364e PM	211	if (boot_cpu_data.dcache.n_aliases == 0)
	212	return;
	213
6f379578	214	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
f26b2a56 PM	215	}
	216
	217	void flush_cache_dup_mm(struct mm_struct *mm)
	218	{
654d364e PM	219	if (boot_cpu_data.dcache.n_aliases == 0)
	220	return;
	221
6f379578	222	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
f26b2a56 PM	223	}
	224
	225	void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
	226	unsigned long pfn)
	227	{
	228	struct flusher_data data;
	229
	230	data.vma = vma;
	231	data.addr1 = addr;
	232	data.addr2 = pfn;
	233
6f379578	234	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
f26b2a56 PM	235	}
	236
	237	void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
	238	unsigned long end)
	239	{
	240	struct flusher_data data;
	241
	242	data.vma = vma;
	243	data.addr1 = start;
	244	data.addr2 = end;
	245
6f379578	246	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
f26b2a56	247	}
0a993b0a	248	EXPORT_SYMBOL(flush_cache_range);
f26b2a56 PM	249
	250	void flush_dcache_page(struct page *page)
	251	{
6f379578	252	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
f26b2a56	253	}
0a993b0a	254	EXPORT_SYMBOL(flush_dcache_page);
f26b2a56 PM	255
	256	void flush_icache_range(unsigned long start, unsigned long end)
	257	{
	258	struct flusher_data data;
	259
	260	data.vma = NULL;
	261	data.addr1 = start;
	262	data.addr2 = end;
	263
6f379578	264	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
f26b2a56 PM	265	}
	266
	267	void flush_icache_page(struct vm_area_struct vma, struct page page)
	268	{
	269	/* Nothing uses the VMA, so just pass the struct page along */
6f379578	270	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
f26b2a56 PM	271	}
	272
	273	void flush_cache_sigtramp(unsigned long address)
	274	{
6f379578	275	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
f26b2a56 PM	276	}
f26b2a56 PM	277
27d59ec1 PM	278	static void compute_alias(struct cache_info *c)
	279	{
	280	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	281	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
	282	}
	283
	284	static void __init emit_cache_params(void)
	285	{
	286	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	287	boot_cpu_data.icache.ways,
	288	boot_cpu_data.icache.sets,
	289	boot_cpu_data.icache.way_incr);
	290	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	291	boot_cpu_data.icache.entry_mask,
	292	boot_cpu_data.icache.alias_mask,
	293	boot_cpu_data.icache.n_aliases);
	294	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	295	boot_cpu_data.dcache.ways,
	296	boot_cpu_data.dcache.sets,
	297	boot_cpu_data.dcache.way_incr);
	298	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	299	boot_cpu_data.dcache.entry_mask,
	300	boot_cpu_data.dcache.alias_mask,
	301	boot_cpu_data.dcache.n_aliases);
	302
	303	/*
	304	* Emit Secondary Cache parameters if the CPU has a probed L2.
	305	*/
	306	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
	307	printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	308	boot_cpu_data.scache.ways,
	309	boot_cpu_data.scache.sets,
	310	boot_cpu_data.scache.way_incr);
	311	printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	312	boot_cpu_data.scache.entry_mask,
	313	boot_cpu_data.scache.alias_mask,
	314	boot_cpu_data.scache.n_aliases);
	315	}
	316	}
	317
ecba1060 PM	318	void __init cpu_cache_init(void)
ecba1060 PM	319	{
3af539e5 PM	320	unsigned int cache_disabled = 0;
	321
	322	#ifdef CCR
	323	cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
	324	#endif
5fb80ae8	325
27d59ec1 PM	326	compute_alias(&boot_cpu_data.icache);
	327	compute_alias(&boot_cpu_data.dcache);
	328	compute_alias(&boot_cpu_data.scache);
	329
37443ef3 PM	330	__flush_wback_region = noop__flush_region;
	331	__flush_purge_region = noop__flush_region;
	332	__flush_invalidate_region = noop__flush_region;
	333
5fb80ae8 MD	334	/*
	335	* No flushing is necessary in the disabled cache case so we can
	336	* just keep the noop functions in local_flush_..() and __flush_..()
	337	*/
	338	if (unlikely(cache_disabled))
	339	goto skip;
	340
109b44a8 PM	341	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
	342	extern void __weak sh2_cache_init(void);
	343
	344	sh2_cache_init();
	345	}
	346
a58e1a2a PM	347	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
	348	extern void __weak sh2a_cache_init(void);
	349
	350	sh2a_cache_init();
	351	}
	352
79f1c9da PM	353	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
	354	extern void __weak sh3_cache_init(void);
	355
	356	sh3_cache_init();
0d051d90 PM	357
	358	if ((boot_cpu_data.type == CPU_SH7705) &&
	359	(boot_cpu_data.dcache.sets == 512)) {
	360	extern void __weak sh7705_cache_init(void);
	361
	362	sh7705_cache_init();
	363	}
79f1c9da PM	364	}
79f1c9da PM	365
ecba1060 PM	366	if ((boot_cpu_data.family == CPU_FAMILY_SH4) \|\|
	367	(boot_cpu_data.family == CPU_FAMILY_SH4A) \|\|
	368	(boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
	369	extern void __weak sh4_cache_init(void);
	370
	371	sh4_cache_init();
	372	}
27d59ec1	373
2b431518 PM	374	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
	375	extern void __weak sh5_cache_init(void);
	376
	377	sh5_cache_init();
	378	}
	379
5fb80ae8	380	skip:
27d59ec1	381	emit_cache_params();
ecba1060	382	}