[deliverable/linux.git] / arch / sh / mm / cache.c

/*
 * arch/sh/mm/cache.c
 *
 * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
 * Copyright (C) 2002 - 2010  Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/smp.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void (*local_flush_cache_all)(void *args) = cache_noop;
void (*local_flush_cache_mm)(void *args) = cache_noop;
void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
void (*local_flush_cache_page)(void *args) = cache_noop;
void (*local_flush_cache_range)(void *args) = cache_noop;
void (*local_flush_dcache_page)(void *args) = cache_noop;
void (*local_flush_icache_range)(void *args) = cache_noop;
void (*local_flush_icache_page)(void *args) = cache_noop;
void (*local_flush_cache_sigtramp)(void *args) = cache_noop;

void (*__flush_wback_region)(void *start, int size);
EXPORT_SYMBOL(__flush_wback_region);
void (*__flush_purge_region)(void *start, int size);
EXPORT_SYMBOL(__flush_purge_region);
void (*__flush_invalidate_region)(void *start, int size);
EXPORT_SYMBOL(__flush_invalidate_region);

static inline void noop__flush_region(void *start, int size)
{
}

static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
                                   int wait)
{
	preempt_disable();

	/*
	 * It's possible that this gets called early on when IRQs are
	 * still disabled due to ioremapping by the boot CPU, so don't
	 * even attempt IPIs unless there are other CPUs online.
	 */
	if (num_online_cpus() > 1)
		smp_call_function(func, info, wait);

	func(info);

	preempt_enable();
}

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long vaddr, void *dst, const void *src,
		       unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	    !test_bit(PG_dcache_dirty, &page->flags)) {
		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(vto, src, len);
		kunmap_coherent(vto);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			set_bit(PG_dcache_dirty, &page->flags);
	}

	if (vma->vm_flags & VM_EXEC)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
}

void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
			 unsigned long vaddr, void *dst, const void *src,
			 unsigned long len)
{
	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	    !test_bit(PG_dcache_dirty, &page->flags)) {
		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(dst, vfrom, len);
		kunmap_coherent(vfrom);
	} else {
		memcpy(dst, src, len);
		if (boot_cpu_data.dcache.n_aliases)
			set_bit(PG_dcache_dirty, &page->flags);
	}
}

void copy_user_highpage(struct page *to, struct page *from,
			unsigned long vaddr, struct vm_area_struct *vma)
{
	void *vfrom, *vto;

	vto = kmap_atomic(to, KM_USER1);

	if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
	    !test_bit(PG_dcache_dirty, &from->flags)) {
		vfrom = kmap_coherent(from, vaddr);
		copy_page(vto, vfrom);
		kunmap_coherent(vfrom);
	} else {
		vfrom = kmap_atomic(from, KM_USER0);
		copy_page(vto, vfrom);
		kunmap_atomic(vfrom, KM_USER0);
	}

	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
		__flush_purge_region(vto, PAGE_SIZE);

	kunmap_atomic(vto, KM_USER1);
	/* Make sure this page is cleared on other CPU's too before using it */
	smp_wmb();
}
EXPORT_SYMBOL(copy_user_highpage);

void clear_user_highpage(struct page *page, unsigned long vaddr)
{
	void *kaddr = kmap_atomic(page, KM_USER0);

	clear_page(kaddr);

	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
		__flush_purge_region(kaddr, PAGE_SIZE);

	kunmap_atomic(kaddr, KM_USER0);
}
EXPORT_SYMBOL(clear_user_highpage);

void __update_cache(struct vm_area_struct *vma,
		    unsigned long address, pte_t pte)
{
	struct page *page;
	unsigned long pfn = pte_pfn(pte);

	if (!boot_cpu_data.dcache.n_aliases)
		return;

	page = pfn_to_page(pfn);
	if (pfn_valid(pfn)) {
		int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
		if (dirty)
			__flush_purge_region(page_address(page), PAGE_SIZE);
	}
}

void __flush_anon_page(struct page *page, unsigned long vmaddr)
{
	unsigned long addr = (unsigned long) page_address(page);

	if (pages_do_alias(addr, vmaddr)) {
		if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
		    !test_bit(PG_dcache_dirty, &page->flags)) {
			void *kaddr;

			kaddr = kmap_coherent(page, vmaddr);
			/* XXX.. For now kunmap_coherent() does a purge */
			/* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
			kunmap_coherent(kaddr);
		} else
			__flush_purge_region((void *)addr, PAGE_SIZE);
	}
}

void flush_cache_all(void)
{
	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
}
EXPORT_SYMBOL(flush_cache_all);

void flush_cache_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
}

void flush_cache_dup_mm(struct mm_struct *mm)
{
	if (boot_cpu_data.dcache.n_aliases == 0)
		return;

	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
}

void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
		      unsigned long pfn)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = addr;
	data.addr2 = pfn;

	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
}

void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
		       unsigned long end)
{
	struct flusher_data data;

	data.vma = vma;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_cache_range);

void flush_dcache_page(struct page *page)
{
	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
}
EXPORT_SYMBOL(flush_dcache_page);

void flush_icache_range(unsigned long start, unsigned long end)
{
	struct flusher_data data;

	data.vma = NULL;
	data.addr1 = start;
	data.addr2 = end;

	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
}

void flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
	/* Nothing uses the VMA, so just pass the struct page along */
	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
}

void flush_cache_sigtramp(unsigned long address)
{
	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
}

static void compute_alias(struct cache_info *c)
{
	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}

static void __init emit_cache_params(void)
{
	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.icache.ways,
		boot_cpu_data.icache.sets,
		boot_cpu_data.icache.way_incr);
	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.icache.entry_mask,
		boot_cpu_data.icache.alias_mask,
		boot_cpu_data.icache.n_aliases);
	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
		boot_cpu_data.dcache.ways,
		boot_cpu_data.dcache.sets,
		boot_cpu_data.dcache.way_incr);
	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
		boot_cpu_data.dcache.entry_mask,
		boot_cpu_data.dcache.alias_mask,
		boot_cpu_data.dcache.n_aliases);

	/*
	 * Emit Secondary Cache parameters if the CPU has a probed L2.
	 */
	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
		printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
			boot_cpu_data.scache.ways,
			boot_cpu_data.scache.sets,
			boot_cpu_data.scache.way_incr);
		printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
			boot_cpu_data.scache.entry_mask,
			boot_cpu_data.scache.alias_mask,
			boot_cpu_data.scache.n_aliases);
	}
}

void __init cpu_cache_init(void)
{
	unsigned int cache_disabled = 0;

#ifdef CCR
	cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
#endif

	compute_alias(&boot_cpu_data.icache);
	compute_alias(&boot_cpu_data.dcache);
	compute_alias(&boot_cpu_data.scache);

	__flush_wback_region		= noop__flush_region;
	__flush_purge_region		= noop__flush_region;
	__flush_invalidate_region	= noop__flush_region;

	/*
	 * No flushing is necessary in the disabled cache case so we can
	 * just keep the noop functions in local_flush_..() and __flush_..()
	 */
	if (unlikely(cache_disabled))
		goto skip;

	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
		extern void __weak sh2_cache_init(void);

		sh2_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
		extern void __weak sh2a_cache_init(void);

		sh2a_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
		extern void __weak sh3_cache_init(void);

		sh3_cache_init();

		if ((boot_cpu_data.type == CPU_SH7705) &&
		    (boot_cpu_data.dcache.sets == 512)) {
			extern void __weak sh7705_cache_init(void);

			sh7705_cache_init();
		}
	}

	if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
	    (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
		extern void __weak sh4_cache_init(void);

		sh4_cache_init();
	}

	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
		extern void __weak sh5_cache_init(void);

		sh5_cache_init();
	}

skip:
	emit_cache_params();
}
Commit	Line	Data
1da177e4	1	/*
f26b2a56	2	* arch/sh/mm/cache.c
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
a6198a23	5	* Copyright (C) 2002 - 2010 Paul Mundt
1da177e4 LT	6	*
	7	* Released under the terms of the GNU GPL v2.0.
	8	*/
1da177e4	9	#include <linux/mm.h>
acca4f4d	10	#include <linux/init.h>
52e27782	11	#include <linux/mutex.h>
e06c4e57	12	#include <linux/fs.h>
f26b2a56	13	#include <linux/smp.h>
7747b9a4 PM	14	#include <linux/highmem.h>
7747b9a4 PM	15	#include <linux/module.h>
1da177e4 LT	16	#include <asm/mmu_context.h>
	17	#include <asm/cacheflush.h>
	18
f26b2a56 PM	19	void (local_flush_cache_all)(void args) = cache_noop;
	20	void (local_flush_cache_mm)(void args) = cache_noop;
	21	void (local_flush_cache_dup_mm)(void args) = cache_noop;
	22	void (local_flush_cache_page)(void args) = cache_noop;
	23	void (local_flush_cache_range)(void args) = cache_noop;
	24	void (local_flush_dcache_page)(void args) = cache_noop;
	25	void (local_flush_icache_range)(void args) = cache_noop;
	26	void (local_flush_icache_page)(void args) = cache_noop;
	27	void (local_flush_cache_sigtramp)(void args) = cache_noop;
	28
37443ef3	29	void (__flush_wback_region)(void start, int size);
0a993b0a	30	EXPORT_SYMBOL(__flush_wback_region);
37443ef3	31	void (__flush_purge_region)(void start, int size);
0a993b0a	32	EXPORT_SYMBOL(__flush_purge_region);
37443ef3	33	void (__flush_invalidate_region)(void start, int size);
0a993b0a	34	EXPORT_SYMBOL(__flush_invalidate_region);
37443ef3	35
37443ef3 PM	36	static inline void noop__flush_region(void *start, int size)
	37	{
	38	}
	39
6f379578 PM	40	static inline void cacheop_on_each_cpu(void (func) (void info), void *info,
	41	int wait)
	42	{
	43	preempt_disable();
a6198a23 PM	44
	45	/*
	46	* It's possible that this gets called early on when IRQs are
	47	* still disabled due to ioremapping by the boot CPU, so don't
	48	* even attempt IPIs unless there are other CPUs online.
	49	*/
	50	if (num_online_cpus() > 1)
	51	smp_call_function(func, info, wait);
	52
6f379578	53	func(info);
a6198a23	54
6f379578 PM	55	preempt_enable();
	56	}
	57
ba1789ef PM	58	void copy_to_user_page(struct vm_area_struct vma, struct page page,
	59	unsigned long vaddr, void dst, const void src,
	60	unsigned long len)
1da177e4	61	{
0dfae7d5 PM	62	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
0dfae7d5 PM	63	!test_bit(PG_dcache_dirty, &page->flags)) {
2277ab4a PM	64	void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	65	memcpy(vto, src, len);
0906a3ad	66	kunmap_coherent(vto);
2277ab4a PM	67	} else {
2277ab4a PM	68	memcpy(dst, src, len);
0dfae7d5 PM	69	if (boot_cpu_data.dcache.n_aliases)
0dfae7d5 PM	70	set_bit(PG_dcache_dirty, &page->flags);
2277ab4a	71	}
ba1789ef PM	72
	73	if (vma->vm_flags & VM_EXEC)
	74	flush_cache_page(vma, vaddr, page_to_pfn(page));
	75	}
	76
	77	void copy_from_user_page(struct vm_area_struct vma, struct page page,
	78	unsigned long vaddr, void dst, const void src,
	79	unsigned long len)
	80	{
0dfae7d5 PM	81	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
0dfae7d5 PM	82	!test_bit(PG_dcache_dirty, &page->flags)) {
2277ab4a PM	83	void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
2277ab4a PM	84	memcpy(dst, vfrom, len);
0906a3ad	85	kunmap_coherent(vfrom);
2277ab4a PM	86	} else {
2277ab4a PM	87	memcpy(dst, src, len);
0dfae7d5 PM	88	if (boot_cpu_data.dcache.n_aliases)
0dfae7d5 PM	89	set_bit(PG_dcache_dirty, &page->flags);
2277ab4a	90	}
1da177e4	91	}
39e688a9	92
7747b9a4 PM	93	void copy_user_highpage(struct page to, struct page from,
	94	unsigned long vaddr, struct vm_area_struct *vma)
	95	{
	96	void vfrom, vto;
	97
7747b9a4	98	vto = kmap_atomic(to, KM_USER1);
7747b9a4	99
0dfae7d5 PM	100	if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
0dfae7d5 PM	101	!test_bit(PG_dcache_dirty, &from->flags)) {
7e01c949	102	vfrom = kmap_coherent(from, vaddr);
2277ab4a	103	copy_page(vto, vfrom);
7e01c949 PM	104	kunmap_coherent(vfrom);
	105	} else {
	106	vfrom = kmap_atomic(from, KM_USER0);
	107	copy_page(vto, vfrom);
	108	kunmap_atomic(vfrom, KM_USER0);
	109	}
7747b9a4	110
7e01c949 PM	111	if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
7e01c949 PM	112	__flush_purge_region(vto, PAGE_SIZE);
39ac11c1	113
7e01c949	114	kunmap_atomic(vto, KM_USER1);
7747b9a4 PM	115	/* Make sure this page is cleared on other CPU's too before using it */
	116	smp_wmb();
	117	}
	118	EXPORT_SYMBOL(copy_user_highpage);
dfff0fa6 PM	119
	120	void clear_user_highpage(struct page *page, unsigned long vaddr)
	121	{
	122	void *kaddr = kmap_atomic(page, KM_USER0);
	123
7e01c949	124	clear_page(kaddr);
dfff0fa6	125
7e01c949 PM	126	if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
7e01c949 PM	127	__flush_purge_region(kaddr, PAGE_SIZE);
dfff0fa6 PM	128
	129	kunmap_atomic(kaddr, KM_USER0);
	130	}
	131	EXPORT_SYMBOL(clear_user_highpage);
9cef7492 PM	132
	133	void __update_cache(struct vm_area_struct *vma,
	134	unsigned long address, pte_t pte)
	135	{
	136	struct page *page;
	137	unsigned long pfn = pte_pfn(pte);
	138
	139	if (!boot_cpu_data.dcache.n_aliases)
	140	return;
	141
	142	page = pfn_to_page(pfn);
964f7e5a	143	if (pfn_valid(pfn)) {
9cef7492	144	int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
76382b5b MP	145	if (dirty)
76382b5b MP	146	__flush_purge_region(page_address(page), PAGE_SIZE);
9cef7492 PM	147	}
9cef7492 PM	148	}
c0fe478d PM	149
	150	void __flush_anon_page(struct page *page, unsigned long vmaddr)
	151	{
	152	unsigned long addr = (unsigned long) page_address(page);
	153
	154	if (pages_do_alias(addr, vmaddr)) {
	155	if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
	156	!test_bit(PG_dcache_dirty, &page->flags)) {
	157	void *kaddr;
	158
	159	kaddr = kmap_coherent(page, vmaddr);
6e4154d4 PM	160	/* XXX.. For now kunmap_coherent() does a purge */
6e4154d4 PM	161	/* __flush_purge_region((void )kaddr, PAGE_SIZE); /
0906a3ad	162	kunmap_coherent(kaddr);
c0fe478d	163	} else
6e4154d4	164	__flush_purge_region((void *)addr, PAGE_SIZE);
c0fe478d PM	165	}
c0fe478d PM	166	}
ecba1060	167
f26b2a56 PM	168	void flush_cache_all(void)
f26b2a56 PM	169	{
6f379578	170	cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
f26b2a56	171	}
0a993b0a	172	EXPORT_SYMBOL(flush_cache_all);
f26b2a56 PM	173
	174	void flush_cache_mm(struct mm_struct *mm)
	175	{
654d364e PM	176	if (boot_cpu_data.dcache.n_aliases == 0)
	177	return;
	178
6f379578	179	cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
f26b2a56 PM	180	}
	181
	182	void flush_cache_dup_mm(struct mm_struct *mm)
	183	{
654d364e PM	184	if (boot_cpu_data.dcache.n_aliases == 0)
	185	return;
	186
6f379578	187	cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
f26b2a56 PM	188	}
	189
	190	void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
	191	unsigned long pfn)
	192	{
	193	struct flusher_data data;
	194
	195	data.vma = vma;
	196	data.addr1 = addr;
	197	data.addr2 = pfn;
	198
6f379578	199	cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
f26b2a56 PM	200	}
	201
	202	void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
	203	unsigned long end)
	204	{
	205	struct flusher_data data;
	206
	207	data.vma = vma;
	208	data.addr1 = start;
	209	data.addr2 = end;
	210
6f379578	211	cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
f26b2a56	212	}
0a993b0a	213	EXPORT_SYMBOL(flush_cache_range);
f26b2a56 PM	214
	215	void flush_dcache_page(struct page *page)
	216	{
6f379578	217	cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
f26b2a56	218	}
0a993b0a	219	EXPORT_SYMBOL(flush_dcache_page);
f26b2a56 PM	220
	221	void flush_icache_range(unsigned long start, unsigned long end)
	222	{
	223	struct flusher_data data;
	224
	225	data.vma = NULL;
	226	data.addr1 = start;
	227	data.addr2 = end;
	228
6f379578	229	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
f26b2a56 PM	230	}
	231
	232	void flush_icache_page(struct vm_area_struct vma, struct page page)
	233	{
	234	/* Nothing uses the VMA, so just pass the struct page along */
6f379578	235	cacheop_on_each_cpu(local_flush_icache_page, page, 1);
f26b2a56 PM	236	}
	237
	238	void flush_cache_sigtramp(unsigned long address)
	239	{
6f379578	240	cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
f26b2a56 PM	241	}
f26b2a56 PM	242
27d59ec1 PM	243	static void compute_alias(struct cache_info *c)
	244	{
	245	c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
	246	c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
	247	}
	248
	249	static void __init emit_cache_params(void)
	250	{
	251	printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	252	boot_cpu_data.icache.ways,
	253	boot_cpu_data.icache.sets,
	254	boot_cpu_data.icache.way_incr);
	255	printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	256	boot_cpu_data.icache.entry_mask,
	257	boot_cpu_data.icache.alias_mask,
	258	boot_cpu_data.icache.n_aliases);
	259	printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	260	boot_cpu_data.dcache.ways,
	261	boot_cpu_data.dcache.sets,
	262	boot_cpu_data.dcache.way_incr);
	263	printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	264	boot_cpu_data.dcache.entry_mask,
	265	boot_cpu_data.dcache.alias_mask,
	266	boot_cpu_data.dcache.n_aliases);
	267
	268	/*
	269	* Emit Secondary Cache parameters if the CPU has a probed L2.
	270	*/
	271	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
	272	printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
	273	boot_cpu_data.scache.ways,
	274	boot_cpu_data.scache.sets,
	275	boot_cpu_data.scache.way_incr);
	276	printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
	277	boot_cpu_data.scache.entry_mask,
	278	boot_cpu_data.scache.alias_mask,
	279	boot_cpu_data.scache.n_aliases);
	280	}
	281	}
	282
ecba1060 PM	283	void __init cpu_cache_init(void)
ecba1060 PM	284	{
3af539e5 PM	285	unsigned int cache_disabled = 0;
	286
	287	#ifdef CCR
	288	cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
	289	#endif
5fb80ae8	290
27d59ec1 PM	291	compute_alias(&boot_cpu_data.icache);
	292	compute_alias(&boot_cpu_data.dcache);
	293	compute_alias(&boot_cpu_data.scache);
	294
37443ef3 PM	295	__flush_wback_region = noop__flush_region;
	296	__flush_purge_region = noop__flush_region;
	297	__flush_invalidate_region = noop__flush_region;
	298
5fb80ae8 MD	299	/*
	300	* No flushing is necessary in the disabled cache case so we can
	301	* just keep the noop functions in local_flush_..() and __flush_..()
	302	*/
	303	if (unlikely(cache_disabled))
	304	goto skip;
	305
109b44a8 PM	306	if (boot_cpu_data.family == CPU_FAMILY_SH2) {
	307	extern void __weak sh2_cache_init(void);
	308
	309	sh2_cache_init();
	310	}
	311
a58e1a2a PM	312	if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
	313	extern void __weak sh2a_cache_init(void);
	314
	315	sh2a_cache_init();
	316	}
	317
79f1c9da PM	318	if (boot_cpu_data.family == CPU_FAMILY_SH3) {
	319	extern void __weak sh3_cache_init(void);
	320
	321	sh3_cache_init();
0d051d90 PM	322
	323	if ((boot_cpu_data.type == CPU_SH7705) &&
	324	(boot_cpu_data.dcache.sets == 512)) {
	325	extern void __weak sh7705_cache_init(void);
	326
	327	sh7705_cache_init();
	328	}
79f1c9da PM	329	}
79f1c9da PM	330
ecba1060 PM	331	if ((boot_cpu_data.family == CPU_FAMILY_SH4) \|\|
	332	(boot_cpu_data.family == CPU_FAMILY_SH4A) \|\|
	333	(boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
	334	extern void __weak sh4_cache_init(void);
	335
	336	sh4_cache_init();
	337	}
27d59ec1	338
2b431518 PM	339	if (boot_cpu_data.family == CPU_FAMILY_SH5) {
	340	extern void __weak sh5_cache_init(void);
	341
	342	sh5_cache_init();
	343	}
	344
5fb80ae8	345	skip:
27d59ec1	346	emit_cache_params();
ecba1060	347	}