sh: bootmem refactoring.
[deliverable/linux.git] / arch / sh / mm / pmb.c
CommitLineData
0c7b1df6
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1/*
2 * arch/sh/mm/pmb.c
3 *
4 * Privileged Space Mapping Buffer (PMB) Support.
5 *
3d467676
MF
6 * Copyright (C) 2005 - 2010 Paul Mundt
7 * Copyright (C) 2010 Matt Fleming
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8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/kernel.h>
a83c0b73
FV
15#include <linux/sysdev.h>
16#include <linux/cpu.h>
0c7b1df6 17#include <linux/module.h>
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18#include <linux/bitops.h>
19#include <linux/debugfs.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22#include <linux/err.h>
51becfd9 23#include <linux/io.h>
d53a0d33 24#include <linux/spinlock.h>
90e7d649 25#include <linux/vmalloc.h>
281983d6 26#include <asm/cacheflush.h>
51becfd9 27#include <asm/sizes.h>
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28#include <asm/system.h>
29#include <asm/uaccess.h>
d7cdc9e8 30#include <asm/pgtable.h>
7bdda620 31#include <asm/page.h>
0c7b1df6 32#include <asm/mmu.h>
eddeeb32 33#include <asm/mmu_context.h>
0c7b1df6 34
d53a0d33
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35struct pmb_entry;
36
37struct pmb_entry {
38 unsigned long vpn;
39 unsigned long ppn;
40 unsigned long flags;
41 unsigned long size;
42
43 spinlock_t lock;
44
45 /*
46 * 0 .. NR_PMB_ENTRIES for specific entry selection, or
47 * PMB_NO_ENTRY to search for a free one
48 */
49 int entry;
50
51 /* Adjacent entry link for contiguous multi-entry mappings */
52 struct pmb_entry *link;
53};
54
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55static struct {
56 unsigned long size;
57 int flag;
58} pmb_sizes[] = {
59 { .size = SZ_512M, .flag = PMB_SZ_512M, },
60 { .size = SZ_128M, .flag = PMB_SZ_128M, },
61 { .size = SZ_64M, .flag = PMB_SZ_64M, },
62 { .size = SZ_16M, .flag = PMB_SZ_16M, },
63};
64
d01447b3 65static void pmb_unmap_entry(struct pmb_entry *, int depth);
fc2bdefd 66
d53a0d33 67static DEFINE_RWLOCK(pmb_rwlock);
edd7de80 68static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
51becfd9 69static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
0c7b1df6 70
4cfa8e75
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71static unsigned int pmb_iomapping_enabled;
72
51becfd9 73static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
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74{
75 return (entry & PMB_E_MASK) << PMB_E_SHIFT;
76}
77
51becfd9 78static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
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79{
80 return mk_pmb_entry(entry) | PMB_ADDR;
81}
82
51becfd9 83static __always_inline unsigned long mk_pmb_data(unsigned int entry)
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84{
85 return mk_pmb_entry(entry) | PMB_DATA;
86}
87
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88static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
89{
90 return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
91}
92
93/*
94 * Ensure that the PMB entries match our cache configuration.
95 *
96 * When we are in 32-bit address extended mode, CCR.CB becomes
97 * invalid, so care must be taken to manually adjust cacheable
98 * translations.
99 */
100static __always_inline unsigned long pmb_cache_flags(void)
101{
102 unsigned long flags = 0;
103
104#if defined(CONFIG_CACHE_OFF)
105 flags |= PMB_WT | PMB_UB;
106#elif defined(CONFIG_CACHE_WRITETHROUGH)
107 flags |= PMB_C | PMB_WT | PMB_UB;
108#elif defined(CONFIG_CACHE_WRITEBACK)
109 flags |= PMB_C;
110#endif
111
112 return flags;
113}
114
115/*
116 * Convert typical pgprot value to the PMB equivalent
117 */
118static inline unsigned long pgprot_to_pmb_flags(pgprot_t prot)
119{
120 unsigned long pmb_flags = 0;
121 u64 flags = pgprot_val(prot);
122
123 if (flags & _PAGE_CACHABLE)
124 pmb_flags |= PMB_C;
125 if (flags & _PAGE_WT)
126 pmb_flags |= PMB_WT | PMB_UB;
127
128 return pmb_flags;
129}
130
a1042aa2 131static inline bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
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132{
133 return (b->vpn == (a->vpn + a->size)) &&
134 (b->ppn == (a->ppn + a->size)) &&
135 (b->flags == a->flags);
136}
137
a1042aa2
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138static bool pmb_mapping_exists(unsigned long vaddr, phys_addr_t phys,
139 unsigned long size)
140{
141 int i;
142
143 read_lock(&pmb_rwlock);
144
145 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
146 struct pmb_entry *pmbe, *iter;
147 unsigned long span;
148
149 if (!test_bit(i, pmb_map))
150 continue;
151
152 pmbe = &pmb_entry_list[i];
153
154 /*
155 * See if VPN and PPN are bounded by an existing mapping.
156 */
157 if ((vaddr < pmbe->vpn) || (vaddr >= (pmbe->vpn + pmbe->size)))
158 continue;
159 if ((phys < pmbe->ppn) || (phys >= (pmbe->ppn + pmbe->size)))
160 continue;
161
162 /*
163 * Now see if we're in range of a simple mapping.
164 */
165 if (size <= pmbe->size) {
166 read_unlock(&pmb_rwlock);
167 return true;
168 }
169
170 span = pmbe->size;
171
172 /*
173 * Finally for sizes that involve compound mappings, walk
174 * the chain.
175 */
176 for (iter = pmbe->link; iter; iter = iter->link)
177 span += iter->size;
178
179 /*
180 * Nothing else to do if the range requirements are met.
181 */
182 if (size <= span) {
183 read_unlock(&pmb_rwlock);
184 return true;
185 }
186 }
187
188 read_unlock(&pmb_rwlock);
189 return false;
190}
191
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192static bool pmb_size_valid(unsigned long size)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
197 if (pmb_sizes[i].size == size)
198 return true;
199
200 return false;
201}
202
203static inline bool pmb_addr_valid(unsigned long addr, unsigned long size)
204{
205 return (addr >= P1SEG && (addr + size - 1) < P3SEG);
206}
207
208static inline bool pmb_prot_valid(pgprot_t prot)
209{
210 return (pgprot_val(prot) & _PAGE_USER) == 0;
211}
212
213static int pmb_size_to_flags(unsigned long size)
214{
215 int i;
216
217 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
218 if (pmb_sizes[i].size == size)
219 return pmb_sizes[i].flag;
220
221 return 0;
222}
223
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224static int pmb_alloc_entry(void)
225{
d53a0d33 226 int pos;
067784f6 227
51becfd9 228 pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
d53a0d33
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229 if (pos >= 0 && pos < NR_PMB_ENTRIES)
230 __set_bit(pos, pmb_map);
231 else
232 pos = -ENOSPC;
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233
234 return pos;
235}
236
8386aebb 237static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
20b5014b 238 unsigned long flags, int entry)
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239{
240 struct pmb_entry *pmbe;
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241 unsigned long irqflags;
242 void *ret = NULL;
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243 int pos;
244
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245 write_lock_irqsave(&pmb_rwlock, irqflags);
246
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247 if (entry == PMB_NO_ENTRY) {
248 pos = pmb_alloc_entry();
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249 if (unlikely(pos < 0)) {
250 ret = ERR_PTR(pos);
251 goto out;
252 }
20b5014b 253 } else {
d53a0d33
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254 if (__test_and_set_bit(entry, pmb_map)) {
255 ret = ERR_PTR(-ENOSPC);
256 goto out;
257 }
258
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259 pos = entry;
260 }
0c7b1df6 261
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262 write_unlock_irqrestore(&pmb_rwlock, irqflags);
263
edd7de80 264 pmbe = &pmb_entry_list[pos];
d53a0d33 265
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266 memset(pmbe, 0, sizeof(struct pmb_entry));
267
d53a0d33 268 spin_lock_init(&pmbe->lock);
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269
270 pmbe->vpn = vpn;
271 pmbe->ppn = ppn;
272 pmbe->flags = flags;
067784f6 273 pmbe->entry = pos;
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274
275 return pmbe;
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276
277out:
278 write_unlock_irqrestore(&pmb_rwlock, irqflags);
279 return ret;
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280}
281
8386aebb 282static void pmb_free(struct pmb_entry *pmbe)
0c7b1df6 283{
d53a0d33 284 __clear_bit(pmbe->entry, pmb_map);
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285
286 pmbe->entry = PMB_NO_ENTRY;
287 pmbe->link = NULL;
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288}
289
290/*
51becfd9 291 * Must be run uncached.
0c7b1df6 292 */
d53a0d33 293static void __set_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 294{
281983d6
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295 unsigned long addr, data;
296
297 addr = mk_pmb_addr(pmbe->entry);
298 data = mk_pmb_data(pmbe->entry);
299
300 jump_to_uncached();
301
90e7d649 302 /* Set V-bit */
281983d6
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303 __raw_writel(pmbe->vpn | PMB_V, addr);
304 __raw_writel(pmbe->ppn | pmbe->flags | PMB_V, data);
305
306 back_to_cached();
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307}
308
d53a0d33 309static void __clear_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 310{
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311 unsigned long addr, data;
312 unsigned long addr_val, data_val;
0c7b1df6 313
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314 addr = mk_pmb_addr(pmbe->entry);
315 data = mk_pmb_data(pmbe->entry);
0c7b1df6 316
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317 addr_val = __raw_readl(addr);
318 data_val = __raw_readl(data);
0c7b1df6 319
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320 /* Clear V-bit */
321 writel_uncached(addr_val & ~PMB_V, addr);
322 writel_uncached(data_val & ~PMB_V, data);
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323}
324
3fe0f36c 325#ifdef CONFIG_PM
d53a0d33
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326static void set_pmb_entry(struct pmb_entry *pmbe)
327{
328 unsigned long flags;
329
330 spin_lock_irqsave(&pmbe->lock, flags);
331 __set_pmb_entry(pmbe);
332 spin_unlock_irqrestore(&pmbe->lock, flags);
333}
3fe0f36c 334#endif /* CONFIG_PM */
d53a0d33 335
90e7d649
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336int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
337 unsigned long size, pgprot_t prot)
d7cdc9e8 338{
fc2bdefd 339 struct pmb_entry *pmbp, *pmbe;
281983d6 340 unsigned long orig_addr, orig_size;
a1042aa2 341 unsigned long flags, pmb_flags;
90e7d649 342 int i, mapped;
90e7d649 343
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344 if (!pmb_addr_valid(vaddr, size))
345 return -EFAULT;
a1042aa2
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346 if (pmb_mapping_exists(vaddr, phys, size))
347 return 0;
7bdda620 348
281983d6
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349 orig_addr = vaddr;
350 orig_size = size;
351
352 flush_tlb_kernel_range(vaddr, vaddr + size);
353
90e7d649 354 pmb_flags = pgprot_to_pmb_flags(prot);
6eb3c735 355 pmbp = NULL;
d7cdc9e8 356
a1042aa2
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357 do {
358 for (i = mapped = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
359 if (size < pmb_sizes[i].size)
360 continue;
d7cdc9e8 361
a1042aa2
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362 pmbe = pmb_alloc(vaddr, phys, pmb_flags |
363 pmb_sizes[i].flag, PMB_NO_ENTRY);
364 if (IS_ERR(pmbe)) {
365 pmb_unmap_entry(pmbp, mapped);
366 return PTR_ERR(pmbe);
367 }
d53a0d33 368
a1042aa2 369 spin_lock_irqsave(&pmbe->lock, flags);
d7cdc9e8 370
a1042aa2 371 pmbe->size = pmb_sizes[i].size;
d7cdc9e8 372
a1042aa2 373 __set_pmb_entry(pmbe);
d7813bc9 374
a1042aa2
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375 phys += pmbe->size;
376 vaddr += pmbe->size;
377 size -= pmbe->size;
d7cdc9e8 378
a1042aa2
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379 /*
380 * Link adjacent entries that span multiple PMB
381 * entries for easier tear-down.
382 */
383 if (likely(pmbp)) {
384 spin_lock(&pmbp->lock);
385 pmbp->link = pmbe;
386 spin_unlock(&pmbp->lock);
387 }
a2767cfb 388
a1042aa2 389 pmbp = pmbe;
d53a0d33 390
a1042aa2
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391 /*
392 * Instead of trying smaller sizes on every
393 * iteration (even if we succeed in allocating
394 * space), try using pmb_sizes[i].size again.
395 */
396 i--;
397 mapped++;
d7cdc9e8 398
a1042aa2
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399 spin_unlock_irqrestore(&pmbe->lock, flags);
400 }
401 } while (size >= SZ_16M);
d7cdc9e8 402
281983d6
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403 flush_cache_vmap(orig_addr, orig_addr + orig_size);
404
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405 return 0;
406}
407
408void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
409 pgprot_t prot, void *caller)
410{
281983d6 411 unsigned long vaddr;
6eb3c735
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412 phys_addr_t offset, last_addr;
413 phys_addr_t align_mask;
414 unsigned long aligned;
415 struct vm_struct *area;
416 int i, ret;
417
418 if (!pmb_iomapping_enabled)
419 return NULL;
420
421 /*
422 * Small mappings need to go through the TLB.
423 */
424 if (size < SZ_16M)
425 return ERR_PTR(-EINVAL);
426 if (!pmb_prot_valid(prot))
427 return ERR_PTR(-EINVAL);
428
429 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
430 if (size >= pmb_sizes[i].size)
431 break;
432
433 last_addr = phys + size;
434 align_mask = ~(pmb_sizes[i].size - 1);
435 offset = phys & ~align_mask;
436 phys &= align_mask;
437 aligned = ALIGN(last_addr, pmb_sizes[i].size) - phys;
438
281983d6
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439 /*
440 * XXX: This should really start from uncached_end, but this
441 * causes the MMU to reset, so for now we restrict it to the
442 * 0xb000...0xc000 range.
443 */
444 area = __get_vm_area_caller(aligned, VM_IOREMAP, 0xb0000000,
6eb3c735
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445 P3SEG, caller);
446 if (!area)
447 return NULL;
448
449 area->phys_addr = phys;
281983d6 450 vaddr = (unsigned long)area->addr;
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451
452 ret = pmb_bolt_mapping(vaddr, phys, size, prot);
a1042aa2 453 if (unlikely(ret != 0))
6eb3c735
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454 return ERR_PTR(ret);
455
281983d6 456 return (void __iomem *)(offset + (char *)vaddr);
d7cdc9e8
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457}
458
90e7d649 459int pmb_unmap(void __iomem *addr)
d7cdc9e8 460{
d53a0d33 461 struct pmb_entry *pmbe = NULL;
90e7d649
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462 unsigned long vaddr = (unsigned long __force)addr;
463 int i, found = 0;
d7cdc9e8 464
d53a0d33
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465 read_lock(&pmb_rwlock);
466
edd7de80 467 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 468 if (test_bit(i, pmb_map)) {
edd7de80 469 pmbe = &pmb_entry_list[i];
90e7d649
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470 if (pmbe->vpn == vaddr) {
471 found = 1;
edd7de80 472 break;
90e7d649 473 }
edd7de80
MF
474 }
475 }
d53a0d33
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476
477 read_unlock(&pmb_rwlock);
478
90e7d649
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479 if (found) {
480 pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
481 return 0;
482 }
d7cdc9e8 483
90e7d649 484 return -EINVAL;
d01447b3
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485}
486
487static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
488{
d7cdc9e8
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489 do {
490 struct pmb_entry *pmblink = pmbe;
491
067784f6
MF
492 /*
493 * We may be called before this pmb_entry has been
494 * entered into the PMB table via set_pmb_entry(), but
495 * that's OK because we've allocated a unique slot for
496 * this entry in pmb_alloc() (even if we haven't filled
497 * it yet).
498 *
d53a0d33 499 * Therefore, calling __clear_pmb_entry() is safe as no
067784f6
MF
500 * other mapping can be using that slot.
501 */
d53a0d33 502 __clear_pmb_entry(pmbe);
fc2bdefd 503
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504 flush_cache_vunmap(pmbe->vpn, pmbe->vpn + pmbe->size);
505
d7cdc9e8
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506 pmbe = pmblink->link;
507
508 pmb_free(pmblink);
d01447b3
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509 } while (pmbe && --depth);
510}
511
512static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
513{
514 unsigned long flags;
d53a0d33 515
d01447b3
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516 if (unlikely(!pmbe))
517 return;
518
519 write_lock_irqsave(&pmb_rwlock, flags);
520 __pmb_unmap_entry(pmbe, depth);
d53a0d33 521 write_unlock_irqrestore(&pmb_rwlock, flags);
d7cdc9e8
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522}
523
d01447b3 524static void __init pmb_notify(void)
20b5014b 525{
d01447b3 526 int i;
20b5014b 527
efd54ea3 528 pr_info("PMB: boot mappings:\n");
20b5014b 529
d01447b3
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530 read_lock(&pmb_rwlock);
531
532 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
533 struct pmb_entry *pmbe;
534
535 if (!test_bit(i, pmb_map))
536 continue;
537
538 pmbe = &pmb_entry_list[i];
539
540 pr_info(" 0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
541 pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
542 pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
543 }
544
545 read_unlock(&pmb_rwlock);
546}
547
548/*
549 * Sync our software copy of the PMB mappings with those in hardware. The
550 * mappings in the hardware PMB were either set up by the bootloader or
551 * very early on by the kernel.
552 */
553static void __init pmb_synchronize(void)
554{
555 struct pmb_entry *pmbp = NULL;
556 int i, j;
557
3d467676 558 /*
efd54ea3
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559 * Run through the initial boot mappings, log the established
560 * ones, and blow away anything that falls outside of the valid
561 * PPN range. Specifically, we only care about existing mappings
562 * that impact the cached/uncached sections.
3d467676 563 *
efd54ea3
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564 * Note that touching these can be a bit of a minefield; the boot
565 * loader can establish multi-page mappings with the same caching
566 * attributes, so we need to ensure that we aren't modifying a
567 * mapping that we're presently executing from, or may execute
568 * from in the case of straddling page boundaries.
3d467676 569 *
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570 * In the future we will have to tidy up after the boot loader by
571 * jumping between the cached and uncached mappings and tearing
572 * down alternating mappings while executing from the other.
3d467676 573 */
51becfd9 574 for (i = 0; i < NR_PMB_ENTRIES; i++) {
3d467676
MF
575 unsigned long addr, data;
576 unsigned long addr_val, data_val;
efd54ea3 577 unsigned long ppn, vpn, flags;
d53a0d33 578 unsigned long irqflags;
d7813bc9 579 unsigned int size;
efd54ea3 580 struct pmb_entry *pmbe;
20b5014b 581
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582 addr = mk_pmb_addr(i);
583 data = mk_pmb_data(i);
20b5014b 584
3d467676
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585 addr_val = __raw_readl(addr);
586 data_val = __raw_readl(data);
20b5014b 587
3d467676
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588 /*
589 * Skip over any bogus entries
590 */
591 if (!(data_val & PMB_V) || !(addr_val & PMB_V))
592 continue;
20b5014b 593
3d467676
MF
594 ppn = data_val & PMB_PFN_MASK;
595 vpn = addr_val & PMB_PFN_MASK;
a0ab3668 596
3d467676
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597 /*
598 * Only preserve in-range mappings.
599 */
efd54ea3 600 if (!pmb_ppn_in_range(ppn)) {
3d467676
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601 /*
602 * Invalidate anything out of bounds.
603 */
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604 writel_uncached(addr_val & ~PMB_V, addr);
605 writel_uncached(data_val & ~PMB_V, data);
efd54ea3 606 continue;
3d467676 607 }
efd54ea3
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608
609 /*
610 * Update the caching attributes if necessary
611 */
612 if (data_val & PMB_C) {
0065b967
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613 data_val &= ~PMB_CACHE_MASK;
614 data_val |= pmb_cache_flags();
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615
616 writel_uncached(data_val, data);
efd54ea3
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617 }
618
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619 size = data_val & PMB_SZ_MASK;
620 flags = size | (data_val & PMB_CACHE_MASK);
efd54ea3
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621
622 pmbe = pmb_alloc(vpn, ppn, flags, i);
623 if (IS_ERR(pmbe)) {
624 WARN_ON_ONCE(1);
625 continue;
626 }
627
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628 spin_lock_irqsave(&pmbe->lock, irqflags);
629
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630 for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
631 if (pmb_sizes[j].flag == size)
632 pmbe->size = pmb_sizes[j].size;
633
d53a0d33
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634 if (pmbp) {
635 spin_lock(&pmbp->lock);
636
637 /*
638 * Compare the previous entry against the current one to
639 * see if the entries span a contiguous mapping. If so,
d01447b3
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640 * setup the entry links accordingly. Compound mappings
641 * are later coalesced.
d53a0d33 642 */
d01447b3 643 if (pmb_can_merge(pmbp, pmbe))
d53a0d33
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644 pmbp->link = pmbe;
645
646 spin_unlock(&pmbp->lock);
647 }
d7813bc9
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648
649 pmbp = pmbe;
650
d53a0d33 651 spin_unlock_irqrestore(&pmbe->lock, irqflags);
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652 }
653}
d53a0d33 654
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655static void __init pmb_merge(struct pmb_entry *head)
656{
657 unsigned long span, newsize;
658 struct pmb_entry *tail;
659 int i = 1, depth = 0;
660
661 span = newsize = head->size;
efd54ea3 662
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663 tail = head->link;
664 while (tail) {
665 span += tail->size;
666
667 if (pmb_size_valid(span)) {
668 newsize = span;
669 depth = i;
670 }
671
672 /* This is the end of the line.. */
673 if (!tail->link)
674 break;
675
676 tail = tail->link;
677 i++;
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678 }
679
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680 /*
681 * The merged page size must be valid.
682 */
c7b03fa0 683 if (!depth || !pmb_size_valid(newsize))
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684 return;
685
686 head->flags &= ~PMB_SZ_MASK;
687 head->flags |= pmb_size_to_flags(newsize);
688
689 head->size = newsize;
690
691 __pmb_unmap_entry(head->link, depth);
692 __set_pmb_entry(head);
a0ab3668 693}
a0ab3668 694
d01447b3 695static void __init pmb_coalesce(void)
a0ab3668 696{
d01447b3
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697 unsigned long flags;
698 int i;
699
700 write_lock_irqsave(&pmb_rwlock, flags);
701
702 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
703 struct pmb_entry *pmbe;
704
705 if (!test_bit(i, pmb_map))
706 continue;
707
708 pmbe = &pmb_entry_list[i];
709
710 /*
711 * We're only interested in compound mappings
712 */
713 if (!pmbe->link)
714 continue;
715
716 /*
717 * Nothing to do if it already uses the largest possible
718 * page size.
719 */
720 if (pmbe->size == SZ_512M)
721 continue;
722
723 pmb_merge(pmbe);
724 }
725
726 write_unlock_irqrestore(&pmb_rwlock, flags);
727}
728
729#ifdef CONFIG_UNCACHED_MAPPING
730static void __init pmb_resize(void)
731{
732 int i;
a0ab3668 733
a0ab3668 734 /*
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735 * If the uncached mapping was constructed by the kernel, it will
736 * already be a reasonable size.
a0ab3668 737 */
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738 if (uncached_size == SZ_16M)
739 return;
740
741 read_lock(&pmb_rwlock);
742
743 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
744 struct pmb_entry *pmbe;
745 unsigned long flags;
746
747 if (!test_bit(i, pmb_map))
748 continue;
749
750 pmbe = &pmb_entry_list[i];
751
752 if (pmbe->vpn != uncached_start)
753 continue;
754
755 /*
756 * Found it, now resize it.
757 */
758 spin_lock_irqsave(&pmbe->lock, flags);
759
760 pmbe->size = SZ_16M;
761 pmbe->flags &= ~PMB_SZ_MASK;
762 pmbe->flags |= pmb_size_to_flags(pmbe->size);
763
764 uncached_resize(pmbe->size);
765
766 __set_pmb_entry(pmbe);
767
768 spin_unlock_irqrestore(&pmbe->lock, flags);
769 }
770
771 read_lock(&pmb_rwlock);
772}
773#endif
774
4cfa8e75
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775static int __init early_pmb(char *p)
776{
777 if (!p)
778 return 0;
779
780 if (strstr(p, "iomap"))
781 pmb_iomapping_enabled = 1;
782
783 return 0;
784}
785early_param("pmb", early_pmb);
786
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787void __init pmb_init(void)
788{
789 /* Synchronize software state */
790 pmb_synchronize();
791
792 /* Attempt to combine compound mappings */
793 pmb_coalesce();
794
795#ifdef CONFIG_UNCACHED_MAPPING
796 /* Resize initial mappings, if necessary */
797 pmb_resize();
798#endif
799
800 /* Log them */
801 pmb_notify();
3d467676 802
2e450643 803 writel_uncached(0, PMB_IRMCR);
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804
805 /* Flush out the TLB */
b5b6c7ee 806 local_flush_tlb_all();
2e450643 807 ctrl_barrier();
20b5014b 808}
0c7b1df6 809
2efa53b2
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810bool __in_29bit_mode(void)
811{
812 return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
813}
814
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815static int pmb_seq_show(struct seq_file *file, void *iter)
816{
817 int i;
818
819 seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n"
820 "CB: Copy-Back, B: Buffered, UB: Unbuffered\n");
821 seq_printf(file, "ety vpn ppn size flags\n");
822
823 for (i = 0; i < NR_PMB_ENTRIES; i++) {
824 unsigned long addr, data;
825 unsigned int size;
826 char *sz_str = NULL;
827
9d56dd3b
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828 addr = __raw_readl(mk_pmb_addr(i));
829 data = __raw_readl(mk_pmb_data(i));
0c7b1df6
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830
831 size = data & PMB_SZ_MASK;
832 sz_str = (size == PMB_SZ_16M) ? " 16MB":
833 (size == PMB_SZ_64M) ? " 64MB":
834 (size == PMB_SZ_128M) ? "128MB":
835 "512MB";
836
837 /* 02: V 0x88 0x08 128MB C CB B */
838 seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n",
839 i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ',
840 (addr >> 24) & 0xff, (data >> 24) & 0xff,
841 sz_str, (data & PMB_C) ? 'C' : ' ',
842 (data & PMB_WT) ? "WT" : "CB",
843 (data & PMB_UB) ? "UB" : " B");
844 }
845
846 return 0;
847}
848
849static int pmb_debugfs_open(struct inode *inode, struct file *file)
850{
851 return single_open(file, pmb_seq_show, NULL);
852}
853
5dfe4c96 854static const struct file_operations pmb_debugfs_fops = {
0c7b1df6
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855 .owner = THIS_MODULE,
856 .open = pmb_debugfs_open,
857 .read = seq_read,
858 .llseek = seq_lseek,
45dabf14 859 .release = single_release,
0c7b1df6
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860};
861
862static int __init pmb_debugfs_init(void)
863{
864 struct dentry *dentry;
865
866 dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
b9e393c2 867 sh_debugfs_root, NULL, &pmb_debugfs_fops);
25627c7f
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868 if (!dentry)
869 return -ENOMEM;
0c7b1df6
PM
870 if (IS_ERR(dentry))
871 return PTR_ERR(dentry);
872
873 return 0;
874}
62c8cbbf 875subsys_initcall(pmb_debugfs_init);
a83c0b73
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876
877#ifdef CONFIG_PM
878static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
879{
880 static pm_message_t prev_state;
edd7de80 881 int i;
a83c0b73
FV
882
883 /* Restore the PMB after a resume from hibernation */
884 if (state.event == PM_EVENT_ON &&
885 prev_state.event == PM_EVENT_FREEZE) {
886 struct pmb_entry *pmbe;
d53a0d33
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887
888 read_lock(&pmb_rwlock);
889
edd7de80 890 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 891 if (test_bit(i, pmb_map)) {
edd7de80
MF
892 pmbe = &pmb_entry_list[i];
893 set_pmb_entry(pmbe);
894 }
895 }
d53a0d33
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896
897 read_unlock(&pmb_rwlock);
a83c0b73 898 }
d53a0d33 899
a83c0b73 900 prev_state = state;
d53a0d33 901
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902 return 0;
903}
904
905static int pmb_sysdev_resume(struct sys_device *dev)
906{
907 return pmb_sysdev_suspend(dev, PMSG_ON);
908}
909
910static struct sysdev_driver pmb_sysdev_driver = {
911 .suspend = pmb_sysdev_suspend,
912 .resume = pmb_sysdev_resume,
913};
914
915static int __init pmb_sysdev_init(void)
916{
917 return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
918}
a83c0b73
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919subsys_initcall(pmb_sysdev_init);
920#endif
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