sh: reworked dynamic PMB mapping.
[deliverable/linux.git] / arch / sh / mm / pmb.c
CommitLineData
0c7b1df6
PM
1/*
2 * arch/sh/mm/pmb.c
3 *
4 * Privileged Space Mapping Buffer (PMB) Support.
5 *
3d467676
MF
6 * Copyright (C) 2005 - 2010 Paul Mundt
7 * Copyright (C) 2010 Matt Fleming
0c7b1df6
PM
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/kernel.h>
a83c0b73
FV
15#include <linux/sysdev.h>
16#include <linux/cpu.h>
0c7b1df6
PM
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/bitops.h>
20#include <linux/debugfs.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/err.h>
51becfd9 24#include <linux/io.h>
d53a0d33 25#include <linux/spinlock.h>
90e7d649 26#include <linux/vmalloc.h>
51becfd9 27#include <asm/sizes.h>
0c7b1df6
PM
28#include <asm/system.h>
29#include <asm/uaccess.h>
d7cdc9e8 30#include <asm/pgtable.h>
7bdda620 31#include <asm/page.h>
0c7b1df6 32#include <asm/mmu.h>
eddeeb32 33#include <asm/mmu_context.h>
0c7b1df6 34
d53a0d33
PM
35struct pmb_entry;
36
37struct pmb_entry {
38 unsigned long vpn;
39 unsigned long ppn;
40 unsigned long flags;
41 unsigned long size;
42
43 spinlock_t lock;
44
45 /*
46 * 0 .. NR_PMB_ENTRIES for specific entry selection, or
47 * PMB_NO_ENTRY to search for a free one
48 */
49 int entry;
50
51 /* Adjacent entry link for contiguous multi-entry mappings */
52 struct pmb_entry *link;
53};
54
90e7d649
PM
55static struct {
56 unsigned long size;
57 int flag;
58} pmb_sizes[] = {
59 { .size = SZ_512M, .flag = PMB_SZ_512M, },
60 { .size = SZ_128M, .flag = PMB_SZ_128M, },
61 { .size = SZ_64M, .flag = PMB_SZ_64M, },
62 { .size = SZ_16M, .flag = PMB_SZ_16M, },
63};
64
d01447b3 65static void pmb_unmap_entry(struct pmb_entry *, int depth);
fc2bdefd 66
d53a0d33 67static DEFINE_RWLOCK(pmb_rwlock);
edd7de80 68static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
51becfd9 69static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
0c7b1df6 70
51becfd9 71static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
0c7b1df6
PM
72{
73 return (entry & PMB_E_MASK) << PMB_E_SHIFT;
74}
75
51becfd9 76static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
0c7b1df6
PM
77{
78 return mk_pmb_entry(entry) | PMB_ADDR;
79}
80
51becfd9 81static __always_inline unsigned long mk_pmb_data(unsigned int entry)
0c7b1df6
PM
82{
83 return mk_pmb_entry(entry) | PMB_DATA;
84}
85
90e7d649
PM
86static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
87{
88 return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
89}
90
91/*
92 * Ensure that the PMB entries match our cache configuration.
93 *
94 * When we are in 32-bit address extended mode, CCR.CB becomes
95 * invalid, so care must be taken to manually adjust cacheable
96 * translations.
97 */
98static __always_inline unsigned long pmb_cache_flags(void)
99{
100 unsigned long flags = 0;
101
102#if defined(CONFIG_CACHE_OFF)
103 flags |= PMB_WT | PMB_UB;
104#elif defined(CONFIG_CACHE_WRITETHROUGH)
105 flags |= PMB_C | PMB_WT | PMB_UB;
106#elif defined(CONFIG_CACHE_WRITEBACK)
107 flags |= PMB_C;
108#endif
109
110 return flags;
111}
112
113/*
114 * Convert typical pgprot value to the PMB equivalent
115 */
116static inline unsigned long pgprot_to_pmb_flags(pgprot_t prot)
117{
118 unsigned long pmb_flags = 0;
119 u64 flags = pgprot_val(prot);
120
121 if (flags & _PAGE_CACHABLE)
122 pmb_flags |= PMB_C;
123 if (flags & _PAGE_WT)
124 pmb_flags |= PMB_WT | PMB_UB;
125
126 return pmb_flags;
127}
128
129static bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
130{
131 return (b->vpn == (a->vpn + a->size)) &&
132 (b->ppn == (a->ppn + a->size)) &&
133 (b->flags == a->flags);
134}
135
136static bool pmb_size_valid(unsigned long size)
137{
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
141 if (pmb_sizes[i].size == size)
142 return true;
143
144 return false;
145}
146
147static inline bool pmb_addr_valid(unsigned long addr, unsigned long size)
148{
149 return (addr >= P1SEG && (addr + size - 1) < P3SEG);
150}
151
152static inline bool pmb_prot_valid(pgprot_t prot)
153{
154 return (pgprot_val(prot) & _PAGE_USER) == 0;
155}
156
157static int pmb_size_to_flags(unsigned long size)
158{
159 int i;
160
161 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
162 if (pmb_sizes[i].size == size)
163 return pmb_sizes[i].flag;
164
165 return 0;
166}
167
067784f6
MF
168static int pmb_alloc_entry(void)
169{
d53a0d33 170 int pos;
067784f6 171
51becfd9 172 pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
d53a0d33
PM
173 if (pos >= 0 && pos < NR_PMB_ENTRIES)
174 __set_bit(pos, pmb_map);
175 else
176 pos = -ENOSPC;
067784f6
MF
177
178 return pos;
179}
180
8386aebb 181static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
20b5014b 182 unsigned long flags, int entry)
0c7b1df6
PM
183{
184 struct pmb_entry *pmbe;
d53a0d33
PM
185 unsigned long irqflags;
186 void *ret = NULL;
067784f6
MF
187 int pos;
188
d53a0d33
PM
189 write_lock_irqsave(&pmb_rwlock, irqflags);
190
20b5014b
MF
191 if (entry == PMB_NO_ENTRY) {
192 pos = pmb_alloc_entry();
d53a0d33
PM
193 if (unlikely(pos < 0)) {
194 ret = ERR_PTR(pos);
195 goto out;
196 }
20b5014b 197 } else {
d53a0d33
PM
198 if (__test_and_set_bit(entry, pmb_map)) {
199 ret = ERR_PTR(-ENOSPC);
200 goto out;
201 }
202
20b5014b
MF
203 pos = entry;
204 }
0c7b1df6 205
d53a0d33
PM
206 write_unlock_irqrestore(&pmb_rwlock, irqflags);
207
edd7de80 208 pmbe = &pmb_entry_list[pos];
d53a0d33 209
d01447b3
PM
210 memset(pmbe, 0, sizeof(struct pmb_entry));
211
d53a0d33 212 spin_lock_init(&pmbe->lock);
0c7b1df6
PM
213
214 pmbe->vpn = vpn;
215 pmbe->ppn = ppn;
216 pmbe->flags = flags;
067784f6 217 pmbe->entry = pos;
0c7b1df6
PM
218
219 return pmbe;
d53a0d33
PM
220
221out:
222 write_unlock_irqrestore(&pmb_rwlock, irqflags);
223 return ret;
0c7b1df6
PM
224}
225
8386aebb 226static void pmb_free(struct pmb_entry *pmbe)
0c7b1df6 227{
d53a0d33 228 __clear_bit(pmbe->entry, pmb_map);
d01447b3
PM
229
230 pmbe->entry = PMB_NO_ENTRY;
231 pmbe->link = NULL;
0c7b1df6
PM
232}
233
234/*
51becfd9 235 * Must be run uncached.
0c7b1df6 236 */
d53a0d33 237static void __set_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 238{
90e7d649
PM
239 /* Set V-bit */
240 __raw_writel(pmbe->ppn | pmbe->flags | PMB_V, mk_pmb_data(pmbe->entry));
241 __raw_writel(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
0c7b1df6
PM
242}
243
d53a0d33 244static void __clear_pmb_entry(struct pmb_entry *pmbe)
0c7b1df6 245{
2e450643
PM
246 unsigned long addr, data;
247 unsigned long addr_val, data_val;
0c7b1df6 248
2e450643
PM
249 addr = mk_pmb_addr(pmbe->entry);
250 data = mk_pmb_data(pmbe->entry);
0c7b1df6 251
2e450643
PM
252 addr_val = __raw_readl(addr);
253 data_val = __raw_readl(data);
0c7b1df6 254
2e450643
PM
255 /* Clear V-bit */
256 writel_uncached(addr_val & ~PMB_V, addr);
257 writel_uncached(data_val & ~PMB_V, data);
0c7b1df6
PM
258}
259
d53a0d33
PM
260static void set_pmb_entry(struct pmb_entry *pmbe)
261{
262 unsigned long flags;
263
264 spin_lock_irqsave(&pmbe->lock, flags);
265 __set_pmb_entry(pmbe);
266 spin_unlock_irqrestore(&pmbe->lock, flags);
267}
268
90e7d649
PM
269int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
270 unsigned long size, pgprot_t prot)
271{
272 return 0;
273}
d7cdc9e8 274
90e7d649
PM
275void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
276 pgprot_t prot, void *caller)
d7cdc9e8 277{
fc2bdefd 278 struct pmb_entry *pmbp, *pmbe;
90e7d649
PM
279 unsigned long pmb_flags;
280 int i, mapped;
281 unsigned long orig_addr, vaddr;
282 phys_addr_t offset, last_addr;
283 phys_addr_t align_mask;
284 unsigned long aligned;
285 struct vm_struct *area;
286
287 /*
288 * Small mappings need to go through the TLB.
289 */
290 if (size < SZ_16M)
291 return ERR_PTR(-EINVAL);
292 if (!pmb_prot_valid(prot))
293 return ERR_PTR(-EINVAL);
7bdda620 294
90e7d649
PM
295 pmbp = NULL;
296 pmb_flags = pgprot_to_pmb_flags(prot);
297 mapped = 0;
d7cdc9e8 298
90e7d649
PM
299 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
300 if (size >= pmb_sizes[i].size)
301 break;
0065b967 302
90e7d649
PM
303 last_addr = phys + size;
304 align_mask = ~(pmb_sizes[i].size - 1);
305 offset = phys & ~align_mask;
306 phys &= align_mask;
307 aligned = ALIGN(last_addr, pmb_sizes[i].size) - phys;
0065b967 308
90e7d649
PM
309 area = __get_vm_area_caller(aligned, VM_IOREMAP, uncached_end,
310 P3SEG, caller);
311 if (!area)
312 return NULL;
d7cdc9e8 313
90e7d649
PM
314 area->phys_addr = phys;
315 orig_addr = vaddr = (unsigned long)area->addr;
316
317 if (!pmb_addr_valid(vaddr, aligned))
318 return ERR_PTR(-EFAULT);
d7cdc9e8
PM
319
320again:
321 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
d53a0d33
PM
322 unsigned long flags;
323
d7cdc9e8
PM
324 if (size < pmb_sizes[i].size)
325 continue;
326
20b5014b
MF
327 pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag,
328 PMB_NO_ENTRY);
fc2bdefd 329 if (IS_ERR(pmbe)) {
90e7d649
PM
330 pmb_unmap_entry(pmbp, mapped);
331 return pmbe;
fc2bdefd 332 }
d7cdc9e8 333
d53a0d33
PM
334 spin_lock_irqsave(&pmbe->lock, flags);
335
90e7d649 336 pmbe->size = pmb_sizes[i].size;
d7cdc9e8 337
90e7d649 338 __set_pmb_entry(pmbe);
d7cdc9e8 339
90e7d649
PM
340 phys += pmbe->size;
341 vaddr += pmbe->size;
342 size -= pmbe->size;
d7813bc9 343
d7cdc9e8
PM
344 /*
345 * Link adjacent entries that span multiple PMB entries
346 * for easier tear-down.
347 */
d53a0d33
PM
348 if (likely(pmbp)) {
349 spin_lock(&pmbp->lock);
d7cdc9e8 350 pmbp->link = pmbe;
d53a0d33
PM
351 spin_unlock(&pmbp->lock);
352 }
d7cdc9e8
PM
353
354 pmbp = pmbe;
a2767cfb
MF
355
356 /*
357 * Instead of trying smaller sizes on every iteration
358 * (even if we succeed in allocating space), try using
359 * pmb_sizes[i].size again.
360 */
361 i--;
90e7d649 362 mapped++;
d53a0d33
PM
363
364 spin_unlock_irqrestore(&pmbe->lock, flags);
d7cdc9e8
PM
365 }
366
d53a0d33 367 if (size >= SZ_16M)
d7cdc9e8
PM
368 goto again;
369
90e7d649 370 return (void __iomem *)(offset + (char *)orig_addr);
d7cdc9e8
PM
371}
372
90e7d649 373int pmb_unmap(void __iomem *addr)
d7cdc9e8 374{
d53a0d33 375 struct pmb_entry *pmbe = NULL;
90e7d649
PM
376 unsigned long vaddr = (unsigned long __force)addr;
377 int i, found = 0;
d7cdc9e8 378
d53a0d33
PM
379 read_lock(&pmb_rwlock);
380
edd7de80 381 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 382 if (test_bit(i, pmb_map)) {
edd7de80 383 pmbe = &pmb_entry_list[i];
90e7d649
PM
384 if (pmbe->vpn == vaddr) {
385 found = 1;
edd7de80 386 break;
90e7d649 387 }
edd7de80
MF
388 }
389 }
d53a0d33
PM
390
391 read_unlock(&pmb_rwlock);
392
90e7d649
PM
393 if (found) {
394 pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
395 return 0;
396 }
d7cdc9e8 397
90e7d649 398 return -EINVAL;
d01447b3
PM
399}
400
401static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
402{
d7cdc9e8
PM
403 do {
404 struct pmb_entry *pmblink = pmbe;
405
067784f6
MF
406 /*
407 * We may be called before this pmb_entry has been
408 * entered into the PMB table via set_pmb_entry(), but
409 * that's OK because we've allocated a unique slot for
410 * this entry in pmb_alloc() (even if we haven't filled
411 * it yet).
412 *
d53a0d33 413 * Therefore, calling __clear_pmb_entry() is safe as no
067784f6
MF
414 * other mapping can be using that slot.
415 */
d53a0d33 416 __clear_pmb_entry(pmbe);
fc2bdefd 417
d7cdc9e8
PM
418 pmbe = pmblink->link;
419
420 pmb_free(pmblink);
d01447b3
PM
421 } while (pmbe && --depth);
422}
423
424static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
425{
426 unsigned long flags;
d53a0d33 427
d01447b3
PM
428 if (unlikely(!pmbe))
429 return;
430
431 write_lock_irqsave(&pmb_rwlock, flags);
432 __pmb_unmap_entry(pmbe, depth);
d53a0d33 433 write_unlock_irqrestore(&pmb_rwlock, flags);
d7cdc9e8
PM
434}
435
d01447b3 436static void __init pmb_notify(void)
20b5014b 437{
d01447b3 438 int i;
20b5014b 439
efd54ea3 440 pr_info("PMB: boot mappings:\n");
20b5014b 441
d01447b3
PM
442 read_lock(&pmb_rwlock);
443
444 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
445 struct pmb_entry *pmbe;
446
447 if (!test_bit(i, pmb_map))
448 continue;
449
450 pmbe = &pmb_entry_list[i];
451
452 pr_info(" 0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
453 pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
454 pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
455 }
456
457 read_unlock(&pmb_rwlock);
458}
459
460/*
461 * Sync our software copy of the PMB mappings with those in hardware. The
462 * mappings in the hardware PMB were either set up by the bootloader or
463 * very early on by the kernel.
464 */
465static void __init pmb_synchronize(void)
466{
467 struct pmb_entry *pmbp = NULL;
468 int i, j;
469
3d467676 470 /*
efd54ea3
PM
471 * Run through the initial boot mappings, log the established
472 * ones, and blow away anything that falls outside of the valid
473 * PPN range. Specifically, we only care about existing mappings
474 * that impact the cached/uncached sections.
3d467676 475 *
efd54ea3
PM
476 * Note that touching these can be a bit of a minefield; the boot
477 * loader can establish multi-page mappings with the same caching
478 * attributes, so we need to ensure that we aren't modifying a
479 * mapping that we're presently executing from, or may execute
480 * from in the case of straddling page boundaries.
3d467676 481 *
efd54ea3
PM
482 * In the future we will have to tidy up after the boot loader by
483 * jumping between the cached and uncached mappings and tearing
484 * down alternating mappings while executing from the other.
3d467676 485 */
51becfd9 486 for (i = 0; i < NR_PMB_ENTRIES; i++) {
3d467676
MF
487 unsigned long addr, data;
488 unsigned long addr_val, data_val;
efd54ea3 489 unsigned long ppn, vpn, flags;
d53a0d33 490 unsigned long irqflags;
d7813bc9 491 unsigned int size;
efd54ea3 492 struct pmb_entry *pmbe;
20b5014b 493
3d467676
MF
494 addr = mk_pmb_addr(i);
495 data = mk_pmb_data(i);
20b5014b 496
3d467676
MF
497 addr_val = __raw_readl(addr);
498 data_val = __raw_readl(data);
20b5014b 499
3d467676
MF
500 /*
501 * Skip over any bogus entries
502 */
503 if (!(data_val & PMB_V) || !(addr_val & PMB_V))
504 continue;
20b5014b 505
3d467676
MF
506 ppn = data_val & PMB_PFN_MASK;
507 vpn = addr_val & PMB_PFN_MASK;
a0ab3668 508
3d467676
MF
509 /*
510 * Only preserve in-range mappings.
511 */
efd54ea3 512 if (!pmb_ppn_in_range(ppn)) {
3d467676
MF
513 /*
514 * Invalidate anything out of bounds.
515 */
2e450643
PM
516 writel_uncached(addr_val & ~PMB_V, addr);
517 writel_uncached(data_val & ~PMB_V, data);
efd54ea3 518 continue;
3d467676 519 }
efd54ea3
PM
520
521 /*
522 * Update the caching attributes if necessary
523 */
524 if (data_val & PMB_C) {
0065b967
PM
525 data_val &= ~PMB_CACHE_MASK;
526 data_val |= pmb_cache_flags();
2e450643
PM
527
528 writel_uncached(data_val, data);
efd54ea3
PM
529 }
530
d7813bc9
PM
531 size = data_val & PMB_SZ_MASK;
532 flags = size | (data_val & PMB_CACHE_MASK);
efd54ea3
PM
533
534 pmbe = pmb_alloc(vpn, ppn, flags, i);
535 if (IS_ERR(pmbe)) {
536 WARN_ON_ONCE(1);
537 continue;
538 }
539
d53a0d33
PM
540 spin_lock_irqsave(&pmbe->lock, irqflags);
541
d7813bc9
PM
542 for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
543 if (pmb_sizes[j].flag == size)
544 pmbe->size = pmb_sizes[j].size;
545
d53a0d33
PM
546 if (pmbp) {
547 spin_lock(&pmbp->lock);
548
549 /*
550 * Compare the previous entry against the current one to
551 * see if the entries span a contiguous mapping. If so,
d01447b3
PM
552 * setup the entry links accordingly. Compound mappings
553 * are later coalesced.
d53a0d33 554 */
d01447b3 555 if (pmb_can_merge(pmbp, pmbe))
d53a0d33
PM
556 pmbp->link = pmbe;
557
558 spin_unlock(&pmbp->lock);
559 }
d7813bc9
PM
560
561 pmbp = pmbe;
562
d53a0d33 563 spin_unlock_irqrestore(&pmbe->lock, irqflags);
d01447b3
PM
564 }
565}
d53a0d33 566
d01447b3
PM
567static void __init pmb_merge(struct pmb_entry *head)
568{
569 unsigned long span, newsize;
570 struct pmb_entry *tail;
571 int i = 1, depth = 0;
572
573 span = newsize = head->size;
efd54ea3 574
d01447b3
PM
575 tail = head->link;
576 while (tail) {
577 span += tail->size;
578
579 if (pmb_size_valid(span)) {
580 newsize = span;
581 depth = i;
582 }
583
584 /* This is the end of the line.. */
585 if (!tail->link)
586 break;
587
588 tail = tail->link;
589 i++;
a0ab3668
PM
590 }
591
d01447b3
PM
592 /*
593 * The merged page size must be valid.
594 */
595 if (!pmb_size_valid(newsize))
596 return;
597
598 head->flags &= ~PMB_SZ_MASK;
599 head->flags |= pmb_size_to_flags(newsize);
600
601 head->size = newsize;
602
603 __pmb_unmap_entry(head->link, depth);
604 __set_pmb_entry(head);
a0ab3668 605}
a0ab3668 606
d01447b3 607static void __init pmb_coalesce(void)
a0ab3668 608{
d01447b3
PM
609 unsigned long flags;
610 int i;
611
612 write_lock_irqsave(&pmb_rwlock, flags);
613
614 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
615 struct pmb_entry *pmbe;
616
617 if (!test_bit(i, pmb_map))
618 continue;
619
620 pmbe = &pmb_entry_list[i];
621
622 /*
623 * We're only interested in compound mappings
624 */
625 if (!pmbe->link)
626 continue;
627
628 /*
629 * Nothing to do if it already uses the largest possible
630 * page size.
631 */
632 if (pmbe->size == SZ_512M)
633 continue;
634
635 pmb_merge(pmbe);
636 }
637
638 write_unlock_irqrestore(&pmb_rwlock, flags);
639}
640
641#ifdef CONFIG_UNCACHED_MAPPING
642static void __init pmb_resize(void)
643{
644 int i;
a0ab3668 645
a0ab3668 646 /*
d01447b3
PM
647 * If the uncached mapping was constructed by the kernel, it will
648 * already be a reasonable size.
a0ab3668 649 */
d01447b3
PM
650 if (uncached_size == SZ_16M)
651 return;
652
653 read_lock(&pmb_rwlock);
654
655 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
656 struct pmb_entry *pmbe;
657 unsigned long flags;
658
659 if (!test_bit(i, pmb_map))
660 continue;
661
662 pmbe = &pmb_entry_list[i];
663
664 if (pmbe->vpn != uncached_start)
665 continue;
666
667 /*
668 * Found it, now resize it.
669 */
670 spin_lock_irqsave(&pmbe->lock, flags);
671
672 pmbe->size = SZ_16M;
673 pmbe->flags &= ~PMB_SZ_MASK;
674 pmbe->flags |= pmb_size_to_flags(pmbe->size);
675
676 uncached_resize(pmbe->size);
677
678 __set_pmb_entry(pmbe);
679
680 spin_unlock_irqrestore(&pmbe->lock, flags);
681 }
682
683 read_lock(&pmb_rwlock);
684}
685#endif
686
687void __init pmb_init(void)
688{
689 /* Synchronize software state */
690 pmb_synchronize();
691
692 /* Attempt to combine compound mappings */
693 pmb_coalesce();
694
695#ifdef CONFIG_UNCACHED_MAPPING
696 /* Resize initial mappings, if necessary */
697 pmb_resize();
698#endif
699
700 /* Log them */
701 pmb_notify();
3d467676 702
2e450643 703 writel_uncached(0, PMB_IRMCR);
a0ab3668
PM
704
705 /* Flush out the TLB */
efd54ea3 706 __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
2e450643 707 ctrl_barrier();
20b5014b 708}
0c7b1df6 709
2efa53b2
PM
710bool __in_29bit_mode(void)
711{
712 return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
713}
714
0c7b1df6
PM
715static int pmb_seq_show(struct seq_file *file, void *iter)
716{
717 int i;
718
719 seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n"
720 "CB: Copy-Back, B: Buffered, UB: Unbuffered\n");
721 seq_printf(file, "ety vpn ppn size flags\n");
722
723 for (i = 0; i < NR_PMB_ENTRIES; i++) {
724 unsigned long addr, data;
725 unsigned int size;
726 char *sz_str = NULL;
727
9d56dd3b
PM
728 addr = __raw_readl(mk_pmb_addr(i));
729 data = __raw_readl(mk_pmb_data(i));
0c7b1df6
PM
730
731 size = data & PMB_SZ_MASK;
732 sz_str = (size == PMB_SZ_16M) ? " 16MB":
733 (size == PMB_SZ_64M) ? " 64MB":
734 (size == PMB_SZ_128M) ? "128MB":
735 "512MB";
736
737 /* 02: V 0x88 0x08 128MB C CB B */
738 seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n",
739 i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ',
740 (addr >> 24) & 0xff, (data >> 24) & 0xff,
741 sz_str, (data & PMB_C) ? 'C' : ' ',
742 (data & PMB_WT) ? "WT" : "CB",
743 (data & PMB_UB) ? "UB" : " B");
744 }
745
746 return 0;
747}
748
749static int pmb_debugfs_open(struct inode *inode, struct file *file)
750{
751 return single_open(file, pmb_seq_show, NULL);
752}
753
5dfe4c96 754static const struct file_operations pmb_debugfs_fops = {
0c7b1df6
PM
755 .owner = THIS_MODULE,
756 .open = pmb_debugfs_open,
757 .read = seq_read,
758 .llseek = seq_lseek,
45dabf14 759 .release = single_release,
0c7b1df6
PM
760};
761
762static int __init pmb_debugfs_init(void)
763{
764 struct dentry *dentry;
765
766 dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
b9e393c2 767 sh_debugfs_root, NULL, &pmb_debugfs_fops);
25627c7f
Z
768 if (!dentry)
769 return -ENOMEM;
0c7b1df6
PM
770 if (IS_ERR(dentry))
771 return PTR_ERR(dentry);
772
773 return 0;
774}
0c7b1df6 775postcore_initcall(pmb_debugfs_init);
a83c0b73
FV
776
777#ifdef CONFIG_PM
778static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
779{
780 static pm_message_t prev_state;
edd7de80 781 int i;
a83c0b73
FV
782
783 /* Restore the PMB after a resume from hibernation */
784 if (state.event == PM_EVENT_ON &&
785 prev_state.event == PM_EVENT_FREEZE) {
786 struct pmb_entry *pmbe;
d53a0d33
PM
787
788 read_lock(&pmb_rwlock);
789
edd7de80 790 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
51becfd9 791 if (test_bit(i, pmb_map)) {
edd7de80
MF
792 pmbe = &pmb_entry_list[i];
793 set_pmb_entry(pmbe);
794 }
795 }
d53a0d33
PM
796
797 read_unlock(&pmb_rwlock);
a83c0b73 798 }
d53a0d33 799
a83c0b73 800 prev_state = state;
d53a0d33 801
a83c0b73
FV
802 return 0;
803}
804
805static int pmb_sysdev_resume(struct sys_device *dev)
806{
807 return pmb_sysdev_suspend(dev, PMSG_ON);
808}
809
810static struct sysdev_driver pmb_sysdev_driver = {
811 .suspend = pmb_sysdev_suspend,
812 .resume = pmb_sysdev_resume,
813};
814
815static int __init pmb_sysdev_init(void)
816{
817 return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
818}
a83c0b73
FV
819subsys_initcall(pmb_sysdev_init);
820#endif
This page took 0.352527 seconds and 5 git commands to generate.