[deliverable/linux.git] / arch / sh / mm / tlb-flush.c

/*
 * TLB flushing operations for SH with an MMU.
 *
 *  Copyright (C) 1999  Niibe Yutaka
 *  Copyright (C) 2003 - 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	if (vma->vm_mm && vma->vm_mm->context.id != NO_CONTEXT) {
		unsigned long flags;
		unsigned long asid;
		unsigned long saved_asid = MMU_NO_ASID;

		asid = vma->vm_mm->context.id & MMU_CONTEXT_ASID_MASK;
		page &= PAGE_MASK;

		local_irq_save(flags);
		if (vma->vm_mm != current->mm) {
			saved_asid = get_asid();
			set_asid(asid);
		}
		__flush_tlb_page(asid, page);
		if (saved_asid != MMU_NO_ASID)
			set_asid(saved_asid);
		local_irq_restore(flags);
	}
}

void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
		     unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;

	if (mm->context.id != NO_CONTEXT) {
		unsigned long flags;
		int size;

		local_irq_save(flags);
		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
		if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
			mm->context.id = NO_CONTEXT;
			if (mm == current->mm)
				activate_context(mm);
		} else {
			unsigned long asid;
			unsigned long saved_asid = MMU_NO_ASID;

			asid = mm->context.id & MMU_CONTEXT_ASID_MASK;
			start &= PAGE_MASK;
			end += (PAGE_SIZE - 1);
			end &= PAGE_MASK;
			if (mm != current->mm) {
				saved_asid = get_asid();
				set_asid(asid);
			}
			while (start < end) {
				__flush_tlb_page(asid, start);
				start += PAGE_SIZE;
			}
			if (saved_asid != MMU_NO_ASID)
				set_asid(saved_asid);
		}
		local_irq_restore(flags);
	}
}

void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long flags;
	int size;

	local_irq_save(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
		flush_tlb_all();
	} else {
		unsigned long asid;
		unsigned long saved_asid = get_asid();

		asid = init_mm.context.id & MMU_CONTEXT_ASID_MASK;
		start &= PAGE_MASK;
		end += (PAGE_SIZE - 1);
		end &= PAGE_MASK;
		set_asid(asid);
		while (start < end) {
			__flush_tlb_page(asid, start);
			start += PAGE_SIZE;
		}
		set_asid(saved_asid);
	}
	local_irq_restore(flags);
}

void flush_tlb_mm(struct mm_struct *mm)
{
	/* Invalidate all TLB of this process. */
	/* Instead of invalidating each TLB, we get new MMU context. */
	if (mm->context.id != NO_CONTEXT) {
		unsigned long flags;

		local_irq_save(flags);
		mm->context.id = NO_CONTEXT;
		if (mm == current->mm)
			activate_context(mm);
		local_irq_restore(flags);
	}
}

void flush_tlb_all(void)
{
	unsigned long flags, status;

	/*
	 * Flush all the TLB.
	 *
	 * Write to the MMU control register's bit:
	 *	TF-bit for SH-3, TI-bit for SH-4.
	 *      It's same position, bit #2.
	 */
	local_irq_save(flags);
	status = ctrl_inl(MMUCR);
	status |= 0x04;
	ctrl_outl(status, MMUCR);
	ctrl_barrier();
	local_irq_restore(flags);
}

void update_mmu_cache(struct vm_area_struct *vma,
		      unsigned long address, pte_t pte)
{
	unsigned long flags;
	unsigned long pteval;
	unsigned long vpn;
	struct page *page;
	unsigned long pfn = pte_pfn(pte);
	struct address_space *mapping;

	if (!pfn_valid(pfn))
		return;

	page = pfn_to_page(pfn);
	mapping = page_mapping(page);
	if (mapping) {
		unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
		int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);

		if (dirty)
			__flush_wback_region((void *)P1SEGADDR(phys),
					     PAGE_SIZE);
	}

	local_irq_save(flags);

	/* Set PTEH register */
	vpn = (address & MMU_VPN_MASK) | get_asid();
	ctrl_outl(vpn, MMU_PTEH);

	pteval = pte_val(pte);

#ifdef CONFIG_CPU_HAS_PTEA
	/* Set PTEA register */
	/* TODO: make this look less hacky */
	ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
#endif

	/* Set PTEL register */
	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#if defined(CONFIG_SH_WRITETHROUGH) && defined(CONFIG_CPU_SH4)
	pteval |= _PAGE_WT;
#endif
	/* conveniently, we want all the software flags to be 0 anyway */
	ctrl_outl(pteval, MMU_PTEL);

	/* Load the TLB */
	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
	local_irq_restore(flags);
}
Commit	Line	Data
26ff6c11 PM	1	/*
	2	* TLB flushing operations for SH with an MMU.
	3	*
	4	* Copyright (C) 1999 Niibe Yutaka
26b7a78c	5	* Copyright (C) 2003 - 2006 Paul Mundt
26ff6c11 PM	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11	#include <linux/mm.h>
26b7a78c	12	#include <linux/io.h>
26ff6c11 PM	13	#include <asm/mmu_context.h>
26ff6c11 PM	14	#include <asm/tlbflush.h>
26b7a78c	15	#include <asm/cacheflush.h>
26ff6c11 PM	16
	17	void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	18	{
19f9a34f	19	if (vma->vm_mm && vma->vm_mm->context.id != NO_CONTEXT) {
26ff6c11 PM	20	unsigned long flags;
	21	unsigned long asid;
	22	unsigned long saved_asid = MMU_NO_ASID;
	23
19f9a34f	24	asid = vma->vm_mm->context.id & MMU_CONTEXT_ASID_MASK;
26ff6c11 PM	25	page &= PAGE_MASK;
	26
	27	local_irq_save(flags);
	28	if (vma->vm_mm != current->mm) {
	29	saved_asid = get_asid();
	30	set_asid(asid);
	31	}
	32	__flush_tlb_page(asid, page);
	33	if (saved_asid != MMU_NO_ASID)
	34	set_asid(saved_asid);
	35	local_irq_restore(flags);
	36	}
	37	}
	38
	39	void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	40	unsigned long end)
	41	{
	42	struct mm_struct *mm = vma->vm_mm;
	43
19f9a34f	44	if (mm->context.id != NO_CONTEXT) {
26ff6c11 PM	45	unsigned long flags;
	46	int size;
	47
	48	local_irq_save(flags);
	49	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	50	if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
19f9a34f	51	mm->context.id = NO_CONTEXT;
26ff6c11 PM	52	if (mm == current->mm)
	53	activate_context(mm);
	54	} else {
19f9a34f	55	unsigned long asid;
26ff6c11 PM	56	unsigned long saved_asid = MMU_NO_ASID;
26ff6c11 PM	57
19f9a34f	58	asid = mm->context.id & MMU_CONTEXT_ASID_MASK;
26ff6c11 PM	59	start &= PAGE_MASK;
	60	end += (PAGE_SIZE - 1);
	61	end &= PAGE_MASK;
	62	if (mm != current->mm) {
	63	saved_asid = get_asid();
	64	set_asid(asid);
	65	}
	66	while (start < end) {
	67	__flush_tlb_page(asid, start);
	68	start += PAGE_SIZE;
	69	}
	70	if (saved_asid != MMU_NO_ASID)
	71	set_asid(saved_asid);
	72	}
	73	local_irq_restore(flags);
	74	}
	75	}
	76
	77	void flush_tlb_kernel_range(unsigned long start, unsigned long end)
	78	{
	79	unsigned long flags;
	80	int size;
	81
	82	local_irq_save(flags);
	83	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	84	if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
	85	flush_tlb_all();
	86	} else {
19f9a34f	87	unsigned long asid;
26ff6c11 PM	88	unsigned long saved_asid = get_asid();
26ff6c11 PM	89
19f9a34f	90	asid = init_mm.context.id & MMU_CONTEXT_ASID_MASK;
26ff6c11 PM	91	start &= PAGE_MASK;
	92	end += (PAGE_SIZE - 1);
	93	end &= PAGE_MASK;
	94	set_asid(asid);
	95	while (start < end) {
	96	__flush_tlb_page(asid, start);
	97	start += PAGE_SIZE;
	98	}
	99	set_asid(saved_asid);
	100	}
	101	local_irq_restore(flags);
	102	}
	103
	104	void flush_tlb_mm(struct mm_struct *mm)
	105	{
	106	/* Invalidate all TLB of this process. */
	107	/* Instead of invalidating each TLB, we get new MMU context. */
19f9a34f	108	if (mm->context.id != NO_CONTEXT) {
26ff6c11 PM	109	unsigned long flags;
	110
	111	local_irq_save(flags);
19f9a34f	112	mm->context.id = NO_CONTEXT;
26ff6c11 PM	113	if (mm == current->mm)
	114	activate_context(mm);
	115	local_irq_restore(flags);
	116	}
	117	}
	118
	119	void flush_tlb_all(void)
	120	{
	121	unsigned long flags, status;
	122
	123	/*
	124	* Flush all the TLB.
	125	*
	126	* Write to the MMU control register's bit:
	127	* TF-bit for SH-3, TI-bit for SH-4.
	128	* It's same position, bit #2.
	129	*/
	130	local_irq_save(flags);
	131	status = ctrl_inl(MMUCR);
	132	status \|= 0x04;
	133	ctrl_outl(status, MMUCR);
	134	ctrl_barrier();
	135	local_irq_restore(flags);
	136	}
26b7a78c PM	137
	138	void update_mmu_cache(struct vm_area_struct *vma,
	139	unsigned long address, pte_t pte)
	140	{
	141	unsigned long flags;
	142	unsigned long pteval;
	143	unsigned long vpn;
	144	struct page *page;
	145	unsigned long pfn = pte_pfn(pte);
	146	struct address_space *mapping;
	147
	148	if (!pfn_valid(pfn))
	149	return;
	150
	151	page = pfn_to_page(pfn);
	152	mapping = page_mapping(page);
	153	if (mapping) {
	154	unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
	155	int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
	156
	157	if (dirty)
	158	__flush_wback_region((void *)P1SEGADDR(phys),
	159	PAGE_SIZE);
	160	}
	161
	162	local_irq_save(flags);
	163
	164	/* Set PTEH register */
	165	vpn = (address & MMU_VPN_MASK) \| get_asid();
	166	ctrl_outl(vpn, MMU_PTEH);
	167
	168	pteval = pte_val(pte);
	169
	170	#ifdef CONFIG_CPU_HAS_PTEA
	171	/* Set PTEA register */
	172	/* TODO: make this look less hacky */
	173	ctrl_outl(((pteval >> 28) & 0xe) \| (pteval & 0x1), MMU_PTEA);
	174	#endif
	175
	176	/* Set PTEL register */
	177	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
adac9570	178	#if defined(CONFIG_SH_WRITETHROUGH) && defined(CONFIG_CPU_SH4)
26b7a78c PM	179	pteval \|= _PAGE_WT;
	180	#endif
	181	/* conveniently, we want all the software flags to be 0 anyway */
	182	ctrl_outl(pteval, MMU_PTEL);
	183
	184	/* Load the TLB */
	185	asm volatile("ldtlb": /* no output / : / no input */ : "memory");
	186	local_irq_restore(flags);
	187	}